Philips p8xce598 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

P8xCE598

8-bit microcontroller with on-chip CAN

Product speciﬁcation Supersedes data of 1995 Oct 24 File under Integrated Circuits, IC18

1996 Jun 27

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION

2.1 Electromagnetic Compatibility (EMC)

2.2 Recommendation on ALE 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 7 MEMORY ORGANIZATION

7.1 Program Memory

7.2 Internal Data Memory

7.3 External Data Memory 8 I/O PORT STRUCTURE 9 PULSE WIDTH MODULATED OUTPUTS

(PWM)

9.1 Prescaler frequency control register (PWMP)

9.2 Pulse Width Register 0 (PWM0)

9.3 Pulse Width Register 1 (PWM1) 10 ANALOG-TO-DIGITAL CONVERTER (ADC)

10.1 ADC Control register (ADCON) 11 TIMERS/COUNTERS

11.1 Timer 0 and Timer 1

11.2 Timer T2 Capture and Compare Logic

11.3 Watchdog Timer (T3) 12 SERIAL I/O PORT: SIO0 (UART) 13 SERIAL I/O PORT: SIO1 (CAN)

13.1 On-chip CAN-controller

13.2 CAN Features

13.3 Interface between CPU and CAN

13.4 Hardware blocks of the CAN-controller

13.5 Control Segment and Message Buffer description

13.6 CAN 2.0A Protocol description

14 INTERRUPT SYSTEM

14.1 Interrupt Enable and Priority Registers

14.2 Interrupt Vectors

14.3 Interrupt Priority 15 POWER REDUCTION MODES

15.1 Power Control Register (PCON)

15.2 CAN Sleep Mode

15.3 Idle Mode

15.4 Power-down Mode 16 OSCILLATOR CIRCUITRY 17 RESET CIRCUITRY

17.1 Power-on Reset 18 INSTRUCTION SET

18.1 Addressing Modes

18.2 Instruction Set 19 ABSOLUTE MAXIMUM RATINGS 20 DC CHARACTERISTICS 21 AC CHARACTERISTICS 22 CAN APPLICATION INFORMATION

22.1 Latency time requirements

22.2 Connecting a P8xCE598 to a bus line (physical layer)

23 PACKAGE OUTLINES 24 SOLDERING

24.1 Introduction

24.2 Reflow soldering

24.3 Wave soldering

24.4 Repairing soldered joints

25 DEFINITIONS 26 LIFE SUPPORT APPLICATIONS

1996 Jun 27 2

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

1 FEATURES

• 80C51 central processing unit (CPU)

• 32 kbytes on-chip ROM,

externally expandible to 64 kbytes

• 2 × 256 bytes on-chip RAM, externally expandible to 64 kbytes

• Two standard 16-bit timers/counters

• One additional 16-bit timer/counter coupled to four

capture and three compare registers

• 10-bit ADC with 8 multiplexed analog inputs

• Two 8-bit resolution Pulse Width Modulated outputs

• 15 interrupt sources with 2 priority levels

(2 to 6 external interrupt sources possible)

• Five 8-bit I/O ports, plus one 8-bit input port shared with analog inputs

• CAN-controller (CAN = Controller Area Network) with DMA data transfer facility to internal RAM

• 1 Mbit/s CAN-controller with bus failure management facility

•1⁄2AVDD reference voltage

• Full-duplex UART compatible with the standard 80C51

• On-chip Watchdog Timer (WDT)

• 1.2 to 16 MHz clock frequency

• Improved Electromagnetic Compatibility (EMC).

2 GENERAL DESCRIPTION

The P8xCE598 is a single-chip 8-bit high-performance microcontroller with on-chip CAN-controller, derived from the 80C51 microcontroller family. It uses the powerful 80C51 instruction set. Figure 1 shows a block diagram of the P8xCE598.

The P8xCE598 is manufactured in an advanced CMOS process, and is designed for use in automotive and general industrial applications. In addition to the 80C51 standard features, the device provides a number of dedicated hardware functions for these applications.

Two versions of the P8xCE598 will be offered:

• P80CE598 (without ROM)

• P83CE598 (with ROM)

Hereafter these versions will be referred to as P8xCE598. The temperature range includes (max. f

= 16 MHz):

CLK

•−40 to +85 °C version, for general applications

•−40 to +125 °C version for automotive applications.

The P8xCE598 combines the functions of P8XC552 (microcontroller) and the PCA82C200 (Philips CAN-controller) with the following enhanced features:

• 32 kbytes Program Memory

• 2 × 256 bytes Data Memory

• DMA between CAN Transmit/Receive Buffer and

internal RAM.

The main differences to the P8xC552 microcontroller are:

• 32 kbytes programmable ROM (P8xC552 has 8 kbytes)

• Additional 256 bytes RAM

• A CAN-controller instead of the I2C-serial interface.

2.1 Electromagnetic Compatibility (EMC)

Primary attention is paid to the reduction of electromagnetic emission of the microcontroller P8xCE598. The following features reduce the electromagnetic emission and additionally improve the electromagnetic susceptibility:

• One analog part power supply pin (AV

) and one

analog part ground pin (AVSS), placed as a pair of pins on one side of the package (see Fig.3), providing power supply (+5V) and ground for ADC, CAN receiver and reference voltage.

• Four digital part supply voltage pins (V four digital part ground pins (V

SS1

to V

DD1 SS4

DD4

) are provided

) and

on the package. These pins, one VDD and one VSS as a pair of pins are placed on each of the four sides of the package to provide:

–V

DD1/VSS1

for internal logic (CPU, Timers/counters,

Memory, CAN, UART, ADC)

–V

DD2/VSS2

for Port 1, Port 3 and Port 4, and PWM0

and PWM1 outputs –V –V

DD3/VSS3 DD4/VSS4

for the on-chip oscillator for the Port 0, Port 2, ALE output and

PSEN output.

• External capacitors should be connected across associated V

DDx

and V

pins (i.e. V

SSx

DD1

and V

SS1

). Lead length should be as short as possible. Ceramic chip capacitors are recommended (100 nF).

• One CAN supply voltage pin (CVDD) and one CAN ground pin (CVSS) as a pair of pins placed on one side of the package providing (digital part) power supply (+5V) and ground for the CAN transmitter outputs.

• Internal decoupling capacitance improves the EMC radiation behaviour and the EMC immunity.

1996 Jun 27 3

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

2.2 Recommendation on ALE

For application that require no external memory or temporarily no external memory: the ALE output signal (pulses at a frequency of1⁄6f software control (bit 5 in PCON SFR: ‘RFI’); if disabled, no ALE pulse will occur. ALE pin will be pulled down internally, switching an external address latch to a quiet state. The MOVX instruction will still toggle ALE as a normal MOVX.

3 ORDERING INFORMATION

TYPE

NUMBER

Without ROM

P80CE598FFB P80CE598FHB

With ROM

P83CE598FFB P83CE598FHB

NAME DESCRIPTION VERSION

QFP80

) can be disabled under

OSC

PACKAGE

plastic quad ﬂat package; 80 leads (lead length 1.95 mm); body 14 × 20 × 2.7 mm; high stand-off height

ALE will retain its normal HIGH value during Idle mode and a LOW value during Power-down mode while in the ‘RFI reduction mode’.

Additionally during internal access ( normally when the address exceeds the internal Program Memory size. During external access (EA = 0) ALE will always toggle normally, whether the flag ‘RFI’ is set or not.

SOT318-1

EA = 1) ALE will toggle

TEMPERATURE

RANGE (°C)

−40 to +85

−40 to +125

−40 to +85

−40 to +125

FREQ.

(MHz)

1.2 to 16

1996 Jun 27 4

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

4 BLOCK DIAGRAM

CTX1

CRX1

REF

ref

ADC0 to ADC7

STADC

PWM0

PWM1

CTX0CRX0

(2)

1/2AV

(6) (2)

DATA

AUXILIARY

CAN

ADC

PWM

DUAL

RAM

256 x 8

MEMORY

RAM

256 x 8

MEMORY

DMA - BUS

INTERNAL BUS

P8xCE598

MLB228

T3

TIMER

WATCHDOG

OUTPUT

SELECTION

COMPARATOR

WITH

16-BIT

THREE

REGISTERS

COMPARATORS

T2

16-BIT

EVENT

TIMER/

COUNTER

FOUR

16-BIT

LATCHES

CAPTURE

RST EWCMSR0 to CMSR5

(5)(2)(2)(4)(4)

CMT0, CMT1

RT2

handbook, full pagewidth

Fig.1 Block diagram.

CT0I to CT3IP4P5RXDTXDP3P2P1P0

(7)

ROM

32K x 8

MEMORY

PROGRAM

CPU



core

T1 INT0 INT1

XTAL1

T0, T1

EVENT

TIMER/

TWO 16 - BIT

XTAL2

(4) (4) (4) (4)

80C51

COUNTERS

excluding

ROM/RAM

PSEN

(4)

1996 Jun 27 5

(4)

I/O

8-BIT

PORTS

UART

PORT

SERIAL

&

I/O PORTS

PARALLEL

(1)

AD0 to AD7

EXT. BUS

(3)

A8 to A15

(1) Alternative function of Port 0.

(2) Alternative function of Port 1.

(3) Alternative function of Port 2.

(4) Alternative function of Port 3.

(5) Alternative function of Port 4.

(6) Alternative function of Port 5.

(7) Not present in P80CE598.

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

5 PINNING

alternative function

handbook, full pagewidth

alternative function

ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7

CMSR0 CMSR1 CMSR2 CMSR3 CMSR4 CMSR5

CMT0 CMT1

STADC

PORT 5

PORT 4

XTAL1 XTAL2

PSEN

ALE

PWM0 PWM1

CRX0

CRX1

REF

ref+

ref –

RST

0 1



0 1 2 3 4 5 6 7

P8xCE598

MBD036

2 3 4 5 6 7

0 1 2 3 4 5 6 7

CV CV

V V

PORT 0

PORT 1

PORT 2

PORT 3

SS DD

AD0 AD1 AD2

LOW ORDER

AD3

ADDRESS

AD4

DATA BUS

AD5 AD6 AD7

CT0I/INT2 CT1I/INT3 CT2I/INT4 CT3I/INT5

T2 RT2 CTX0 CTX1

A8 A9 A10

HIGH ORDER

A11 A12 A13 A14 A15

RXD/DATA

TXD/CLOCK INT0

INT1 T0

T1 WR RD

AND

ADDRESS

BUS

Fig.2 Pin functions.

1996 Jun 27 6

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598



handbook, full pagewidth

P5.7/ADC7 P5.6/ADC6 P5.5/ADC5 P5.4/ADC4 P5.3/ADC3 P5.2/ADC2 P5.1/ADC1 P5.0/ADC0

ref

SS1

DD1

STADC

PWM0

CRX1

CRX0 80

79 1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16

REF 78

SS4

V 77

DD4

P0.1/AD1

P0.0/AD0 75

P0.3/AD3

P0.2/AD2

P8xCE598

P0.5/AD5

P0.4/AD4

P0.7/AD7

P0.6/AD6 69

n.c. 67

n.c. 66

64 63 62

61 60 59 58 57 56 55 54 53 52 51 50 49

ALE PSEN P2.7/A15 P2.6/A14

P2.5/A13

P2.4/A12 P2.3/A11 P2.2/A10

P2.1/A09 P2.0/A08

SS3

DD3 XTAL1 XTAL2 n.c. n.c.



PWM1

n.c.

19 20 21 22 23 24

P4.6/CMT0

P4.5/CMSR5

DD2

P4.7/CMT1

SS2

RST

P1.0/CT0I/INT2

P4.0/CMSR0 P4.1/CMSR1 P4.2/CMSR2 P4.3/CMSR3

P4.4/CMSR4

Fig.3 Pin configuration QFP80/SOT318-1.

1996 Jun 27 7

P1.1/CT1I/INT3

P1.2/CT2I/INT4

P1.3/CT3I/INT5

P1.4/T2

P1.5/RT2

P1.6/CTX0

P1.7/CTX1

48 47 46 45 44 43 42 41

P3.7/RD

P3.6/WR P3.5/T1

P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1/TXD

P3.0/RXD

MLB229

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

Table 1 Pin description for single function pins (SOT318-1 and SOT351-1; see note 1)

SYMBOL PIN DESCRIPTION

DD1

DD2

DD3

DD4

STADC 15 Start ADC operation. Input starting analog-to-digital conversion (note 2). This pin must not ﬂoat. PWM0 16 Pulse width modulation output 0. PMW1 17 Pulse width modulation output 1. EW 18 Enable Watchdog Timer (WDT): enable for T3 Watchdog Timer and disable Power-down mode.

RST 30 Reset: input to reset the P8xCE598 (note 3). CV

XTAL2 51 Crystal pin 2: output of the inverting ampliﬁer that forms the oscillator.

XTAL1 52 Crystal pin 1: input to the inverting ampliﬁer that forms the oscillator, and input to the internal clock

SS1

SS2

SS3

SS4

PSEN 63 Program Store Enable: Read strobe to external Program Memory (active LOW).

ALE 64 Address Latch Enable: latches the Low-byte of the address during accesses to external memory

EA 65 External Access input. See note 5. REF 78 CRX1 79 Inputs from the CAN-bus line to the differential input comparator of the on-chip CAN-controller CRX0 80 AV

REF−

REF+

n.c. 23,

14 Power supply, digital part: for internal logic (CPU, Timers/counters, Memory, CAN, UART, ADC). 28 Power supply, digital part: for Port 1, Port 3, Port 4, PWM0 and PWM1 outputs. 53 Power supply, digital part: for the on-chip oscillator. 76 Power supply, digital part: for Port 0, Port 2, ALE output and PSEN output.

This pin must not ﬂoat.

37 Ground potential for the CAN transmitter outputs. 40 Power supply (+5V) for the CAN transmitter outputs.

When an external clock oscillator is used this pin is left open-circuit.

generator. Receives the external clock oscillator signal, when an external oscillator is used. 13 Ground, digital part: for internal logic (CPU, Timers/Counters, Memory, CAN, UART, ADC). 29 Ground, digital part: for Port 1, Port 3 and Port 4, and PWM0 and PWM1 outputs. 54 Ground, digital part: for the on-chip oscillator. 77 Ground, digital part: for the Port 0, Port 2, ALE output and PSEN output.

Drive: 8 × LSTTL inputs.

(note 4). Drive: 8 × LSTTL inputs; handles CMOS inputs without an external pull-up.

⁄2AVDD reference voltage output respectively input (note 6).

(note 7).

1 Low-end of ADC (analog-to-digital conversion) reference resistor. 2 High-end of ADC (analog-to-digital conversion) reference resistor (note 8). 3 Ground, analog part. For ADC, CAN receiver and reference voltage. 4 Power supply, analog part (+5 V). For ADC, CAN receiver and reference voltage.

No connection.

49, 50, 66,

Notes

1. To avoid a ‘latch up’ effect at power-on: VSS− 0.5 V < ‘voltage on any pin at any time’ < VDD+ 0.5 V.

2. Triggered by a rising edge. ADC operation can also be started by software.

3. RST also provides a reset pulse as output when timer T3 overﬂows or after a CAN wake-up from Power-down.

1996 Jun 27 8

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

4. ALE is activated every six oscillator periods. During an external data memory access one ALE pulse is skipped.

5. See Section 7.1, Table 3 for EA operation. For P83CE598 microcontrollers specified with the option ‘ROM-code protection’, the EA pin is latched during reset and is ‘don't care’ after reset, regardless of whether the ROM-code protection is selected or not.

6. Pin 78, REF: a) Selection of input respectively output dependent of CAN Control Register bit 5 (CR.5; see Section 13.5.3

Table 32). b) If the internal reference is used, then REF should be connected to AVSS via a capacitor with a value of ≥ 10 nF. c) After an external reset (RST = HIGH) the internal1⁄2AVDD source is activated and, REF is a reference output. d) If the CAN-controller is in the reset state, e.g. after an external reset, then the1⁄2AVDD source is switched off

during Power-down mode.

7. CAN Bus line: a) CRX0 level > CRX1 level is interpreted as a logic 1 (recessive). b) CRX0 level < CRX1 level is interpreted as a logic 0 (dominant).

8. The level of AV

must be higher than that of AV

REF+

REF−

Table 2 Pin description for pins with alternative functions (SOT318-2 and SOT351-1; see note 1)

SYMBOL

DEFAULT ALTERNATIVE

Port 4

P4.0 to P4.7 19 to 22, 24 to 27 8-bit quasi-bidirectional I/O port.

CMSR0 19 Compare and Set/Reset outputs for TimerT2. CMSR1 20 CMSR2 21 CMSR3 22 CMSR4 24 CMSR5 25 CMT0 26 Compare and toggle outputs for TimerT2. CMT1 27

Port 1

P1.0 to P1.7 31 to 36, 38 to 39 8-bit quasi-bidirectional I/O port.

CT0I/INT2 31 Capture timer inputs for TimerT2, CT1I/INT3 32 CT2I/INT4 33 CT3I/INT5 34 T2 35 T2 event input (rising edge triggered). RT2 36 T2 timer reset input (rising edge triggered). CTX0 38 CAN transmitter output 0 (note 2). CTX1 39 CAN transmitter output 1 (note 2).

PIN DESCRIPTION

or External interrupt inputs 2to5.

1996 Jun 27 9

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

SYMBOL

DEFAULT ALTERNATIVE

Port 3

P3.0 to P3.7 41 to 48 8-bit quasi-bidirectional I/O port.

RXD 41 Serial Input Port. TXD 42 Serial Output Port. INT0 43 External interrupt input 0. INT1 44 External interrupt input 1. T0 45 Timer 0 external input. T1 46 Timer 1 external input. WR 47 External Data Memory Write strobe. RD 48 External Data Memory Read strobe.

Port 2 (Sink/source: 1 × TTL = 4 × LSTTL inputs)

P2.0 to P2.7 55 to 62 8-bit quasi-bidirectional I/O port.

A08 to A15 High-order address byte for external memory.

Port 0 (Sink/source: 8 × LSTTL inputs)

P0.7 to P0.0 68 to 75 8-bit open drain bidirectional I/O port.

AD7 to AD0 Multiplexed Low-order address and Data bus for

PIN DESCRIPTION

external memory.

Port 5

P5.7 to P5.0 5 to 12 8-bit input port.

ADC7 to ADC0 8 input channels to ADC.

Notes

1. To avoid a ‘latch up’ effect at power-on: VSS− 0.5 V < ‘voltage on any pin at any time’ < VDD+ 0.5 V.

2. If the CAN-controller is in the reset state (e.g. after a power-up reset; CAN Control Register bit CR.0; see Section 13.5.3 Table 32, the CAN transmitter outputs are floating and the pins P1.6 and P1.7 can be used as open-drain port pins. After a power-up reset the port data is HIGH, leaving the pins P1.6 and P1.7 floating.

1996 Jun 27 10

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

6 FUNCTIONAL DESCRIPTION

The P8xCE598 functions will be described as shown in the following overview:

• Memory organization

• I/O Port structure

• Pulse Width Modulated outputs

• Analog-to-Digital Converter

• Timers/Counters

• Serial I/O Ports

• Interrupt system

• Power reduction modes

• Oscillator circuitry

• Reset circuitry

• Instruction Set

• EMC (see Section 2.1).

handbook, full pagewidth

64K

7 MEMORY ORGANIZATION

The Central Processing Unit (CPU) manipulates operands in three memory spaces (see Fig.4) as follows:

• 32 kbytes internal, resp. 64 kbytes external Program Memory

• 512 bytes internal Data Memory MAIN- and AUXILIARY RAM.

• Up to 64 kbytes external Data Memory (with 256 bytes residing in the internal AUXILIARY RAM).

64K

32767

EXTERNAL

32768

INTERNAL

(EA = 1)

PROGRAM MEMORY

EXTERNAL

(EA = 0)

OVERLAPPED SPACE

255

INDIRECT ONLY

127

DIRECT AND

INDIRECT

MAIN RAM

INTERNAL DATA MEMORY

Fig.4 Memory map.

SFRs

AUXILIARY

RAM

MLB230

256

EXTERNAL

DATA MEMORY

1996 Jun 27 11

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

7.1 Program Memory

The Program Memory of the P8xCE598 consists of 32 kbytes ROM on-chip, externally expandible up to 64 kbytes.

Table 3 Instruction fetch controlled by

EA (note 1)

DURING RESET

LATCHED TO:

H − internal Program Memory (note 2) 0000H → 7FFFH H − external Program Memory 8000H → FFFFH L − 0000H → FFFFH

− ‘don’t care’ −−

Notes

1. This implementation prevents reading of the internal program code by switching from external Program Memory during a MOVC instruction.

2. By setting a security bit the internal Program Memory content is protected, which means it cannot be read out. If the security bit has been set to LOW there are no restrictions for the MOVC instruction.

7.2 Internal Data Memory

The internal Data Memory is physically built-up and accessible as shown in Table 4 (see Fig.5).

Table 4 Internal Data Memory size and address mode

INTERNAL

DATA MEMORY

MAIN RAM (note 1)

AUXILIARY RAM (note 2)

SFRs (note 3) 128 bytes 128 to 255 X −−

AFTER RESET

SIZE LOCATION

256 bytes 0 to 127 X X Address pointers are R0 and R1 of the

256 bytes 0 to 255 − X Address pointers are R0 and R1 of the

INSTRUCTIONS FETCHED FROM:

ADDRESS MODE

DIRECT INDIRECT

128 to 255 − X

ADDRESS

LOCATION

POINTERS

selected register bank.

selected register bank and the DPTR.

Notes

1. MAIN RAM can be addressed directly and indirectly as in the 80C51.

2. AUXILIARY RAM (0 to 255): a) Is indirectly addressable in the same way as the external Data Memory with MOVX instructions. b) Access will not affect the ports P0, P2, P3.6 and P3.7 during internal program execution.

3. SFRs = Special Function Registers.

1996 Jun 27 12

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

7.2.1 MAIN RAM

Four 8-bit register banks occupy the lower RAM area,

• BANK 0: location 0 to 7

• BANK 1: location 8 to 15

• BANK 2: location 16 to 23

• BANK 4: location 24 to 31.

Only one of these banks may be enabled at the same time. The next 16 bytes, locations 32 through 45, contains

128 directly addressable bit locations. The stack can be located anywhere in the internal Main

RAM address space. The stack depth is only limited by the internal RAM space available. All registers except the program counter and the four 8-bit register banks reside in the SFR address space.

7.3 External Data Memory

An access to external Data Memory locations higher than 255 will be performed with the MOVX @DPTR instructions in the same way as in the 80C51 structure, i.e.with P0 and P2 as data/address bus and P3.6 and P3.7 as Write and Read strobe signals.

Note that these external Data Memory locations cannot be accessed with R0 or R1 as address pointer.

7FH

(MSB) (LSB)

2FH

7F 7E 7D 7C 7B 7A 79 78

2EH

77 76 75 74 73 72 71 70

2DH

6F 6E 6D 6C 6B 6A 69 68

2CH

67 66 65 64 63 62 61 60

2BH

5F 5E 5D 5C 5B 5A 59 58

2AH

57 56 55 54 53 52 51 50

29H

4F 4E 4D 4C 4B 4A 49 48

28H

47 46 45 44 43 42 41 40

27H

3F 3E 3D 3C 3B 3A 39 38

26H

37 36 35 34 33 32 31 30

25H

2F 2E 2D 2C 2B 2A 29 28

24H

27 26 25 24 23 22 21 20

23H

1F 1E 1D 1C 1B 1A 19 18

22H

17 16 15 14 13 12 11 10

21H

0F 0E 0D 0C 0B 0A 09 08

20H

07 06 05 04 03 02 01 00

1FH

BANK 3

18H 17H

BANK 2

10H 0FH

BANK 1

08H 07H

BANK 0

00H

127

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

24 23

16 15

8 7

MGA152

1996 Jun 27 13

Fig.5 Internal MAIN RAM bit addresses.

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

DIRECT

handbook, full pagewidth

MNEMONIC

BIT ADDRESS

BYTE

ADDRESS (HEX)

T3 PWMP PWM1 PWM0

IP1

RTE

STE # TMH2 # TML2 CTCON

TM2CON

IEN1

ACC

CANADR

CANDAT

CANCON

CANSTA

PSW # CTH3 # CTH2 # CTH1 # CTH0

CMH2 CMH1 CMH0

TM2IR

FFH FEH FDH FCH

FEFF FD FC FB FA F9 F8

F6F7 F5 F4 F3 F2 F1 F0

EEEF ED EC EB EA E9 E8

E6E7 E5 E4 E3 E2 E1 E0

DEDF DD DC DB DA D9 D8

D6D7 D5 D4 D3 D2 D1 D0

CECF CD CC CB CA C9 C8

F8H

F0H EFH EEH EDH ECH EBH EAH

E8H

E0H

DBH DAH D9H D8H

D0H CFH CEH

CDH CCH

CBH CAH C9H C8H

SFRs containing

directly addressable

bits

# ADCH

ADCON

# P5

# denotes read-only registers

C6C7 C5 C4 C3 C2 C1 C0

Fig.6 Special Function Register memory map (a).

1996 Jun 27 14

C6H C5H C4H

C0H

MGA150

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

DIRECT

handbook, full pagewidth

MNEMONIC

BIT ADDRESS

BYTE

ADDRESS (HEX)

IP0

P3 # CTL3 # CTL2 # CTL1 # CTL0

CML2 CML1

CML0

IEN0

S0BUF

S0CON

TH1 TH0 TL1 TL0

TMOD

TCON

PCON

BEBF BD BC BB BA B9 B8

B6B7 B5 B4 B3 B2 B1 B0

AEAF AD AC AB AA A9 A8

A6A7 A5 A4 A3 A2 A1 A0

9E9F 9D 9C 9B 9A 99 98

9697 95 94 93 92 91 90

8E8F 8D 8C 8B 8A 89 88

B8H

B0H AFH AEH ADH ACH ABH AAH A9H A8H

A0H

99H 98H

90H

8DH 8CH

8BH 8AH 89H 88H 87H

SFRs containing

directly addressable

bits

DPH

DPL

SP P0

# denotes read-only registers

8687 85 84 83 82 81 80

Fig.7 Special Function Register memory map (b).

1996 Jun 27 15

83H 82H 81H 80H

MGA151

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

8 I/O PORT STRUCTURE

The P8xCE598 has six 8-bit parallel ports: Port 0 to Port 5. In addition to the standard 8-bit parallel ports, the I/O facilities also include a number of special I/O lines. The use of a Port 1, Port 3 or Port 4 pins as an alternative function is carried out automatically provided the associated SFR bit is set HIGH.

Table 5 Default Port functions

PORT TYPE FUNCTION REMARKS

Port 0 I/O The same as in the 80C51 Except for the additional functions of P1.6 and Port 1 I/O Port 2 I/O Port 3 I/O Port 4 I/O Parallel I/O port Parallel I/O function is identical to Port1, 2 and 3. Port 5 I Parallel input port with an input function only May be used as normal inputs if the ADC function

Table 6 Alternative Port functions

P1.7.

is inoperative.

PORT TYPE FUNCTION REMARKS

Port 0 I/O Multiplexed Low-order address and

Data bus for external memory (AD7 to AD0)

Port 1 I/O Capture timer inputs for Timer T2

(CT0I to CT3I), or External interrupt request inputs (INT2 to INT5)

T2 event input (T2) External counter input. T2 timer reset input (RT2) External counter reset input. CAN transmitter output 0 (CTX0) CTX0 and CTX1 outputs of the CAN interface CAN transmitter output 1 (CTX1)

Port 2 I/O High-order address byte for external memory

(A08 to A15)

Port 3 I/O Serial Input Port (RXD) Receiver input of serial port SIO0 (UART).

Serial Output Port (TXD) Transmitter output of serial port SIO0 (UART). External interrupt ( External interrupt ( Timer 0 external input (T0) Counter inputs. Timer 1 external input (T1) External data memory Write strobe ( External data memory Read strobe (

Port 4 I/O Compare and Set/Reset outputs

(CMSR0 to CMSR5) Compare and toggle outputs (CMT0, CMT1)

Port 5 I Input channels to ADC (ADC7 to ADC0) Port 5 may be used in conjunction with the ADC

INT0) External interrupt request inputs. INT1)

WR) Control signal to write to external Data Memory.

RD) Control signal to read from external Data Memory.

Provides the multiplexed Low-order address and data bus used for expanding the P8xCE598 with standard memories and peripherals.

External interrupt request inputs, if capture information is not utilized.

(note 1). Port 2 provides the High-order address bus when

the P8xCE598 is expanded with external Program Memory and/or external Data Memory.

Can be conﬁgured to provide signals indicating a match between Timer counter T2 and its compare registers.

interface (note 2).

1996 Jun 27 16

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

Notes to the Alternative Port functions

1. Port lines P1.6 and P1.7 may be selected as CTX0 and CTX1 outputs of the serial port SIO1 (CAN). After reset P1.6 and P1.7 may be used as normal I/O ports, if the CAN interface is not used.

2. Unused analog inputs can be used as digital inputs. As Port 5 lines may be used as inputs to the ADC, these digital inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines when driven by analog signals. Channel-to-channel crosstalk should be taken into consideration when both digital and analog signals are simultaneously input to Port 5 (see Chapter 20).

handbook, full pagewidth

from port latch

input data

read port pin

2 oscillator

periods

strong pull-up

INPUT

BUFFER

Fig.8 I/O buffers in the P8xCE598 (P1.0 to P1.5, Ports 2, 3, and 4).

9 PULSE WIDTH MODULATED OUTPUTS (PWM)

Two Pulse Width Modulated (PWM) output channels are available with the P8xCE598. These channels provide output pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP which generates the clock for the counter. Both the prescaler and counter are common to both PWM channels. The 8-bit counter counts modulo 255 i.e. from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two registers: PWM0 and PWM1.

Provided the contents of either of these registers is greater than the counter value, the output of PWM0 or PWM1 is set LOW. If the contents of these register are equal to, or less than the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the register PWM0 and PWM1. The pulse-width-ratio is in

255

⁄

and may be programmed in

255

the range of 0 to increments of1⁄

+5 V

The repetition frequency f given by:

PWM

-------------------------------------------------------------2PWMP1+()× 255×

I/O PIN

PORT

1, 2, 3 or 4

MGA153

, at the PWMn outputs is

PWM

CLK

When using an oscillator frequency of 16 MHz, for example, the above formula would give a repetition frequency range of 123 Hz to 31.4 kHz.

By loading the PWM registers with either 00H or FFH, the PWM outputs can be retained at a constant HIGH or LOW level respectively. When loading FFH to the PWM registers, the 8-bit counter will never actually reach this (FFH) value. Both output pins

PWMn are driven by push-pull drivers,

and are not shared with any other function.

1996 Jun 27 17

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

9.1 Prescaler frequency control register (PWMP)

Table 7 Prescaler frequency control register (address FEH)

76543210

PWMP.7 PWMP.6 PWMP.5 PWMP.4 PWMP.3 PWMP.2 PWMP.1 PWMP.0

Table 8 Description of PWMP bits

BIT SYMBOL FUNCTION

7 to 0 PWMP.7

PWMP.0

9.2 Pulse Width Register 0 (PWM0)

Table 9 Pulse Width Register (address FCH)

76543210

PWM0.7 PWM0.6 PWM0.5 PWM0.4 PWM0.3 PWM0.2 PWM0.1 PWM0.0

Prescaler division factor. The Prescaler division factor = (PWMP) + 1

Table 10 Description of PWM0 bits

BIT SYMBOL FUNCTION

7 to 0 PWM0.7

PWM0.0

9.3 Pulse Width Register 1 (PWM1)

Table 11 Pulse width register (address FDH)

76543210

PWM1.7 PWM1.6 PWM1.5 PWM1.4 PWM1.3 PWM1.2 PWM1.1 PWM1.0

Table 12 Description of PWM1 bits

BIT SYMBOL FUNCTION

7 to 0 PWM1.7

PWM1.0

Pulse width ratio.

LOW/HIGH ratio of PWMn signals

Pulse width ratio.

LOW/HIGH ratio of PWMn signals

PWMn()

----------------------------------------- 255 PWMn()–

PWMn()

----------------------------------------- 255 PWMn()–

1996 Jun 27 18

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

handbook, full pagewidth

PWM0

I N T

E R N A L

 B U S

clk

PRESCALER

PWMP

Fig.9 Functional diagram of Pulse Width Modulated outputs.

10 ANALOG-TO-DIGITAL CONVERTER (ADC)

The analog input circuitry consists of an 8-input analog multiplexer and an ADC with 10-bit resolution. The analog reference voltage and analog power supplies are connected via separate input pins. The conversion takes 50 machine cycles i.e. 37.5 µs at 16 MHz oscillator frequency. The input voltage swing is from 0 V to AVDD. The ADC is controlled using the ADCON control register. Register bits ADCON.0 to ADCON.2 select the input channels of the analog multiplexer (see Fig.10). The completion of the 10-bit analog-to-digital conversion is flagged by ADCI in the ADCON register and the result is stored in the SFR ADCH (upper 8-bits) and the 2 lower bits (ADC.1 and ADC.0) in register ADCON.

An analog-to-digital conversion in progress is unaffected by an external or software ADC start. The result of a completed conversion remains unchanged provided ADCI = HIGH. While ADCI or ADCS are HIGH, a new ADC START will be blocked and consequently lost. An analog-to-digital conversion already in progress is aborted when the Idle or Power-down mode is entered.

8-BIT COMPARATOR

8-BIT COUNTER1/2

8-BIT COMPARATOR

PWM1

OUTPUT BUFFER

PWM0

PWM1

MGA154

The result of a completed conversion (ADCI = HIGH) remains unaffected during the Idle mode. The LOW-to-HIGH transition of STADC is recognized at the end of a machine cycle and the conversion commences at the beginning of the next cycle. When a conversion is initiated by software, the conversion starts at the beginning of the machine cycle following the instruction that sets ADCS.

The next two machine cycles are used to initiate the converter. At the end of this first cycle, the ADCS status flag is set to HIGH while the conversion is in progress. Sampling of the analog input commences at the end of the second cycle.

During the next eight machine cycles, the voltage at the previously selected pin of Port 5 is sampled and this input voltage should be stable in order to obtain a useful sample. In any case, the input voltage slew rate must be less than 10 V/ms (5 V conversion range) in order to prevent an undefined result. The conversion takes four machine cycles per bit.

1996 Jun 27 19

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

10.1 ADC Control register (ADCON) Table 13 ADC Control register (address C5H)

76543210

ADC.1 ADC.0 ADEX ADCI ADCS AADR2 AADR1 AADR0

Table 14 Description of the ADCON bits

BIT SYMBOL FUNCTION

7 ADC.1 Bit 1 of ADC converted value. 6 ADC.0 Bit 0 of ADC converted value. 5 ADEX Enable external start of conversion by STADC. If ADEX is:

LOW, then conversion cannot be started externally by STADC (only by software by setting ADCS)

HIGH, then conversion can be started externally by a rising edge on STADC or externally.

4 ADCI ADC interrupt ﬂag. This ﬂag is set when an analog-to-digital conversion result is ready

to be read. If enabled, an interrupt is invoked. The ﬂag must be cleared by software. It cannot be set by software (see Table 15).

3 ADCS ADC start and status. Setting this bit starts an analog-to-digital conversion. It may be

set by software or by the external signal STADC. The ADC logic ensures that this signal is HIGH while the ADC is busy. On completion of the conversion, ADCS is reset at the same time the interrupt ﬂag ADCI is set. ADCS can not be reset by software (see

Table 15). 2 AADR2 Analog input select. This binary coded address selects one of the eight analog port 1 AADR1 0 AADR0

pins of P5 to be input to the converter. It can only be changed when ADCI and ADCS

are both LOW. AADR2 is the MSB (e.g. 100B selects the analog input channel ADC4).

Table 15 ADCI and ADCS operating modes If ADCI is cleared by software while ADCS is set at the same time a new analog-to-digital conversion with the same

channel-number may be started. It is recommended to reset ADCI before ADCS is set.

ADCI ADCS OPERATION

0 0 ADC not busy, a conversion can be started. 0 1 ADC busy, start of a new conversion is blocked. 1 X (don’t care) Conversion completed (note 1).

Note

1. Start of a new conversion requires ADCI = 0.

1996 Jun 27 20

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

andbook, full pagewidth

ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7

ANALOG INPUT

MULTIPLEXER

ADCON

10-BIT A/D

CONVERTER

1234567012345670

INTERNAL BUS

Fig.10 Functional diagram of analog input.

STADC

analog reference

supply (analog part)

ground (analog part)

ADCH

MGA155

1996 Jun 27 21

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

11 TIMERS/COUNTERS

The P8xCE598 contains:

• Three 16-bit timer/event counters: Timer 0, Timer 1 and Timer 2

• One 8-bit timer, T3 (Watchdog WDT).

11.1 Timer 0 and Timer 1

Timer 0 and Timer 1 may be programmed to carry out the following functions:

• Measure time intervals and pulse durations

• Count events

• Generate interrupt requests.

Timer 0 and Timer 1 can be programmed independently to operate in 3 modes:

Mode 0 8-bit timer or 8-bit counter each with divide-by-32

prescaler. Mode 1 16-bit timer-interval or event counter. Mode 2 8-bit timer-interval or event counter with

automatic reload upon overflow. Timer 0 can be programmed to operate in an additional

mode as follows: Mode 3 one 8-bit time-interval or event counter and one

8-bit timer-interval counter. When Timer 0 is in Mode 3, Timer 1 can be programmed

to operate in Modes 0, 1 or 2 but cannot set an interrupt flag or generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port baud-rate generator.

The frequency handling range of these counters with a 16 MHz crystal is as follows:

• In the timer function, the timer is incremented at a

frequency of 1.33 MHz (

⁄12 of the oscillator frequency)

• 0 Hz to an upper limit of 0.66 MHz (1⁄24 of the oscillator

frequency) when programmed for external inputs.

Both internal and external inputs can be gated to the counter by a second external source for directly measuring pulse durations. When configured as a counter, the register is incremented on every falling edge on the corresponding input pin, T0 or T1.

The earliest moment, when the incremented register value can be read is during the second machine cycle following the machine cycle within which the incrementing pulse occurred.The counters are started and stopped under software control. Each one sets its interrupt request flag

when it overflows from all HIGHs to all LOWs (or automatic reload value), with the exception of Mode 3 as previously described.

11.2 Timer T2 Capture and Compare Logic

Timer T2 is a 16-bit timer/counter which has capture and compare facilities (see Fig.11).

The 16-bit timer/counter is clocked via a prescaler with a programmable division factor of 1, 2, 4 or 8. The input of

the prescaler is clocked with

⁄12 of the oscillator

frequency, or by an external source connected to the T2 input, or it is switched off. The maximum repetition rate of the external clock source is1⁄12f

, twice that of Timer 0

CLK

and Timer 1. The prescaler is incremented on a rising edge. It is cleared if its division factor or its input source is changed, or if the timer/counter is reset.

T2 is readable ‘on the fly’, without any extra read latches; this means that software precautions have to be taken against misinterpretation at overflow from least to most significant byte while T2 is being read. T2 is not loadable and is reset by the RST signal or at the positive edge of the input signal RT2, if enabled. In the Idle mode the timer/counter and prescaler are reset and halted.

T2 is connected to four 16-bit Capture Registers: CT0, CT1, CT2 and CT3. A rising or falling edge on the inputs CT0I, CT1I, CT2I or CT3I (alternative function of Port 1) results in loading the contents of T2 into the respective Capture Registers and an interrupt request.

Using the Capture Register CTCON, these inputs may invoke capture and interrupt request on a positive edge, a negative edge or on both edges. If neither a positive nor a negative edge is selected for capture input, no capture or interrupt request can be generated by this input.

The contents of the Compare Registers CM0, CM1 and CM2 are continually compared with the counter value of Timer T2. When a match occurs, an interrupt may be invoked. A match of CM0 sets the bits 0 to 5 of Port 4, a CM1 match resets these bits and a CM2 match toggles bits 6 and 7 of Port 4, provided these functions are enabled by the STE/RTE registers. A match of CM0 and CM1 at the same time results in resetting bits 0 to 5 of Port 4. CM0, CM1 and CM2 are reset by the RST signal.

Port 4 can be read and written by software without affecting the toggle, set and reset signals. At a byte overflow of the least significant byte, or at a 16-bit overflow of the timer/counter, an interrupt sharing the same interrupt vector is requested. Either one or both of these overflows can be programmed to request an interrupt. All interrupt flags must be reset by software.

1996 Jun 27 22

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

handbook, full pagewidth

off

CLK

RT2

T2ER

external reset

S S S S S S

TG TG

STE

= set

= reset

= toggle

= toggle status

1/12

enable

CT0I INT

CT0

R R R R R R

T T

RTE

CT1I INT

CTI0

PRESCALER

P4.0 P4.1 P4.2 P4.3 P4.4 P4.5

P4.6 P4.7

T2 SFR address: TML2 = lower 8 bits

I/O port 4

TMH2 = higher 8 bits

CTI1

CT1

T2 COUNTER

CM0 (S)

COMP

CT2I INT

CTI2

CT2

8-bit overflow interrupt 16-bit overflow interrupt

INT

COMP

CM1 (R)

CT3I INT

INT

CT3

COMP

CM2 (T)

CTI3

INT

MGA156

Fig.11 Block diagram of Timer T2 configuration.

1996 Jun 27 23

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

11.2.1 COUNTER CONTROL REGISTER (TM2CON)

Table 16 Counter Control register (address EAH)

76543210

T2IS1 T2IS0 T2ER T2B0 T2P1 T2P0 T2MS1 T2MS0

Table 17 Description of the TM2CON bits

BIT SYMBOL FUNCTION

7 T2IS1 Timer 2 16-bit overﬂow interrupt select. 6 T2IS0 Timer 2 byte overﬂow interrupt select. 5 T2ER Timer 2 external reset enable. 4 T2B0 Timer 2 byte overﬂow interrupt ﬂag. 3 T2P1 Timer 2 prescaler select (see Table 18). 2 T2P0 1 T2MS1 Timer 2 mode select (see Table 19). 0 T2MS0

Table 18 Timer 2 prescaler select

T2P1 T2P0 T2 CLOCK

0 0 Clock source

⁄

01 10 11

Clock source

⁄

Clock source

⁄

Clock source

Table 19 Timer 2 mode select

T2MS1 T2MS0 MODE

0 0 Timer T2 is halted 0 1 T2 clock source = 1 0 Test mode; do not use 1 1 T2 clock source = pin T2

⁄12f

11.2.2 CAPTURE CONTROL REGISTER (CTCON)

Table 20 Capture Control register (address EBH)

76543210

CTN3 CTP3 CTN2 CTP2 CTN1 CTP1 CTN0 CTP0

Table 21 Description of the CTCON bits

FUNCTION

BIT SYMBOL

CAPTURE INTERRUPT ON

7 CTN3 CT3I negative edge 6 CTP3 CT3I positive edge 5 CTN2 CT2I negative edge 4 CTP2 CT2I positive edge 3 CTN1 CT1I negative edge 2 CTP1 CT1I positive edge 1 CTN0 CT0I negative edge 0 CTP0 CT0I positive edge

CLK

1996 Jun 27 24

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

11.2.3 TIMER INTERRUPT FLAG REGISTER (TM2IR)

Table 22 Timer Interrupt Flag register (address C8H)

76543210

T2OV CMI2 CMI1 CMI0 CTI3 CTI2 CTI1 CTI0

Table 23 Description of the TM2IR bits (see notes 1 and 2)

BIT SYMBOL FUNCTION

7 T2OV T2: 16-bit overﬂow interrupt ﬂag. 6 CMI2 CM2: interrupt ﬂag. 5 CMI1 CM1: interrupt ﬂag. 4 CMI0 CM0: interrupt ﬂag. 3 CTI3 CT3: interrupt ﬂag. 2 CTI2 CT2: interrupt ﬂag. 1 CTI1 CT1: interrupt ﬂag. 0 CTI0 CT0: interrupt ﬂag.

Notes

1. Interrupt Enable IEN1 is used to enable/disable Timer 2 interrupts (see Section 14.1.2).

2. Interrupt Priority Register IP1 is used to determine the Timer 2 interrupt priority (see Section 14.1.4).

11.2.4 S

Table 24 Set Enable register (address EEH)

Table 25 Description of the STE bits (see notes 1 and 2)

ET ENABLE REGISTER (STE)

76543210

TG47 TG46 SP45 SP44 SP43 SP42 SP41 SP40

BIT SYMBOL FUNCTION

7 TG47 if HIGH then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle. 6 TG46 if HIGH then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle. 5 SP45 if HIGH then P4.5 is set on a match of CM0 and T2. 4 SP44 if HIGH then P4.4 is set on a match of CM0 and T2. 3 SP43 if HIGH then P4.3 is set on a match of CM0 and T2. 2 SP42 if HIGH then P4.2 is set on a match of CM0 and T2. 1 SP41 if HIGH then P4.1 is set on a match of CM0 and T2. 0 SP40 if HIGH then P4.0 is set on a match of CM0 and T2.

Notes

1. If STE.n is LOW then P4.n is not affected by a match of CM0 and T2 (n = 0, 1, 2, 3, 4, 5).

2. STE.6 and STE.7 are read only.

1996 Jun 27 25

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

11.2.5 RESET/TOGGLE ENABLE REGISTER (RTE)

Table 26 Reset/Toggle Enable register (address EFH)

76543210

TP47 TP46 RP45 RP44 RP43 RP42 RP41 RP40

Table 27 Description of the RTE bits (note 1)

BIT SYMBOL FUNCTION

7 TP47 if HIGH then P4.7 toggles on a match of CM2 and T2. 6 TP46 if HIGH then P4.6 toggles on a match of CM2 and T2. 5 RP45 if HIGH then P4.5 is reset on a match of CM1 and T2. 4 RP44 if HIGH then P4.4 is reset on a match of CM1 and T2. 3 RP43 if HIGH then P4.3 is reset on a match of CM1 and T2. 2 RP42 if HIGH then P4.2 is reset on a match of CM1 and T2. 1 RP41 if HIGH then P4.1 is reset on a match of CM1 and T2. 0 RP40 if HIGH then P4.0 is reset on a match of CM1 and T2.

Note

1. If RTE.n is LOW then P4.n is not affected by a match of CM1 and T2 or CM2 and T2.

For more information, refer to the 8051-based

“8-bit Microcontrollers Data Handbook IC20”

1996 Jun 27 26

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

11.3 Watchdog Timer (T3)

In addition to Timer T2 and the standard timers (Timer 0 and Timer 1), a Watchdog Timer (WDT) comprising an 11-bit prescaler and an 8-bit timer (T3) is also provided (see Fig.12).

The timer T3 is incremented every 1.5 ms, derived from the oscillator frequency of 16 MHz by the following

formula:

timer

------------------------- 12 2048×

CLK

When a timer T3 overflow occurs, the microcontroller is reset and a reset-output-pulse is generated at pin RST. This short output pulse (3 machine cycles) may be suppressed if the RST pin is connected to a capacitor.

To prevent a system reset (by an overflow of the WDT), the user program has to reload T3 within periods that are shorter than the programmed Watchdog time interval.

If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will produce a reset upon overflow thus preventing the processor running out of control.

The Watchdog Timer can only be reloaded if the condition flag WLE = PCON.4 has been previously set by software. At the moment the counter is loaded the condition flag is automatically cleared.

The timer interval between the timer's reloading and the occurrence of a reset depends on the reloaded value. For example, this may range from 1.5 ms to 0.375 s when using an oscillator frequency of 16 MHz.

In the Idle state the Watchdog Timer and reset circuitry remain active.

The Watchdog Timer (WDT) is controlled by the Enable Watchdog pin (

Table 28

EW); see Table 28.

EW controlling WDT and Power-down mode

PIN EW WDT POWER-DOWN MODE

LOW enabled disabled

HIGH disabled enabled

handbook, full pagewidth

1/12 f

CLK

INTERNAL BUS

PRESCALER

11-BIT

write

TIMER T3 (8-BIT)

LOADCLEAR

LOADEN

CLEAR

WLE PD

PCON.4

INTERNAL BUS

Fig.12 Functional diagram of T3 Watchdog Timer.

overflow

internal

reset

LOADEN

PCON.1

RST

MGA157

1996 Jun 27 27

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

12 SERIAL I/O PORT: SIO0 (UART)

The Serial Port SIO0 is a full duplex (UART) serial I/O port i.e. it can transmit and receive simultaneously. This Serial Port is also receive-buffered. It can commence reception of a second byte before the previously received byte has been read from the receive register. However, if the first byte has still not been read by the time reception of the second byte is complete, one of these (first or second) bytes will be lost. The SIO0 receive and transmit registers are both accessed via the S0BUF SFR. Writing to S0BUF loads the transmit register, and reading S0BUF accesses to a physically separate receive register. SIO0 can operate in 4 modes:

Mode 0 Serial data is transmitted and received through

RXD. TXD outputs the shift clock. 8 data bits are

transmitted/received (LSB first). The baud rate is

fixed at1⁄12 of the oscillator frequency. Mode 1 10 bits are transmitted via TXD or received

through RXD: a start bit (0), 8 data bits (LSB first),

and a stop bit (1). On receive, the stop bit is put

into RB8 of the S0CON SFR. The baud rate is

variable. Mode 2 11 bits are transmitted through TXD or received

through RXD: a start bit (0), 8 data bits (LSB first),

a programmable 9th data bit, and a stop bit (1).

On transmit, the 9th data bit (TB8 in S0CON) can

be assigned the value of 0 or 1. With nominal

software, TB8 can be the parity bit (P in PSW).

During a receive, the 9th data bit is stored in RB8

(S0CON), and the stop bit is ignored. The baud

rate is programmable to either1⁄32 or1⁄64 of the

oscillator frequency. Mode 3 11 bits are transmitted through TXD or received

through RXD: a start bit (0), 8 data bits (LSB first),

a programmable 9th data bit, and a stop bit (1).

Mode 3 is the same as Mode 2 except for the

baud rate which is variable in Mode 3. In all four modes, transmission is initiated by any

instruction that writes to the S0BUF SFR. Reception is initiated in Mode 0 when RI = 0 and REN = 1. In the other three modes, reception is initiated by the incoming start bit provided that REN = 1.

Modes 2 and 3 are provided for multiprocessor communications. In these modes, 9 data bits are received with the 9th bit written to RB8 (S0CON). The 9th bit is followed by the stop bit. The port can be programmed so that with receiving the stop bit, the Serial Port interrupt will be activated if, and only if RB8 = 1.

This feature is enabled by setting bit SM2 in S0CON. This feature may be used in multiprocessor systems.

For more information about how to use the UART in combination with the registers S0CON, PCON, IE, SBUF and the Timer register, refer to the 8051-based

“8-bit Microcontrollers Data Handbook IC20”

13 SERIAL I/O PORT: SIO1 (CAN)

SIO1 (CAN) provides the CAN (Controller Area Network) serial-bus data communication interface. SIO1 (CAN) replaces the SIO1 (I microcontroller derivative P8xC552.

13.1 On-chip CAN-controller

CAN is the definition of a high performance communication protocol for serial data communication. The P8xCE598 on-chip CAN-controller is a full implementation of the CAN 2.0A protocol. With the P8xCE598 powerful local networks can be built, both for automotive and general industrial environments. This results in a much reduced wiring harness and enhanced diagnostic and supervisory capabilities.

13.2 CAN Features

• Multi-master architecture

• Bus access priority determined by the message

identifier

• 2032 message identifier (2

• Guaranteed latency time for high priority messages

• Powerful error handling capability

• Data length from 0 up to 8 bytes

• Multicast and broadcast message facility

• Non destructive bit-wise arbitration

• Non-return-to-zero (NRZ) coding/decoding with

bit-stuffing

• Programmable transfer rate (up to 1 Mbit/s)

• Programmable output driver configuration

• Suitable for use in a wide range of networks including

the SAE's network classes A, B and C

• DMA providing high-speed on-chip data exchange

• Bus failure management facility

•1⁄2AVDD reference voltage.

C) serial interface as provided in the

standard frame CAN 2.0A)

1996 Jun 27 28

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

13.3 Interface between CPU and CAN

The internal interface between the P8xCE598's CPU and on-chip CAN-controller is achieved via the following four SFRs (see Fig.13):

• CANADR, to point to a register of the CAN-controller

• CANDAT, to read or write data

• CANCON, to read interrupt flags and to write commands

• CANSTA, to read status information and to write DMA

pointer.

Additionally, the DMA-logic allows a high-speed data exchange between the CAN-controller and the CPU's on-chip Main RAM. For more information, see Section 13.5.15 “Handling of the CPU-CAN interface”.

13.4 Hardware blocks of the CAN-controller

The P8xCE598 CAN-controller contains all necessary hardware for high performance serial network communications (see Fig.14 and Table 29).

It controls the communication flow through the area network using the CAN-protocol. The CAN-controller meets the following requirements:

• Short message length

• Bus access priority, determined by the message

identifier

• Powerful error handling capability

• Configuration flexibility to allow area network expansion

• Guaranteed latency time for urgent messages;

– The latency time defines the period between the

initiation (Transmission Request) and the start of the transmission on the bus. The latency time strongly depends on a large variety of bus-related conditions. In the case of a message being transmitted on the bus and one distortion, the latency time can be up to 149 bit times (worst case). For more information see Chapter 22, “CAN application information”.

handbook, full pagewidth

CPU

MAIN RAM

internal

bus

4 special function

registers

CANADR

CANDAT

CANCON

CANSTA

DMA bus

DBH

DAH

D9H

D8H

DMA

LOGIC

ADDRESS

DATA

CAN

CONTROLLER

MGA158

Fig.13 Interface between CPU and CAN-controller.

1996 Jun 27 29

Philips Semiconductors Product speciﬁcation

8-bit microcontroller with on-chip CAN P8xCE598

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address

data

INTERFACE

MANAGEMENT

LOGIC

TRANSMIT

BUFFER

ON - CHIP

RECEIVE

BUFFER 0

RECEIVE

BUFFER 1

BIT TIMING

LOGIC

TRANSCEIVER

LOGIC

CAN

CONTROLLER

ERROR

MANAGEMENT

LOGIC

BIT STREAM

PROCESSOR

MGA159

CRX0

and

CRX1

CTX0

and

CTX1

Fig.14 Block diagram of the P8xCE598 on-chip CAN-controller.

Table 29 Hardware blocks of the CAN-controller (see Fig.14)

NAME BLOCK DESCRIPTION

Interface Management Logic IML Interprets commands from the CPU, allocates the message buffers

(TBF, RBF0 and RBF1) and provides interrupts and status information to the microcontroller.

Transmit Buffer TBF 10 bytes memory into which the CPU writes messages which are to be

transmitted over the CAN network.

Receive Buffers (0 and 1) RBF0 RBF0 and RBF1 are each 10 bytes memories which are alternatively used to

RBF1

store messages received from the CAN network. The CPU can process one message while another is being received.

Bit Stream Processor BSP Is a sequencer, controlling the data stream between the Transmit Buffer,

Receive Buffers (parallel data) and the CAN-bus (serial data). Bit Timing Logic BTL Synchronizes the CAN-controller to the bitstream on the CAN-bus. Transceiver Control Logic TCL Controls the output driver. Error Management Logic EML Performs the error conﬁnement according to the CAN-protocol.

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