± |
INTEGRATED CIRCUITS |
|
P80C31X2/32X2
P80C51X2/52X2/54X2/58X2
P87C51X2/52X2/54X2/58X2
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP 128B/256B RAM
low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
Product data |
2003 Jan 24 |
Supersedes data of 2002 Sep 12 |
|
P s
on o s
Philips Semiconductors |
Product data |
|
|
|
|
|
|
|
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
The Philips microcontrollers described in this data sheet are high-performance static 80C51 designs incorporating Philips' high-density CMOS technology with operation from 2.7 V to 5.5 V. They support both 6-clock and 12-clock operation.
The P8xC31X2/51X2 and P8xC32X2/52X2/54X2/58X2 contain 128 byte RAM and 256 byte RAM respectively, 32 I/O lines, three
16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits.
In addition, the devices are low power static designs which offer a wide range of operating frequencies down to zero. Two software
selectable modes of power reduction Ð idle mode and power-down mode Ð are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data. Then the execution can be resumed from the point the clock was stopped.
For applications requiring more ROM and RAM, as well as more on-chip peripherals, see the P89C66x and P89C51Rx2 data sheets.
Type |
|
Memory |
|
|
Timers |
|
Serial Interfaces |
|
|||||
|
|
|
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|
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|
|
|
|
|
|
ADCbits/ch. |
|
RAM |
ROM |
OTP |
Flash |
of# Timers |
PWM |
PCA |
WD |
UART |
I |
CAN |
SPI |
|
|
|
|
|
|
|
|
|
|
|
C |
|
|
|
|
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|
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2 |
|
|
|
P87C58X2 |
256B |
± |
32K |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
P80C58X2 |
256B |
32K |
± |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
P87C54X2 |
256B |
± |
16K |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
P80C54X2 |
256B |
16K |
± |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
P87C52X2 |
256B |
± |
8K |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
P80C52X2 |
256B |
8K |
± |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
P87C51X2 |
128B |
± |
4K |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
P80C51X2 |
128B |
4K |
± |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
P80C32X2 |
256B |
± |
± |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
P80C31X2 |
128B |
± |
± |
± |
3 |
± |
± |
± |
n |
± |
± |
± |
± |
|
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|
|
|
|
NOTE:
|
|
|
DefaultClock Rate |
Optional RateClock |
Max. |
Freq. |
Freq. |
|
|
Interrupts (External) |
|
Freq. |
|||||
PinsI/O |
Program Security |
Range |
Range |
|||||
at 6-clk |
||||||||
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at 3V |
at 5V |
||
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/ 12-clk |
|||
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|
(MHz) |
(MHz) |
||
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|
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(MHz) |
|||
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|
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|
|
||
32 |
6 (2) |
n |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
32 |
6 (2) |
n |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
32 |
6 (2) |
n |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
32 |
6 (2) |
n |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
32 |
6 (2) |
n |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
32 |
6 (2) |
n |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
32 |
6 (2) |
n |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
32 |
6 (2) |
n |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
32 |
6 (2) |
± |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
32 |
6 (2) |
± |
12±clk |
6-clk |
30/33 |
0±16 |
0±30/33 |
|
|
|
|
|
|
|
|
|
1.I2C = Inter-Integrated Circuit Bus; CAN = Controller Area Network; SPI = Serial Peripheral Interface; PCA = Programmable Counter Array;
ADC = Analog-to-Digital Converter; PWM = Pulse Width Modulation
2003 Jan 24 |
2 |
853-2337 29260 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
•80C51 Central Processing Unit
±4 kbytes ROM/EPROM (P80/P87C51X2)
±8 kbytes ROM/EPROM (P80/P87C52X2)
±16 kbytes ROM/EPROM (P80/P87C54X2)
±32 kbytes ROM/EPROM (P80/P87C58X2)
±128 byte RAM (P80/P87C51X2 and P80C31X2)
±256 byte RAM (P80/P87C52/54X2/58X2 and P80C32X2)
±Boolean processor
±Fully static operation
±Low voltage (2.7 V to 5.5 V at 16 MHz) operation
•12-clock operation with selectable 6-clock operation (via software or via parallel programmer)
•Memory addressing capability
± Up to 64 kbytes ROM and 64 kbytes RAM
•Power control modes:
±Clock can be stopped and resumed
±Idle mode
±Power-down mode
•CMOS and TTL compatible
•Two speed ranges at VCC = 5 V
±0 to 30 MHz with 6-clock operation
±0 to 33 MHz with 12-clock operation
•PLCC, DIP, TSSOP or LQFP packages
•Extended temperature ranges
•Dual Data Pointers
•Security bits:
±ROM (2 bits)
±OTP (3 bits)
•Encryption array - 64 bytes
•Four interrupt priority levels
•Six interrupt sources
•Four 8-bit I/O ports
•Full-duplex enhanced UART
±Framing error detection
±Automatic address recognition
•Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture and compare)
•Programmable clock-out pin
•Asynchronous port reset
•Low EMI (inhibit ALE, slew rate controlled outputs, and 6-clock mode)
•Wake-up from Power Down by an external interrupt.
2003 Jan 24 |
3 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
Type number |
Package |
|
|
Temperature |
|
|
|
|
Range (°C) |
|
Name |
Description |
Version |
|
|
|
|||
|
|
|
|
|
P80C31X2BA |
PLCC44 |
plastic leaded chip carrier; 44 leads |
SOT187-2 |
0 to +70 |
|
|
|
|
|
P80C31X2BN |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
0 to +70 |
|
|
|
|
|
P80C32X2BA |
PLCC44 |
plastic leaded chip carrier; 44 leads |
SOT187-2 |
0 to +70 |
|
|
|
|
|
P80C32X2BN |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
0 to +70 |
|
|
|
|
|
P80C32X2BBD |
LQFP44 |
plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm |
SOT389-1 |
0 to +70 |
|
|
|
|
|
P80C32X2FA |
PLCC44 |
plastic leaded chip carrier; 44 leads |
SOT187-2 |
±40 to +85 |
|
|
|
|
|
P80C32X2FN |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
±40 to +85 |
Type number |
Package |
|
|
Temperature |
|
|
|
|
Range (°C) |
|
Name |
Description |
Version |
|
|
|
|||
|
|
|
|
|
P87C51X2BA |
PLCC44 |
plastic leaded chip carrier; 44 leads |
SOT187-2 |
0 to +70 |
|
|
|
|
|
P87C51X2BN |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
0 to +70 |
|
|
|
|
|
P87C51X2BBD |
LQFP44 |
plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm |
SOT389-1 |
0 to +70 |
|
|
|
|
|
P87C51X2FA |
PLCC44 |
plastic leaded chip carrier; 44 leads |
SOT187-2 |
±40 to +85 |
|
|
|
|
|
P87C51X2FBD |
LQFP44 |
plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm |
SOT389-1 |
±40 to +85 |
Type number |
Package |
|
|
Temperature |
|
|
|
|
Range (°C) |
|
Name |
Description |
Version |
|
|
|
|||
|
|
|
|
|
P87C52X2BA |
PLCC44 |
plastic leaded chip carrier; 44 leads |
SOT187-2 |
0 to +70 |
|
|
|
|
|
P87C52X2BN |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
0 to +70 |
|
|
|
|
|
P87C52X2BBD |
LQFP44 |
plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm |
SOT389-1 |
0 to +70 |
|
|
|
|
|
P87C52X2FA |
PLCC44 |
plastic leaded chip carrier; 44 leads |
SOT187-2 |
±40 to +85 |
|
|
|
|
|
P87C52X2FN |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
±40 to +85 |
|
|
|
|
|
P87C52X2FBD |
LQFP44 |
plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm |
SOT389-1 |
±40 to +85 |
Type number |
Package |
|
|
Temperature |
|
|
|
|
Range (°C) |
|
Name |
Description |
Version |
|
|
|
|||
|
|
|
|
|
P87C54X2BA |
PLCC44 |
plastic lead chip carrier; 44 leads |
SOT187-2 |
0 to +70 |
|
|
|
|
|
P87C54X2BN |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
0 to +70 |
|
|
|
|
|
P87C54X2BBD |
LQFP44 |
plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm |
SOT389-1 |
0 to +70 |
|
|
|
|
|
P87C54X2BDH |
TSSOP38 |
plastic thin shrink small outline package; 38 leads; body width 4.4 mm; |
SOT510-1 |
0 to +70 |
|
|
lead pitch 0.5 mm |
|
|
P87C54X2FA |
PLCC44 |
plastic lead chip carrier; 44 leads |
SOT187-2 |
±40 to +85 |
|
|
|
|
|
P87C54X2FBD |
LQFP44 |
plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm |
SOT389-1 |
±40 to +85 |
Type number |
Package |
|
|
|
Temperature |
|
|
|
|
|
Range (°C) |
|
Name |
Description |
Version |
||
|
|
||||
|
|
|
|
|
|
P87C58X2BA |
PLCC44 |
plastic lead chip carrier; 44 leads |
SOT187-2 |
|
0 to +70 |
|
|
|
|
|
|
P87C58X2BN |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
|
0 to +70 |
|
|
|
|
|
|
P87C58X2BBD |
LQFP44 |
plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm |
SOT389-1 |
0 to +70 |
|
|
|
|
|
|
|
P87C58X2FA |
PLCC44 |
plastic lead chip carrier; 44 leads |
SOT187-2 |
|
±40 to +85 |
|
|
|
|
|
|
P87C58X2FBD |
LQFP44 |
plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm |
SOT389-1 |
±40 to +85 |
|
|
|
|
|
|
|
P87C58X2FN |
DIP40 |
plastic dual in-line package; 40 leads (600 mil) |
SOT129-1 |
|
±40 to +85 |
All OTP parts listed here are also available as ROM parts (80C5xX2). Please contact your Philips representative if you would like to order a ROM part.
2003 Jan 24 |
4 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
Memory |
|
|
|
Temperature Range |
Package |
||||||||
|
|
|
|
|
|
|
|
||||||
|
|
P87C51X2 |
|
|
|
B = 0 °C TO +70 °C |
A = PLCC |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
F = ±40 °C TO +85 °C |
N = DIP |
|
|
|
|
|
|
|
|
|
|
|
|
||
|
7 = |
OTP |
|
5 = ROM/OTP |
1 = 128 BYTES RAM |
X2 = 6-clock |
|
BD = LQFP |
|||||
|
0 = |
ROM or |
|
3 = ROMless |
4 KBYTES ROM/OTP |
mode available |
|
DH = TSSOP |
|||||
|
|
ROMless |
|
|
2 = 256 BYTES RAM |
|
|
||||||
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
8 KBYTES ROM/OTP |
|
|
|
|
|
|
|
|
|
|
|
|
|
4 = 256 BYTES RAM |
|
|
|
|
|
|
|
|
|
|
|
|
|
16 KBYTES ROM/OTP |
|
|
|
|
|
|
|
|
|
|
|
|
|
8 = 256 BYTES RAM |
|
|
|
|
|
|
|
|
|
|
|
|
|
32 KBYTES ROM/OTP |
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
The following table illustrates the correlation between operating mode, power supply and maximum external clock frequency:
Operating Mode |
Power Supply |
Maximum Clock Frequency |
|
|
|
6-clock |
5 V ± 10% |
30 MHz |
|
|
|
6-clock |
2.7 V to 5.5 V |
16 MHz |
|
|
|
12-clock |
5 V ± 10% |
33 MHz |
|
|
|
12-clock |
2.7 V to 5.5 V |
16 MHz |
|
|
|
2003 Jan 24 |
5 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
|
Accelerated 80C51 CPU |
|
(12-clk mode, 6-clk mode) |
|
0K / 4K / 8K / 16K / |
|
32 kbyte |
|
CODE ROM / EPROM |
|
Full-duplex enhanced |
|
UART |
|
128 / 256 Byte |
|
Data RAM |
|
Timer 0 |
|
Timer 1 |
|
Port 3 |
|
Configurable I/Os |
|
Timer 2 |
|
Port 2 |
|
Configurable I/Os |
|
Port 1 |
|
Configurable I/Os |
|
Port 0 |
|
Configurable I/Os |
Crystal or |
Oscillator |
Resonator |
|
|
su01579 |
2003 Jan 24 |
6 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
|
|
|
|
P0.0±P0.7 |
P2.0±P2.7 |
|
|
|
|
|
|
PORT 0 |
PORT 2 |
|
|
|
|
|
|
DRIVERS |
DRIVERS |
|
|
VCC |
|
|
|
|
|
|
|
VSS |
|
|
|
|
|
|
|
|
RAM ADDR |
RAM |
PORT 0 |
PORT 2 |
ROM/EPROM |
|
|
|
REGISTER |
|
LATCH |
LATCH |
|
|
|
|
|
|
|
|
|
|
8 |
|
B |
|
ACC |
|
|
STACK |
|
|
REGISTER |
|
|
|
POINTER |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
PROGRAM |
|
|
|
|
TMP1 |
|
|
ADDRESS |
|
|
|
TMP2 |
|
|
REGISTER |
|
|
|
|
|
ALU |
|
|
BUFFER |
|
|
|
|
|
|
|
|
|
|
|
|
|
SFRs |
|
|
|
|
|
|
|
TIMERS |
|
PC |
|
|
|
PSW |
|
|
INCRE- |
|
|
|
|
|
|
|
|
MENTER |
|
|
|
|
|
|
8 |
16 |
|
|
|
|
|
|
|
PROGRAM |
|
|
|
|
|
|
|
COUNTER |
PSEN |
|
INSTRUCTION |
REGISTER |
|
|
|
|
ALE/PROG |
TIMING |
|
|
|
DPTR'S |
||
EA / VPP |
AND |
|
|
|
MULTIPLE |
||
CONTROL |
|
|
|
|
|||
RST |
|
|
|
|
|
||
|
PD |
|
PORT 1 |
|
|
PORT 3 |
|
|
|
|
LATCH |
|
|
LATCH |
|
|
OSCILLATOR |
|
|
|
|
||
|
|
|
PORT 1 |
|
|
PORT 3 |
|
|
|
|
DRIVERS |
|
|
DRIVERS |
|
|
XTAL1 |
|
XTAL2 |
|
|
|
|
|
|
|
P1.0±P1.7 |
|
P3.0±P3.71 |
|
|
|
|
|
|
|
|
|
su01723 |
NOTE:
1. P3.2 and P3.5 absent in the TSSOP38 package.
2003 Jan 24 |
7 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
|
|
VCC |
VSS |
|
|
|
XTAL1 |
|
|
|
|
|
0 |
ADDRESS AND |
|
|
|
PORT |
DATA BUS |
|
|
|
|
|
|
|
XTAL2 |
|
|
|
|
|
|
T2 |
|
|
|
1 |
T2EX |
|
|
RST |
|
|
|
|
PORT |
|
|
|
|
EA/VPP |
|
|
|
|
|
|
|
|
|
PSEN |
|
|
FUNCTIONSSECONDARY |
ALE/PROG |
2PORT |
|
|
RxD |
3PORT |
|
||
|
|
|
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TxD |
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INT01 |
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INT1 |
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ADDRESS BUS |
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T0 |
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T11 |
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WR |
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RD |
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SU01724 |
NOTE:
1. INT0/P3.2 and T1/P3.5 are absent in the TSSOP38 package.
PLASTIC DUAL IN-LINE PACKAGE
PIN CONFIGURATIONS
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T2/P1.0 |
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1 |
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40 |
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VCC |
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T2EX/P1.1 |
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2 |
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39 |
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P0.0/AD0 |
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P1.2 |
3 |
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38 |
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P0.1/AD1 |
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P1.3 |
4 |
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37 |
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P0.2/AD2 |
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P1.4 |
5 |
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36 |
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P0.3/AD3 |
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P1.5 |
6 |
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35 |
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P0.4/AD4 |
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P1.6 |
7 |
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34 |
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P0.5/AD5 |
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P1.7 |
8 |
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33 |
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P0.6/AD6 |
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RST |
9 |
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32 |
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P0.7/AD7 |
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DUAL |
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RxD/P3.0 |
10 |
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31 |
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EA/VPP |
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IN-LINE |
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TxD/P3.1 |
11 |
PACKAGE |
30 |
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ALE |
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12 |
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29 |
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INT0/P3.2 |
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PSEN |
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13 |
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28 |
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P2.7/A15 |
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INT1/P3.3 |
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T0/P3.4 |
14 |
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27 |
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P2.6/A14 |
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T1/P3.5 |
15 |
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26 |
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P2.5/A13 |
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16 |
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25 |
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P2.4/A12 |
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WR/P3.6 |
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17 |
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24 |
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P2.3/A11 |
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RD/P3.7 |
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XTAL2 |
18 |
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23 |
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P2.2/A10 |
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XTAL1 |
19 |
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22 |
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P2.1/A9 |
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VSS |
20 |
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21 |
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P2.0/A8 |
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SU01063 |
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2003 Jan 24 |
8 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS |
PLASTIC THIN SHRINK SMALL OUTLINE PACK |
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6 |
1 |
40 |
PIN FUNCTIONS |
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1 |
38 |
7 |
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39 |
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PLCC |
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TSSOP |
17 |
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29 |
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18 |
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28 |
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Pin |
Function |
Pin |
Function |
Pin |
Function |
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1 |
NIC* |
16 |
P3.4/T0 |
31 |
P2.7/A15 |
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19 |
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20 |
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2 |
P1.0/T2 |
17 |
P3.5/T1 |
32 |
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PSEN |
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3 |
P1.1/T2EX |
18 |
P3.6/WR |
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33 |
ALE |
Pin |
Function |
Pin |
Function |
Pin |
Function |
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4 |
P1.2 |
19 |
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34 |
NIC* |
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P3.7/RD |
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1 |
P3.0/RxD |
14 |
P2.4/A12 |
27 |
P0.1/AD1 |
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5 |
P1.3 |
20 |
XTAL2 |
35 |
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EA/VPP |
2 |
P3.1/TxD |
15 |
P2.5/A13 |
28 |
P0.0/AD0 |
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6 |
P1.4 |
21 |
XTAL1 |
36 |
P0.7/AD7 |
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16 |
P2.6/A14 |
29 |
VDD |
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3 |
P3.3/INT1 |
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7 |
P1.5 |
22 |
VSS |
37 |
P0.6/AD6 |
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4 |
P3.4/T0 |
17 |
P2.7/A15 |
30 |
P1.0/T2 |
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8 |
P1.6 |
23 |
NIC* |
38 |
P0.5/AD5 |
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5 |
P3.6/WR |
18 |
PSEN |
31 |
P1.1/T2EX |
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9 |
P1.7 |
24 |
P2.0/A8 |
39 |
P0.4/AD4 |
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32 |
P1.2 |
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6 |
P3.7/RD |
19 |
ALE/PROG |
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10 |
RST |
25 |
P2.1/A9 |
40 |
P0.3/AD3 |
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33 |
P1.3 |
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7 |
XTAL2 |
20 |
EA/VPP |
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11 |
P3.0/RxD |
26 |
P2.2/A10 |
41 |
P0.2/AD2 |
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8 |
XTAL1 |
21 |
P0.7/AD7 |
34 |
P1.4 |
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12 |
NIC* |
27 |
P2.3/A11 |
42 |
P0.1/AD1 |
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9 |
VSS |
22 |
P0.6/AD6 |
35 |
P1.5 |
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13 |
P3.1/TxD |
28 |
P2.4/A12 |
43 |
P0.0/AD0 |
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10 |
P2.0/A8 |
23 |
P0.5/AD5 |
36 |
P1.6 |
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14 |
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29 |
P2.5/A13 |
44 |
VCC |
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P3.2/INT0 |
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11 |
P2.1/A9 |
24 |
P0.4/AD4 |
37 |
P1.7 |
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15 |
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30 |
P2.6/A14 |
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P3.3/INT1 |
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12 |
P2.2/A10 |
25 |
P0.3/AD3 |
38 |
RST |
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* NO INTERNAL CONNECTION |
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13 |
P2.3/A11 |
26 |
P0.2/AD2 |
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su01725 |
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SU01062 |
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LOW PROFILE QUAD FLAT PACK
PIN FUNCTIONS
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44 |
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34 |
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1 |
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33 |
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LQFP |
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11 |
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23 |
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12 |
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22 |
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Pin |
Function |
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Pin |
Function |
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Pin |
Function |
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1 |
P1.5 |
16 |
VSS |
31 |
P0.6/AD6 |
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2 |
P1.6 |
17 |
NIC* |
32 |
P0.5/AD5 |
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3 |
P1.7 |
18 |
P2.0/A8 |
33 |
P0.4/AD4 |
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4 |
RST |
19 |
P2.1/A9 |
34 |
P0.3/AD3 |
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5 |
P3.0/RxD |
20 |
P2.2/A10 |
35 |
P0.2/AD2 |
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6 |
NIC* |
21 |
P2.3/A11 |
36 |
P0.1/AD1 |
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7 |
P3.1/TxD |
22 |
P2.4/A12 |
37 |
P0.0/AD0 |
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8 |
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23 |
P2.5/A13 |
38 |
VCC |
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P3.2/INT0 |
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9 |
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24 |
P2.6/A14 |
39 |
NIC* |
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P3.3/INT1 |
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10 |
P3.4/T0 |
25 |
P2.7/A15 |
40 |
P1.0/T2 |
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11 |
P3.5/T1 |
26 |
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41 |
P1.1/T2EX |
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PSEN |
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12 |
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27 |
ALE |
42 |
P1.2 |
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P3.6/WR |
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13 |
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28 |
NIC* |
43 |
P1.3 |
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P3.7/RD |
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14 |
XTAL2 |
29 |
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44 |
P1.4 |
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EA/VPP |
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15 |
XTAL1 |
30 |
P0.7/AD7 |
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* NO INTERNAL CONNECTION |
SU01487 |
2003 Jan 24 |
9 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
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PIN NUMBER |
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MNEMONIC |
DIP |
PLCC |
LQFP |
TSSOP |
TYPE |
NAME AND FUNCTION |
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VSS |
20 |
22 |
16 |
9 |
I |
Ground: 0 V reference. |
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VCC |
40 |
44 |
38 |
29 |
I |
Power Supply: This is the power supply voltage for normal, idle, and power-down |
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operation. |
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P0.0-0.7 |
39±32 |
43±36 |
37±30 |
28±21 |
I/O |
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s |
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written to them float and can be used as high-impedance inputs. Port 0 is also the |
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multiplexed low-order address and data bus during accesses to external program |
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and data memory. In this application, it uses strong internal pull-ups when emitting |
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1s. Port 0 also outputs the code bytes during program verification and received |
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code bytes during EPROM programming. External pull-ups are required during |
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program verification. |
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P1.0±P1.7 |
1±8 |
2±9 |
40±44, |
30±37 |
I/O |
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that |
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1±3 |
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have 1s written to them are pulled high by the internal pull-ups and can be used as |
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inputs. As inputs, port 1 pins that are externally pulled low will source current |
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because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also |
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receives the low-order address byte during program memory verification. Alternate |
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functions for Port 1 include: |
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1 |
2 |
40 |
30 |
I/O |
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T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable |
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Clock-Out) |
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2 |
3 |
41 |
31 |
I |
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T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control |
||||||
P2.0±P2.7 |
21±28 |
24±31 |
18±25 |
10±17 |
I/O |
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that |
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have 1s written to them are pulled high by the internal pull-ups and can be used as |
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inputs. As inputs, port 2 pins that are externally being pulled low will source current |
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because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 |
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emits the high-order address byte during fetches from external program memory |
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and during accesses to external data memory that use 16-bit addresses (MOVX |
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@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. |
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During accesses to external data memory that use 8-bit addresses (MOV @Ri), port |
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2 emits the contents of the P2 special function register. Some Port 2 pins receive |
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the high order address bits during EPROM programming and verification. |
|||||||
P3.0±P3.7 |
10±17 |
11, |
5, |
1±6 |
I/O |
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that |
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13±19 |
7±13 |
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have 1s written to them are pulled high by the internal pull-ups and can be used as |
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inputs. As inputs, port 3 pins that are externally being pulled low will source current |
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because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves |
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the special features of the 80C51 family, as listed below: |
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10 |
11 |
5 |
1 |
I |
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RxD (P3.0): Serial input port |
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11 |
13 |
7 |
2 |
O |
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TxD (P3.1): Serial output port |
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12 |
14 |
8 |
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I |
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(P3.2): External interrupt1 |
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INT0 |
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13 |
15 |
9 |
3 |
I |
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(P3.3): External interrupt |
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INT1 |
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14 |
16 |
10 |
4 |
I |
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T0 (P3.4): Timer 0 external input |
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15 |
17 |
11 |
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I |
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T1 (P3.5): Timer 1 external input1 |
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16 |
18 |
12 |
5 |
O |
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(P3.6): External data memory write strobe |
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WR |
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17 |
19 |
13 |
6 |
O |
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(P3.7): External data memory read strobe |
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RD |
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RST |
9 |
10 |
4 |
38 |
I |
Reset: A high on this pin for two machine cycles while the oscillator is running, |
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resets the device. An internal diffused resistor to VSS permits a power-on reset |
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using only an external capacitor to VCC. |
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30 |
33 |
27 |
19 |
O |
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of |
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ALE/PROG |
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the address during an access to external memory. In normal operation, ALE is |
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emitted at a constant rate of 1/6 (12-clock Mode) or 1/3 (6-clock Mode) the |
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oscillator frequency, and can be used for external timing or clocking. Note that one |
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ALE pulse is skipped during each access to external data memory. This pin is also |
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the program pulse input |
(PROG) |
during EPROM programming. ALE can be |
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disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during |
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a MOVX instruction. |
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2003 Jan 24 |
10 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
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PIN NUMBER |
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MNEMONIC |
DIP |
PLCC |
LQFP |
TSSOP |
TYPE |
NAME AND FUNCTION |
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29 |
32 |
26 |
18 |
O |
Program Store Enable: The read strobe to external program memory. When the |
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PSEN |
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device is executing code from the external program memory, |
PSEN |
is activated |
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twice each machine cycle, except that two |
PSEN |
activations are skipped during |
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each access to external data memory. |
PSEN |
is not activated during fetches from |
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internal program memory. |
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31 |
35 |
29 |
20 |
I |
External Access Enable/Programming Supply Voltage: |
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must be externally held low to enable |
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EA/VPP |
EA |
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the device to fetch code from external program memory locations 0000H to |
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0FFFH/1FFFH/3FFFH/7FFFH. If |
EA |
is held high, the device executes from internal program memory |
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unless the program counter contains an address greater than the on-chip ROM/OTP. This pin also |
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receives the 12.75 V programming supply voltage (VPP) during EPROM programming. If security bit |
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1 is programmed, |
EA |
will be internally latched on Reset. |
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XTAL1 |
19 |
21 |
15 |
8 |
I |
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock |
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generator circuits. |
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XTAL2 |
18 |
20 |
14 |
7 |
O |
Crystal 2: Output from the inverting oscillator amplifier. |
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NOTES: |
+ 0.5 V or V |
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± 0.5 V, respectively. |
To avoid ªlatch-upº effect at power-on, the voltage on any pin at any time must not be higher than V |
SS |
||
CC |
|
1. Absent in the TSSOP38 package.
2003 Jan 24 |
11 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
Table 1. |
Special Function Registers |
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SYMBOL |
DESCRIPTION |
DIRECT |
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BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION |
RESET |
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ADDRESS |
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MSB |
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LSB |
VALUE |
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ACC* |
Accumulator |
E0H |
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E7 |
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E6 |
E5 |
E4 |
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E3 |
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E2 |
E1 |
E0 |
00H |
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AUXR# |
Auxiliary |
8EH |
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xxxxxxx0B |
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± |
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± |
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± |
± |
± |
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± |
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± |
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AO |
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AUXR1# |
Auxiliary 1 |
A2H |
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xxx000x0B |
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± |
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± |
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± |
LPEP2 |
WUPD |
0 |
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± |
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DPS |
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B* |
B register |
F0H |
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F7 |
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F6 |
F5 |
F4 |
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F3 |
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F2 |
F1 |
F0 |
00H |
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CKCON |
Clock Control Register |
8FH |
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xxx00000B |
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± |
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± |
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± |
± |
± |
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± |
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± |
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X2 |
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DPTR: |
Data Pointer (2 bytes) |
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DPH |
Data Pointer High |
83H |
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00H |
DPL |
Data Pointer Low |
82H |
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00H |
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AF |
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AE |
AD |
AC |
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AB |
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AA |
A9 |
A8 |
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IE* |
Interrupt Enable |
A8H |
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0x000000B |
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EA |
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± |
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ET2 |
ES |
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ET1 |
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EX1 |
ET0 |
EX0 |
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BF |
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BE |
BD |
BC |
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BB |
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BA |
B9 |
B8 |
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IP* |
Interrupt Priority |
B8H |
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xx000000B |
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± |
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± |
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PT2 |
PS |
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PT1 |
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PX1 |
PT0 |
PX0 |
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IPH# |
Interrupt Priority High |
B7H |
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xx000000B |
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± |
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± |
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PT2H |
PSH |
PT1H |
PX1H |
PT0H |
PX0H |
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87 |
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86 |
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85 |
84 |
83 |
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82 |
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81 |
80 |
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P0* |
Port 0 |
80H |
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FFH |
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AD7 |
AD6 |
AD5 |
AD4 |
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AD3 |
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AD2 |
AD1 |
AD0 |
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97 |
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96 |
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95 |
94 |
93 |
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92 |
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91 |
90 |
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P1* |
Port 1 |
90H |
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FFH |
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± |
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± |
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± |
± |
± |
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± |
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T2EX |
T2 |
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A7 |
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A6 |
A5 |
A4 |
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A3 |
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A2 |
A1 |
A0 |
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P2* |
Port 2 |
A0H |
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FFH |
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AD15 |
AD14 |
AD13 |
AD12 |
AD11 |
AD10 |
AD9 |
AD8 |
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B7 |
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B6 |
B5 |
B4 |
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B3 |
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B2 |
B1 |
B0 |
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P3* |
Port 3 |
B0H |
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FFH |
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RD |
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WR |
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T1 |
T0 |
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INT1 |
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INT0 |
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TxD |
RxD |
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PCON#1 |
Power Control |
87H |
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00xx0000B |
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SMOD1 |
SMOD0 |
± |
POF |
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GF1 |
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GF0 |
PD |
IDL |
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D7 |
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D6 |
D5 |
D4 |
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D3 |
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D2 |
D1 |
D0 |
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PSW* |
Program Status Word |
D0H |
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000000x0B |
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CY |
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AC |
F0 |
RS1 |
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RS0 |
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OV |
± |
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P |
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RACAP2H# |
Timer 2 Capture High |
CBH |
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00H |
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RACAP2L# |
Timer 2 Capture Low |
CAH |
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00H |
SADDR# |
Slave Address |
A9H |
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00H |
SADEN# |
Slave Address Mask |
B9H |
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00H |
SBUF |
Serial Data Buffer |
99H |
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xxxxxxxxB |
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9F |
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9E |
9D |
9C |
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9B |
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9A |
99 |
98 |
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SCON* |
Serial Control |
98H |
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00H |
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SM0/FE |
SM1 |
SM2 |
REN |
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TB8 |
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RB8 |
TI |
RI |
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SP |
Stack Pointer |
81H |
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07H |
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8F |
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8E |
8D |
8C |
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8B |
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8A |
89 |
88 |
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TCON* |
Timer Control |
88H |
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00H |
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TF1 |
TR1 |
TF0 |
TR0 |
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IE1 |
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IT1 |
IE0 |
IT0 |
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CF |
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CE |
CD |
CC |
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CB |
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CA |
C9 |
C8 |
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T2CON* |
Timer 2 Control |
C8H |
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TF2 |
EXF2 |
RCLK |
TCLK |
EXEN2 |
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TR2 |
C/T2 |
CP/RL2 |
00H |
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T2MOD# |
Timer 2 Mode Control |
C9H |
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± |
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± |
± |
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T2OE |
DCEN |
xxxxxx00B |
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TH0 |
Timer High 0 |
8CH |
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00H |
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TH1 |
Timer High 1 |
8DH |
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00H |
TH2# |
Timer High 2 |
CDH |
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00H |
TL0 |
Timer Low 0 |
8AH |
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00H |
TL1 |
Timer Low 1 |
8BH |
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00H |
TL2# |
Timer Low 2 |
CCH |
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00H |
TMOD |
Timer Mode |
89H |
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GATE |
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C/T |
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M1 |
M0 |
GATE |
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C/T |
M1 |
M0 |
00H |
NOTE:
Unused register bits that are not defined should not be set by the user's program. If violated, the device could function incorrectly.
*SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
± Reserved bits.
1.Reset value depends on reset source.
2.LPEP ± Low Power EPROM operation (OTP only)
2003 Jan 24 |
12 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.
Using the oscillator
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. However, minimum and maximum high and low times specified in the data sheet must be observed.
Clock Control Register (CKCON)
This device provides control of the 6-clock/12-clock mode by both an SFR bit (bit X2 in register CKCON and an OTP bit (bit OX2). When X2 is 0, 12-clock mode is activated. By setting this bit to 1, the system is switching to 6-clock mode. Having this option implemented as SFR bit, it can be accessed anytime and changed to either value. Changing X2 from 0 to 1 will result in executing user code at twice the speed, since all system time intervals will be divided by 2. Changing back from 6-clock to 12-clock mode will slow down running code by a factor of 2.
The OTP clock control bit (OX2) activates the 6-clock mode when programmed using a parallel programmer, superceding the X2 bit (CKCON.0). Please also see Table 2 below.
Table 2.
OX2 clock mode bit |
X2 bit |
CPU clock mode |
(can only be set by |
(CKCON.0) |
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parallel programmer) |
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erased |
0 |
12-clock mode |
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(default) |
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erased |
1 |
6-clock mode |
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programmed |
X |
6-clock mode |
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RESET
A reset is accomplished by holding the RST pin HIGH for at least two machine cycles (24 oscillator periods in 12-clock and 12 oscillator periods in 6-clock mode), while the oscillator is running. To insure a reliable power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. After the reset, the part runs in 12-clock mode, unless it has been set to 6-clock operation using a parallel programmer.
Stop Clock Mode
The static design enables the clock speed to be reduced down to 0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. For lowest power consumption the Power Down mode is suggested.
Idle Mode
In idle mode (see Table 3), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
Programmable Clock-Out
A 50% duty cycle clock can be programmed to be output on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed:
1.to input the external clock for Timer/Counter 2, or
2.to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency in 12-clock mode (122 Hz to
8 MHz in 6-clock mode).
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation:
Oscillator Frequency
n (65536±RCAP2H, RCAP2L)
Where:
n = 2 in 6-clock mode, 4 in 12-clock mode.
(RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock
Power-Down Mode
To save even more power, a Power Down mode (see Table 3) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values down to 2.0 V and care must be taken to return VCC to the minimum specified operating voltages before the Power Down
Mode is terminated.
Either a hardware reset or external interrupt can be used to exit from
Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. WUPD (AUXR1.3±Wakeup from
Power Down) enables or disables the wakeup from power down with external interrupt. Where:
WUPD = 0: Disable
WUPD = 1: Enable
To properly terminate Power Down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms).
To terminate Power Down with an external interrupt, INT0 or INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
2003 Jan 24 |
13 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
Low-Power EPROM operation (LPEP)
The EPROM array contains some analog circuits that are not required when VCC is less than 4 V, but are required for a VCC greater than 4 V. The LPEP bit (AUXR.4), when set, will powerdown these analog circuits resulting in a reduced supply current. This bit should be set ONLY for applications that operate at a VCC less than 4 V.
Design Consideration
When the idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction
following the one that invokes Idle should not be one that writes to a port pin or to external memory.
ONCE Mode
The ONCE (ªOn-Circuit Emulationº) Mode facilitates testing and debugging of systems without the device having to be removed from the circuit. The ONCE Mode is invoked in the following way:
1.Pull ALE low while the device is in reset and PSEN is high;
2.Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the device is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Table 3. External Pin Status During Idle and Power-Down Modes
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MODE |
PROGRAM MEMORY |
ALE |
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PSEN |
PORT 0 |
PORT 1 |
PORT 2 |
PORT 3 |
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Idle |
Internal |
1 |
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1 |
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Data |
Data |
Data |
Data |
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Idle |
External |
1 |
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1 |
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Float |
Data |
Address |
Data |
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Power-down |
Internal |
0 |
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0 |
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Data |
Data |
Data |
Data |
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Power-down |
External |
0 |
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0 |
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Float |
Data |
Data |
Data |
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Timer 0 and Timer 1
The ªTimerº or ªCounterº function is selected by control bits C/Tin the Special Function Register TMOD. These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different. The four operating modes are described in the following text.
Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. Figure 2 shows the Mode 0 operation.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The counted input is enabled to the Timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the
Timer to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a control bit in the Special Function Register TCON (Figure 3).
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers.
Mode 0 operation is the same for Timer 0 as for Timer 1. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Mode 1
Mode 1 is the same as Mode 0, except that the Timer register is being run with all 16 bits.
Mode 2
Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as shown in Figure 4. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which is preset by software. The reload leaves THn unchanged.
Mode 2 operation is the same for Timer 0 as for Timer 1.
Mode 3
Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The logic for Mode 3 on Timer 0 is shown in Figure 5. TL0 uses the Timer 0 control bits: C/T, GATE, TR0, and TF0 as well as pin INT0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus,
TH0 now controls the ªTimer 1º interrupt.
Mode 3 is provided for applications requiring an extra 8-bit timer on the counter. With Timer 0 in Mode 3, an 80C51 can look like it has three Timer/Counters. When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt.
2003 Jan 24 |
14 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
TMOD |
Address = 89H |
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Reset Value = 00H |
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Not Bit Addressable |
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0 |
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GATE |
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C/T |
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M1 |
M0 |
GATE |
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M1 |
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M0 |
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TIMER 1 |
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BIT |
SYMBOL |
FUNCTION |
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TMOD.3/ |
GATE |
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Gating control when set. Timer/Counter ªnº is enabled only while |
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ªINTnºpin is high and |
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TMOD.7 |
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ªTRnº control pin is set. when cleared Timer ªnº is enabled whenever ªTRnº control bit is set. |
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TMOD.2/ |
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Timer or Counter Selector cleared for Timer operation (input from internal system clock.) |
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C/T |
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TMOD.6 |
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Set for Counter operation (input from ªTnº input pin). |
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M1 |
M0 |
OPERATING |
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0 |
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0 |
8048 Timer: ªTLnº serves as 5-bit prescaler. |
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01 16-bit Timer/Counter: ªTHnº and ªTLnº are cascaded; there is no prescaler.
10 8-bit auto-reload Timer/Counter: ªTHnº holds a value which is to be reloaded into ªTLnº each time it overflows.
11 (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only controlled by Timer 1 control bits.
1 |
1 |
(Timer 1) Timer/Counter 1 stopped. |
SU01580
Figure 1. Timer/Counter 0/1 Mode Control (TMOD) Register
OSC |
d* |
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C/T = 0 |
TLn |
THn |
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TFn |
Interrupt |
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C/T = 1 |
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Tn Pin |
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Control |
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TRn |
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Timer n |
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Gate bit |
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INTn Pin |
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*d = 6 in 6-clock mode; d = 12 in 12-clock mode. |
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SU01618 |
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Figure 2. |
Timer/Counter 0/1 Mode 0: 13-Bit Timer/Counter |
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2003 Jan 24 |
15 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
TCON |
Address = 88H |
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Reset Value = 00H |
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Bit Addressable |
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7 |
6 |
5 |
4 |
3 |
2 |
1 |
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TF1 |
TR1 |
TF0 |
TR0 |
IE1 |
IT1 |
IE0 |
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IT0 |
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FUNCTION |
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TCON.7 |
TF1 |
Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. |
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Cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. |
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TCON.6 |
TR1 |
Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter on/off. |
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TCON.5 |
TF0 |
Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. |
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Cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. |
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TCON.4 |
TR0 |
Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter on/off. |
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TCON.3 |
IE1 |
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. |
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Cleared when interrupt processed. |
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TCON.2 |
IT1 |
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered |
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external interrupts. |
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TCON.1 |
IE0 |
Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. |
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Cleared when interrupt processed. |
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TCON.0 |
IT0 |
Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level |
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triggered external interrupts. |
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SU01516 |
Figure 3. Timer/Counter 0/1 Control (TCON) Register
OSC |
d* |
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C/T = 0 |
TLn |
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TFn |
Interrupt |
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(8 Bits) |
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C/T = 1 |
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Tn Pin |
Control |
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TRn |
Reload |
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Timer n |
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Gate bit |
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THn |
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INTn Pin |
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(8 Bits) |
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*d = 6 in 6-clock mode; d = 12 in 12-clock mode. |
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SU01619 |
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Figure 4. |
Timer/Counter 0/1 Mode 2: 8-Bit Auto-Reload |
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|
2003 Jan 24 |
16 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
OSC |
d* |
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C/T = 0 |
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TL0 |
TF0 |
Interrupt |
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(8 Bits) |
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C/T = 1 |
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T0 Pin |
Control |
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TR0 |
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Timer 0 |
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Gate bit |
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INT0 Pin |
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d* |
TH0 |
TF1 |
Interrupt |
OSC |
(8 Bits) |
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Control |
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TR1 |
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*d = 6 in 6-clock mode; d = 12 in 12-clock mode. |
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SU01620 |
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Figure 5. |
Timer/Counter 0 Mode 3: Two 8-Bit Counters |
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Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2 in the special function register T2CON (see Figure 6). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting), and Baud Rate
Generator, which are selected by bits in the T2CON as shown in Table 4.
Capture Mode
In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2 in T2CON) which, upon overflowing, sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register). If EXEN2=1, Timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 (like TF2) can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in
Figure 7 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 (12-clock Mode) or osc/6 (6-clock Mode) pulses).
Auto-Reload Mode (Up or Down Counter)
In the 16-bit auto-reload mode, Timer 2 can be configured as either a timer or counter (C/T2 in T2CON), then programmed to count up or down. The counting direction is determined by bit DCEN (Down
Counter Enable) which is located in the T2MOD register (see Figure 8). After reset, DCEN=0 which means Timer 2 will default to counting up. If DCEN is set, Timer 2 can count up or down depending on the value of the T2EX pin.
Figure 9 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software.
If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1.
In Figure 10 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX, Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2.
A logic 0 applied to pin T2EX causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. A Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2.
The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.
2003 Jan 24 |
17 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
Table 4. Timer 2 Operating Modes
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RCLK + TCLK |
CP/RL2 |
TR2 |
MODE |
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0 |
0 |
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1 |
16-bit Auto-reload |
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0 |
1 |
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1 |
16-bit Capture |
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1 |
X |
1 |
Baud rate generator |
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X |
X |
0 |
(off) |
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T2CON |
Address = C8H |
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Reset Value = 00H |
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Bit Addressable |
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7 |
6 |
5 |
4 |
3 |
2 |
1 |
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0 |
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TF2 |
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EXF2 |
RCLK |
TCLK |
EXEN2 |
TR2 |
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2 |
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C/T |
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CP/RL2 |
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Symbol |
Position |
Name and Significance |
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TF2 |
T2CON.7 |
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set |
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when either RCLK or TCLK = 1. |
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EXF2 |
T2CON.6 |
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and |
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EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 |
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interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down |
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counter mode (DCEN = 1). |
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RCLK |
T2CON.5 |
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock |
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in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. |
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TCLK |
T2CON.4 |
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock |
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in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. |
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EXEN2 |
T2CON.3 |
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative |
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transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to |
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ignore events at T2EX. |
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TR2 |
T2CON.2 |
Start/stop control for Timer 2. A logic 1 starts the timer. |
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2 |
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T2CON.1 |
Timer or counter select. (Timer 2) |
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C/T |
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0 = Internal timer (OSC/12 in 12-clock mode or OSC/6 in 6-clock mode) |
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1 = External event counter (falling edge triggered). |
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T2CON.0 |
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When |
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CP/RL2 |
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cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when |
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EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload |
on Timer 2 overflow.
SU01621
Figure 6. Timer/Counter 2 (T2CON) Control Register
2003 Jan 24 |
18 |
Philips Semiconductors |
Product data |
80C51 8-bit microcontroller family
4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz)
P80C3xX2; P80C5xX2;
P87C5xX2
OSC |
n* |
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C/T2 = 0 |
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TL2 |
TH2 |
TF2 |
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(8 bits) |
(8 bits) |
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C/T2 = 1 |
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T2 Pin |
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Control |
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TR2 |
Capture |
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Transition |
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Timer 2 |
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Detector |
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Interrupt |
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RCAP2L |
RCAP2H |
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T2EX Pin |
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EXF2 |
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Control |
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EXEN2 |
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SU01622 |
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*n = 6 in 6-clock mode; n = 12 in 12-clock mode. |
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Figure 7. Timer 2 in Capture Mode
T2MOD |
Address = 0C9H |
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Reset Value = XXXX XX00B |
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Not Bit Addressable |
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7 |
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6 |
5 |
4 |
3 |
2 |
1 |
0 |
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Ð |
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Ð |
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Ð |
Ð |
Ð |
Ð |
T2OE |
DCEN |
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Symbol |
Position |
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Function |
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Ð |
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Not implemented, reserved for future use.* |
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T2OE |
T2MOD.1 |
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Timer 2 Output Enable bit. |
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DCEN |
T2MOD.0 |
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Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down |
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counter. |
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* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
SU01519
Figure 8. Timer 2 Mode (T2MOD) Control Register
2003 Jan 24 |
19 |