Philips P82B96 User Guide

INTEGRATED CIRCUITS

P82B96

Dual bi-directional bus buffer

Product data	2004 Mar 29
Supersedes data of 2003 Apr 02

P s

on o s

Philips Semiconductors	Product data
Dual bi-directional bus buffer	P82B96

FEATURES

•Bi-directional data transfer of I2C-bus signals

•Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side

•Tx/Ty outputs have 60 mA sink capability for driving low impedance or high capacitive buses

•400 kHz operation over at least 20 meters of wire (see AN10148)

•Supply voltage range of 2 V to 15 V with I2C logic levels on Sx/Sy side independent of supply voltage

•Splits I2C signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with opto-electrical isolators and similar devices that need uni-directional input and output signal paths.

•Low power supply current

•ESD protection exceeds 3500 V HBM per JESD22-A114,

250 V DIP package / 400 V SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101

•Latch-up free (bipolar process with no latching structures)

•Packages offered: DIP, SO, and TSSOP

TYPICAL APPLICATIONS

•Interface between I2C buses operating at different logic levels

(e.g., 5 V and 3 V or 15 V)

•Interface between I2C and SMB (350 μA) bus standard.

•Simple conversion of I2C SDA or SCL signals to multi-drop differential bus hardware, e.g., via compatible PCA82C250.

•Interfaces with Opto-couplers to provide Opto isolation between I2C-bus nodes up to 400 kHz.

DESCRIPTION

The P82B96 is a bipolar IC that creates a non-latching, bi-directional, logic interface between the normal I2C-bus and a range of other bus configurations. It can interface I2C-bus logic signals to similar buses having different voltage and current levels.

For example it can interface to the 350 μA SMB bus, to 3.3 V logic devices, and to 15 V levels and/or low impedance lines to improve noise immunity on longer bus lengths.

It achieves this interface without any restrictions on the normal I2C protocols or clock speed. The IC adds minimal loading to the I2C node, and loadings of the new bus or remote I2C nodes are not transmitted or transformed to the local node. Restrictions on the number of I2C devices in a system, or the physical separation between them, are virtually eliminated. Transmitting SDA/SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bi-directional signal line with I2C properties.

PIN CONFIGURATIONS

8-pin dual in-line, SO, TSSOP

Sx	1				8	VCC
Rx	2				7	Sy
Tx	3				6	Ry
GND	4				5	Ty
					SU01011
PINNING
SYMBOL		PIN		DESCRIPTION
Sx		1		I2C-bus (SDA or SCL)
Rx		2		Receive signal
Tx		3		Transmit signal
GND		4		Negative Supply
Ty		5		Transmit signal
Ry		6		Receive signal
Sy		7		I2C-bus (SDA or SCL)
VCC		8		Positive supply

SPECIAL NOTE:

Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration. Bi-directional I2C signals do not allow any direction control pin so, instead, slightly different logic low voltage levels are used at Sx/Sy to avoid latching of this buffer. A ªregular2IC lowº applied at the Rx/Ry of a P82B96 will be propagated to Sx/Sy as a ªbuffered lowº with a slightly higher voltage level. If this special ªbuffered lowº is applied to the Sx/Sy of another P82B96 that second P82B96 will not recognize it as a ªregular2IC-bus lowº and will not propagate it to its Tx/Ty output.

The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example

PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended for, and compatible with, the normal I2C logic voltage levels of I2C master and slave chipsÐor even Tx/Rx signals of a second P82B96 if required. The Tx/Rx and Ty/Ry I/O pins use the standard I2C logic voltage levels of all I2C parts. There are NO restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave devices. For more details see Application

Note AN255.

2004 Mar 29

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Philips Semiconductors	Product data
Dual bi-directional bus buffer	P82B96

ORDERING INFORMATION

PACKAGES	TEMPERATURE RANGE	ORDER CODE	TOPSIDE MARK	DRAWING NUMBER
8-pin plastic dual In-line package	±40 °C to +85 °C	P82B96PN	P82B96PN	SOT97-1
8-pin plastic small outline package	±40 °C to +85 °C	P82B96TD	P82B96T	SOT96-1
8-pin plastic thin shrink small outline package	±40 °C to +85 °C	P82B96DP	82B96	SOT505-1

NOTE:

1. Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.

BLOCK DIAGRAM

			+VCC (2±15 V)
			8
	Sx (SDA)	1				3	Tx (TxD, SDA)
			2				Rx (RxD, SDA)
		7				5
	Sy (SCL)						Ty (TxD, SCL)
			6
							Ry (RxD, SCL)

P82B96

4

GND

SU01012

FUNCTIONAL DESCRIPTION

The P82B96 has two identical buffers allowing buffering of both of the I2C (SDA and SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the I2C interface pin which drives the buffered bus, and a reverse signal path from the buffered bus input to drive the I2C-bus interface.

Thus these paths are:

1.Sense the voltage state of the I2C pin Sx (or Sy) and transmit this state to the pin Tx (Ty resp.), and

2.Sense the state of the pin Rx (Ry) and pull the I2C pin LOW whenever Rx (Ry) is LOW.

The rest of this discussion will address only the ªxº side of the buffer: the ªyº side is identical.

The I2C pin (Sx) is designed to interface with a normal I2C-bus.

The logic threshold voltage levels on the I2C-bus are independent of the IC supply VCC The maximum I2C-bus supply voltage is 15 V and the guaranteed static sink current is 3 mA.

The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic LOW is below 42 % of VCC, and logic HIGH is above 58 % of VCC: with a typical switching threshold of half VCC.

Tx is an open collector output without ESD protection diodes to VCC. It may be connected via a pull-up resistor to a supply voltage in

excess of VCC, as long as the 15 V rating is not exceeded. It has a larger current sinking capability than a normal I2C device, being able

to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well.

A logic LOW is only transmitted to Tx when the voltage at the I2C pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I2C-bus (Sx) to be pulled to a logic LOW level in accordance with I2C requirements (max. 1.5 V in 5 V applications) but not low enough to be looped back to the Tx output and cause the buffer to latch LOW.

The minimum LOW level this chip can achieve on the I2C-bus by a LOW at Rx is typically 0.8 V.

If the supply voltage VCC fails, then neither the I2C nor the Tx output will be held LOW. Their open collector configuration allows them to be pulled up to the rated maximum of 15 V even without VCC present. The input configuration on Sx and Rx also present no loading of external signals even when VCC is not present.

The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 7 pF for all bus voltages and supply voltages including VCC = 0 V.

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Philips Semiconductors	Product data
Dual bi-directional bus buffer	P82B96

MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134).

Voltages with respect to pin GND (pin 4).

SYMBOL	PARAMETER	MIN.	MAX.	UNIT
VCC to GND	Supply voltage range VCC	±0.3	+18	V
Vbus	Voltage range on I2C Bus, SDA or SCL	±0.3	+18	V
VTx	Voltage range on buffered output	±0.3	+18	V
VRx	Voltage range on receive input	±0.3	+18	V
I	DC current (any pin)	Ð	250	mA
Rtot	Power dissipation	Ð	300	mW
Tstg	Storage temperature range	±55	+125	°C
Tamb	Operating ambient temperature range	±40	+85	°C

CHARACTERISTICS

At Tamb = 25 °C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Power Supply
VCC	Supply voltage (operating)		2.0	Ð	15	V
ICC	Supply current, buses HIGH		Ð	0.9	1.8	mA
ICC	Supply current at VCC = 15 V, buses HIGH		Ð	1.1	2.5	mA
ICC	Additional supply current per Tx or Ty LOW		Ð	1.7	3.5	mA

Bus pull-up (load) voltages and currents

VSx, VSy

Maximum input/output voltage level

Open collector;

Ð

Ð

15

V

I2C-bus and V

Rx

, V

Ry

= HIGH

I

Sx

, I

Sy

Static output loading on I2C-bus (Note 1)

V

Sx

, V

Sy

= 1.0 V;

0.2

Ð

3

mA

VRx, VRy = LOW

I

Sx

, I

Sy

Dynamic output sink capability on I2C-bus

V

Sx

, V

Sy

> 2 V;

7

18

Ð

mA

VRx, VRy = LOW

I

Sx

, I

Sy

Leakage current on I2C-bus

V

Sx

, V

Sy

= 5 V;

Ð

Ð

1

μA

VRx, VRy = HIGH

I

Sx

, I

Sy

Leakage current on I2C-bus

V

Sx

, V

Sy

= 15 V;

Ð

1

Ð

μA

VRx, VRy = HIGH

VTx, VTy

Maximum output voltage level

Open collector

Ð

Ð

15

V

ITx, ITy

Static output loading on buffered bus

VTx, VTy = 0.4 V;

Ð

Ð

30

mA

VSx, VSy = LOW on I2C-bus = 0.4 V

ITx, ITy

Dynamic output sink capability, buffered bus

VTx, VTy > 1 V

60

100

Ð

mA

VSx, VSy = LOW on I2C-bus = 0.4 V

ITx, ITy

Leakage current on buffered bus

VTx, VTy = VCC = 15 V;

Ð

1

Ð

μA

VSx, VSy = HIGH

Input Currents

I , I

Sy

Input current from I2C-bus

bus LOW

Ð

±1

Ð

μA

Sx

VRx, VRy = HIGH

IRx, IRy

Input current from buffered bus

bus LOW

Ð

±1

Ð

μA

VRx, VRy = 0.4 V

IRx, IRy

Leakage current on buffered bus input

VRx, VRy = VCC

Ð

1

Ð

μA

Output Logic LOW Levels

V

Sx

, V

Sy

Output logic level LOW, on normal I2C bus

I

Sx

, I

Sy

= 3 mA

0.8

0.88

1.0

V

(Note 2)

V

Sx

, V

Sy

Output logic level LOW, on normal I2C bus

I

Sx

, I

Sy

= 0.2 mA

670

730

790

mV

(Note 2)

dVSx/dT,

Temperature coefficient of output LOW

ISx, ISy = 0.2 mA

Ð

±1.8

Ð

mV/K

dVSy/dT

levels (Note 2)

2004 Mar 29

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Philips Semiconductors	Product data
Dual bi-directional bus buffer	P82B96

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Input logic switching threshold voltages
VSx, VSy	Input logic voltage LOW (Note 3)	On normal I2C-bus	Ð	640	600	mV
VSx, VSy	Input logic level HIGH threshold (Note 3)	On normal I2C-bus	700	650	Ð	mV

dVSx/dT,	Temperature coefficient of input thresholds		Ð	±2	Ð	mV/K
dVSy/dT
VRx, VRy	Input logic HIGH level	Fraction of applied VCC	0.58	Ð	Ð	V
VRx, VRy	Input threshold	Fraction of applied VCC	Ð	0.5	Ð	V
VRx, VRy	Input logic LOW level	Fraction of applied VCC	Ð	Ð	0.42	V
Logic level threshold difference

VSx, VSy	Input/Output logic level difference (Note 1)

VSX output LOW at 0.2 mA ±	50	85	Ð	mV
VSX input HIGH max

NOTES:

1.The minimum value requirement for pull-up current, 200 μA, guarantees that the minimum value for VSX output LOW will always exceed the minimum VSX input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While

the tolerances on absolute levels allow a small probability the LOW from one SX output is recognized by an SX input of another P82B96 this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked because the resulting system

would be very susceptible to induced noise and would not support all I2C operating modes.

2.The output logic LOW depends on the sink current. For scaling, see Application Note AN255.

3.The input logic threshold is independent of the supply voltage.

CHARACTERISTICS

At Tamb = 25 °C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated.

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Bus Release on VCC Failure
VSx, VSy,	VCC voltage at which all buses are		Ð	Ð	1	V
VTx, VTy	guaranteed to be released
dV/dT	Temperature coefficient of guaranteed release		Ð	±4	Ð	mV/K
	voltage

Buffer response time
Tfall delay	Buffer time delay on FALLING input between	RTx pull-up = 160 Ω,	Ð	70	Ð	ns
VSx to VTx	VSx = input switching threshold,	no capacitive load, VCC = 5 V
VSy to VTy	and VTx output falling 50%.
Trise delay	Buffer time delay on RISING input between	RTx pull-up = 160 Ω,	Ð	90	Ð	ns
VSx to VTx	VSx = input switching threshold,	no capacitive load, VCC = 5 V
VSy to VTy	and VTx output reaching 50% VCC
Tfall delay	Buffer time delay on FALLING input between	RSx pull-up = 1500 Ω, no	Ð	250	Ð	ns
VRx to VSx	VRx = input switching threshold,	capacitive load, VCC = 5 V
VRy to VSy	and VSx output falling 50%.
Trise delay	Buffer time delay on RISING input between	RSx pull-up = 1500 Ω,	Ð	270	Ð	ns
VRx to VSx	VRx = input switching threshold,	no capacitive load, VCC = 5 V
VRy to VSy	and VSx output reaching 50% VCC
Input capacitance
Cin	Effective input capacitance of any signal pin		Ð	Ð	7	pF
	measured by incremental bus rise times
NOTES ON RESPONSE TIME
The fall-time of VTX from 5 V to 2.5 V in the test is approximately 15 ns.
The fall-time of VSX from 5 V to 2.5 V in the test is approximately 50 ns.
The rise-time of VTX from 0 V to 2.5 V in the test is approximately 20 ns.
The rise-time of VSX from 0.9 V to 2.5 V in the test is approximately 70 ns.

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