Philips P82B96 User Guide
INTEGRATED CIRCUITS
P82B96
Dual bi-directional bus buffer
Product data
Supersedes data of 2003 Apr 02
2004 Mar 29
Philips Semiconductors Product data
P82B96Dual bi-directional bus buffer
PIN CONFIGURATIONS
8-pin dual in-line, SO, TSSOP
FEATURES
•Bi-directional data transfer of I
2
C-bus signals
•Isolates capacitance allowing 400 pF on Sx/Sy side and
4000 pF on Tx/Ty side
•Tx/Ty outputs have 60 mA sink capability for driving
low impedance or high capacitive buses
•400 kHz operation over at least 20 meters of wire (see
•Supply voltage range of 2 V to 15 V with I
side independent of supply voltage
•Splits I
2
C signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals
for interface with opto-electrical isolators and similar devices that
need uni-directional input and output signal paths.
2
C logic levels on Sx/Sy
AN10148
•Low power supply current
•ESD protection exceeds 3500 V HBM per JESD22-A114,
250 V DIP package / 400 V SO package MM per JESD22-A115,
and 1000 V CDM per JESD22-C101
•Latch-up free (bipolar process with no latching structures)
•Packages offered: DIP, SO, and TSSOP
TYPICAL APPLICATIONS
•Interface between I
(e.g., 5 V and 3 V or 15 V)
•Interface between I
•Simple conversion of I
differential bus hardware, e.g., via compatible PCA82C250.
2
C buses operating at different logic levels
2
C and SMB (350 µA) bus standard.
2
C SDA or SCL signals to multi-drop
•Interfaces with Opto-couplers to provide Opto isolation between
2
C-bus nodes up to 400 kHz.
I
DESCRIPTION
The P82B96 is a bipolar IC that creates a non-latching,
bi-directional, logic interface between the normal I
range of other bus configurations. It can interface I
signals to similar buses having different voltage and current levels.
For example it can interface to the 350 µA SMB bus, to 3.3 V logic
devices, and to 15 V levels and/or low impedance lines to improve
noise immunity on longer bus lengths.
It achieves this interface without any restrictions on the normal I
protocols or clock speed. The IC adds minimal loading to the I
node, and loadings of the new bus or remote I
transmitted or transformed to the local node. Restrictions on the
number of I
between them, are virtually eliminated. Transmitting SDA/SCL
signals via balanced transmission lines (twisted pairs) or with
galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals
may be directly connected, without causing latching, to provide an
alternative bi-directional signal line with I
2
C devices in a system, or the physical separation
2
2
C-bus and a
2
C-bus logic
2
C nodes are not
C properties.
2
2
C
1
2
Rx
3
Tx
45
GND Ty
)
C
PINNING
SYMBOL
Sx
Rx
Tx
GND
Ty
Ry
Sy
V
CC
SPECIAL NOTE:
Two or more Sx or Sy I/Os must not be interconnected. The P82B96
design does not support this configuration. Bi-directional I
do not allow any direction control pin so, instead, slightly different
logic low voltage levels are used at Sx/Sy to avoid latching of this
buffer . A “regular I
propagated to Sx/Sy as a “buffered low” with a slightly higher
voltage level. If this special “buffered low” is applied to the Sx/Sy of
another P82B96 that second P82B96 will not recognize it as a
“regular I
The Sx/Sy side of P82B96 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example
PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended
for, and compatible with, the normal I2C logic voltage levels of I2C
master and slave chips—or even Tx/Rx signals of a second P82B96
if required. The Tx/Rx and Ty/Ry I/O pins use the standard I
voltage levels of all I
interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s,
for example in a star or multi-point configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to
the line card slave devices. For more details see
Note AN255
2
C-bus low” and will not propagate it to its Tx/Ty output.
.
PIN
1
I2C-bus (SDA or SCL)
2
Receive signal
3
Transmit signal
4
Negative Supply
5
Transmit signal
6
Receive signal
7
I2C-bus (SDA or SCL)
8
Positive supply
2
C low” applied at the Rx/Ry of a P82B96 will be
2
C parts. There are NO restrictions on the
8Sx
V
CC
7
Sy
6
Ry
SU01011
DESCRIPTION
Application
2
C signals
2
C logic
2004 Mar 29
2
Philips Semiconductors Product data
P82B96Dual bi-directional bus buffer
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER
8-pin plastic dual In-line package –40 °C to +85 °C P82B96PN P82B96PN SOT97-1
8-pin plastic small outline package –40 °C to +85 °C P82B96TD P82B96T SOT96-1
8-pin plastic thin shrink small outline package –40 °C to +85 °C P82B96DP 82B96 SOT505-1
NOTE:
1. Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.
BLOCK DIAGRAM
+V
(2–15 V)
CC
8
Sx (SDA)
Sy (SCL)
1
7
P82B96
GND
FUNCTIONAL DESCRIPTION
The P82B96 has two identical buffers allowing buffering of both of
2
the I
C (SDA and SCL) signals. Each buffer is made up of two logic
signal paths, a forward path from the I
the buffered bus, and a reverse signal path from the buffered bus
input to drive the I
2
C-bus interface.
Thus these paths are:
1. Sense the voltage state of the I
this state to the pin Tx (Ty resp.), and
2. Sense the state of the pin Rx (Ry) and pull the I
whenever Rx (Ry) is LOW.
The rest of this discussion will address only the “x” side of the buffer:
the “y” side is identical.
2
The I
C pin (Sx) is designed to interface with a normal I2C-bus.
The logic threshold voltage levels on the I2C-bus are independent of
the IC supply V
The maximum I2C-bus supply voltage is 15 V and
CC
the guaranteed static sink current is 3 mA.
The logic level of Rx is determined from the power supply voltage
V
of the chip. Logic LOW is below 42 % of VCC, and logic HIGH is
CC
above 58 % of V
: with a typical switching threshold of half V
CC
2
C interface pin which drives
2
C pin Sx (or Sy) and transmit
2
C pin LOW
CC.
3
Tx (TxD, SDA)
2
Rx (RxD, SDA)
5
Ty (TxD, SCL)
6
Ry (RxD, SCL)
4
SU01012
Tx is an open collector output without ESD protection diodes to VCC.
It may be connected via a pull-up resistor to a supply voltage in
excess of V
larger current sinking capability than a normal I
as long as the 15 V rating is not exceeded. It has a
CC,
2
C device, being able
to sink a static current of greater than 30 mA, and typical 100 mA
dynamic pull-down capability as well.
A logic LOW is only transmitted to Tx when the voltage at the I
pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I
(Sx) to be pulled to a logic LOW level in accordance with I
requirements (max. 1.5 V in 5 V applications) but not low enough to
be looped back to the Tx output and cause the buffer to latch LOW.
The minimum LOW level this chip can achieve on the I
LOW at Rx is typically 0.8 V.
If the supply voltage V
fails, then neither the I2C nor the Tx output
CC
will be held LOW. Their open collector configuration allows them to
be pulled up to the rated maximum of 15 V even without V
present. The input configuration on Sx and Rx also present no
loading of external signals even when V
is not present.
CC
The effective input capacitance of any signal pin, measured by its
effect on bus rise times, is less than 7 pF for all bus voltages and
supply voltages including V
CC
= 0 V.
2
C-bus
2
C
2
C-bus by a
CC
2
C
2004 Mar 29
3
Philips Semiconductors Product data
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P82B96Dual bi-directional bus buffer
MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages with respect to pin GND (pin 4).
SYMBOL
VCC to GND
V
bus
V
Tx
V
Rx
I
R
tot
T
stg
T
amb
Supply voltage range V
CC
Voltage range on I2C Bus, SDA or SCL
Voltage range on buffered output
Voltage range on receive input
DC current (any pin)
Power dissipation
Storage temperature range
Operating ambient temperature range
CHARACTERISTICS
At T
= 25 °C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated.
amb
SYMBOL
Power Supply
V
CC
I
CC
I
CC
I
CC
Supply voltage (operating)
Supply current, buses HIGH
Supply current at VCC = 15 V, buses HIGH
Additional supply current per Tx or Ty LOW
Bus pull-up (load) voltages and currents
VSx, V
Sy
ÁÁÁ
ISx, I
Sy
ISx, I
Sy
ÁÁÁ
ISx, I
Sy
ISx, I
Sy
ÁÁÁ
VTx, V
Ty
ITx, I
Ty
ITx, I
Ty
ÁÁÁ
ITx, I
Ty
Maximum input/output voltage level
БББББББББ
Static output loading on I2C-bus (Note 1)
Dynamic output sink capability on I2C-bus
БББББББББ
Leakage current on I2C-bus
Leakage current on I2C-bus
БББББББББ
Maximum output voltage level
Static output loading on buffered bus
Dynamic output sink capability, buf fered bus
БББББББББ
Leakage current on buffered bus
Input Currents
ISx, I
Sy
ÁÁÁ
IRx, I
Ry
IRx, I
Ry
Input current from I2C-bus
БББББББББ
Input current from buffered bus
Leakage current on buffered bus input
Output Logic LOW Levels
VSx, V
Sy
VSx, V
Sy
ÁÁÁ
dVSx/dT,
dV
/dT
Sy
Output logic level LOW, on normal I2C bus
(Note 2)
Output logic level LOW, on normal I2C bus
БББББББББ
(Note 2)
Temperature coefficient of output LOW
levels (Note 2)
PARAMETER
PARAMETER
CONDITIONS
Open collector;
2
I
C-bus and VRx, VRy = HIGH
ББББББББ
VSx, VSy = 1.0 V;
V
, VRy = LOW
Rx
VSx, VSy > 2 V;
, VRy = LOW
V
ББББББББ
Rx
VSx, VSy = 5 V;
V
, VRy = HIGH
Rx
VSx, VSy = 15 V;
V
, VRy = HIGH
ББББББББ
Rx
Open collector
VTx, V
V
= 0.4 V;
Ty
, VSy = LOW on I2C-bus = 0.4 V
Sx
VTx, VTy > 1 V
V
, VSy = LOW on I2C-bus = 0.4 V
Sx
ББББББББ
VTx, VTy = VCC = 15 V;
V
, VSy = HIGH
Sx
bus LOW
V
ББББББББ
, V
= HIGH
Rx
Ry
bus LOW
, VRy = 0.4 V
V
Rx
VRx, V
= V
Ry
CC
ISx, ISy = 3 mA
ISx, ISy = 0.2 mA
ББББББББ
ISx, ISy = 0.2 mA
MIN.
–0.3
–0.3
–0.3
–0.3
—
—
–55
–40
MIN.
2.0
—
—
—
—
ÁÁ
0.2
7
ÁÁ
—
—
ÁÁ
—
—
60
ÁÁ
—
—
ÁÁ
—
—
0.8
670
ÁÁ
—
TYP.
—
0.9
1.1
1.7
—
Á
—
18
Á
—
1
Á
—
—
100
Á
1
–1
Á
–1
1
0.88
730
Á
–1.8
MAX.
+18
+18
+18
+18
250
300
+125
+85
MAX.
15
1.8
2.5
3.5
15
Á
3
—
Á
1
—
Á
15
30
—
Á
—
—
Á
—
—
1.0
790
Á
—
UNIT
V
V
V
V
mA
mW
°C
°C
UNIT
V
mA
mA
mA
V
ÁÁ
mA
mA
ÁÁ
µA
µA
ÁÁ
V
mA
mA
ÁÁ
µA
µA
ÁÁ
µA
µA
V
mV
ÁÁ
mV/K
2004 Mar 29
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P82B96Dual bi-directional bus buffer
SYMBOL
PARAMETER
CONDITIONS
Input logic switching threshold voltages
VSx, V
Sy
VSx, V
Sy
dVSx/dT,
dV
/dT
ÁÁÁ
Sy
VRx, V
Ry
VRx, V
Ry
VRx, V
Ry
Input logic voltage LOW (Note 3)
Input logic level HIGH threshold (Note 3)
Temperature coefficient of input thresholds
БББББББББ
Input logic HIGH level
Input threshold
Input logic LOW level
On normal I2C-bus
On normal I2C-bus
ББББББББÁÁÁ
Fraction of applied V
Fraction of applied V
Fraction of applied V
CC
CC
CC
Logic level threshold difference
VSx, V
Sy
ÁÁÁ
Input/Output logic level difference (Note 1)
БББББББББ
VSX output LOW at 0.2 mA –
V
input HIGH max
ББББББББ
SX
NOTES:
1. The minimum value requirement for pull-up current, 200 µA, guarantees that the minimum value for V
minimum V
the tolerances on absolute levels allow a small probability the LOW from one S
has no consequences for normal applications. In any design the S
would be very susceptible to induced noise and would not support all I
2. The output logic LOW depends on the sink current. For scaling, see
input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While
SX
pins of different ICs should never be linked because the resulting system
X
2
C operating modes.
Application Note AN255
output is recognized by an SX input of another P82B96 this
X
.
3. The input logic threshold is independent of the supply voltage.
CHARACTERISTICS
At T
= 25 °C; Voltages are specified with respect to GND with V
amb
SYMBOL
PARAMETER
Bus Release on VCC Failure
VSx, VSy,
V
, V
ÁÁÁ
Tx
Ty
dV/dT
V
voltage at which all buses are
CC
guaranteed to be released
ББББББББББ
Temperature coefficient of guaranteed release
voltage
Buffer response time
T
fall delay
VSx to V
ÁÁÁ
VSy to V
T
rise delay
ÁÁÁ
VSx to V
VSy to V
ÁÁÁ
T
fall delay
ÁÁÁ
VRx to V
VRy to V
ÁÁÁ
T
rise delay
VRx to V
ÁÁÁ
VRy to V
Buffer time delay on F ALLING input between
V
= input switching threshold,
Tx
Ty
Tx
Ty
Sx
Sy
ББББББББББ
Sx
and V
output falling 50%.
Tx
Buffer time delay on RISING input between
ББББББББББ
V
= input switching threshold,
Sx
and V
output reaching 50% V
Tx
ББББББББББ
Buffer time delay on F ALLING input between
ББББББББББ
V
= input switching threshold,
Rx
and V
output falling 50%.
Sx
ББББББББББ
Buffer time delay on RISING input between
V
Sx
Sy
= input switching threshold,
Rx
ББББББББББ
and V
output reaching 50% V
Sx
Input capacitance
C
in
Effective input capacitance of any signal pin
measured by incremental bus rise times
NOTES ON RESPONSE TIME
The fall-time of V
The fall-time of V
The rise-time of V
The rise-time of V
from 5 V to 2.5 V in the test is approximately 15 ns.
TX
from 5 V to 2.5 V in the test is approximately 50 ns.
SX
from 0 V to 2.5 V in the test is approximately 20 ns.
TX
from 0.9 V to 2.5 V in the test is approximately 70 ns.
SX
CC
CC
= 5 V unless otherwise stated.
CC
CONDITIONS
ББББББÁÁÁ
MIN.
RTx pull-up = 160 Ω,
no capacitive load, V
ББББББ
RTx pull-up = 160 Ω,
ББББББ
no capacitive load, V
ББББББ
RSx pull-up = 1500 Ω, no
ББББББ
capacitive load, V
ББББББ
CC
CC
CC
= 5 V
= 5 V
= 5 V
ÁÁ
ÁÁ
ÁÁ
ÁÁ
ÁÁ
RSx pull-up = 1500 Ω,
no capacitive load, V
ББББББ
CC
= 5 V
ÁÁ
–2
Á
—
—
85
Á
MAX.
600
—
—
Á
—
—
0.42
—
Á
MAX.
1
Á
—
—
Á
—
Á
Á
—
Á
Á
—
Á
7
MIN.
—
700
TYP.
640
650
—
0.58
—
0.5
—
50
ÁÁ
output LOW will always exceed the
SX
TYP.
—
—
—
—
—
—
—
—
ÁÁ
–4
70
ÁÁ
90
ÁÁ
ÁÁ
250
ÁÁ
ÁÁ
270
ÁÁ
—
UNIT
mV
mV
mV/K
ÁÁ
V
V
V
mV
ÁÁ
UNIT
V
ÁÁ
mV/K
ns
ÁÁ
ns
ÁÁ
ÁÁ
ns
ÁÁ
ÁÁ
ns
ÁÁ
pF
2004 Mar 29
5
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