Philips P82B96 User Guide

INTEGRATED CIRCUITS

P82B96

Dual bi-directional bus buffer

Product data
Supersedes data of 2003 Apr 02

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2004 Mar 29

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

PIN CONFIGURATIONS
8-pin dual in-line, SO, TSSOP

FEATURES

•Bi-directional data transfer of I

2

C-bus signals

•Isolates capacitance allowing 400 pF on Sx/Sy side and

4000 pF on Tx/Ty side

•Tx/Ty outputs have 60 mA sink capability for driving

low impedance or high capacitive buses

•400 kHz operation over at least 20 meters of wire (see

•Supply voltage range of 2 V to 15 V with I

side independent of supply voltage

•Splits I

2

C signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals

for interface with opto-electrical isolators and similar devices that
need uni-directional input and output signal paths.

2

C logic levels on Sx/Sy

AN10148

•Low power supply current

•ESD protection exceeds 3500 V HBM per JESD22-A114,

250 V DIP package / 400 V SO package MM per JESD22-A115,
and 1000 V CDM per JESD22-C101

•Latch-up free (bipolar process with no latching structures)

•Packages offered: DIP, SO, and TSSOP

TYPICAL APPLICATIONS

•Interface between I

(e.g., 5 V and 3 V or 15 V)

•Interface between I

•Simple conversion of I

differential bus hardware, e.g., via compatible PCA82C250.

2

C buses operating at different logic levels

2

C and SMB (350 µA) bus standard.

2

C SDA or SCL signals to multi-drop

•Interfaces with Opto-couplers to provide Opto isolation between

2

C-bus nodes up to 400 kHz.

I

DESCRIPTION

The P82B96 is a bipolar IC that creates a non-latching,
bi-directional, logic interface between the normal I
range of other bus configurations. It can interface I
signals to similar buses having different voltage and current levels.

For example it can interface to the 350 µA SMB bus, to 3.3 V logic
devices, and to 15 V levels and/or low impedance lines to improve
noise immunity on longer bus lengths.

It achieves this interface without any restrictions on the normal I
protocols or clock speed. The IC adds minimal loading to the I
node, and loadings of the new bus or remote I
transmitted or transformed to the local node. Restrictions on the
number of I
between them, are virtually eliminated. Transmitting SDA/SCL
signals via balanced transmission lines (twisted pairs) or with
galvanic isolation (opto-coupling) is simple because separate
directional Tx and Rx signals are provided. The Tx and Rx signals
may be directly connected, without causing latching, to provide an
alternative bi-directional signal line with I

2

C devices in a system, or the physical separation

2

2

C-bus and a

2

C-bus logic

2

C nodes are not

C properties.

2

2

C

1

2

Rx

3

Tx

45

GND Ty

)

C

PINNING

SYMBOL

Sx
Rx
Tx

GND

Ty
Ry
Sy

V

CC

SPECIAL NOTE:

Two or more Sx or Sy I/Os must not be interconnected. The P82B96
design does not support this configuration. Bi-directional I
do not allow any direction control pin so, instead, slightly different
logic low voltage levels are used at Sx/Sy to avoid latching of this
buffer . A “regular I
propagated to Sx/Sy as a “buffered low” with a slightly higher
voltage level. If this special “buffered low” is applied to the Sx/Sy of
another P82B96 that second P82B96 will not recognize it as a
“regular I
The Sx/Sy side of P82B96 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example
PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended
for, and compatible with, the normal I2C logic voltage levels of I2C
master and slave chips—or even Tx/Rx signals of a second P82B96
if required. The Tx/Rx and Ty/Ry I/O pins use the standard I
voltage levels of all I
interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s,
for example in a star or multi-point configuration with the Tx/Rx and
Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to
the line card slave devices. For more details see

Note AN255

2

C-bus low” and will not propagate it to its Tx/Ty output.

.

PIN

1

I2C-bus (SDA or SCL)

2

Receive signal

3

Transmit signal

4

Negative Supply

5

Transmit signal

6

Receive signal

7

I2C-bus (SDA or SCL)

8

Positive supply

2

C low” applied at the Rx/Ry of a P82B96 will be

2

C parts. There are NO restrictions on the

8Sx

V

CC

7

Sy

6

Ry

SU01011

DESCRIPTION

Application

2

C signals

2

C logic

2004 Mar 29

2

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE TOPSIDE MARK DRAWING NUMBER

8-pin plastic dual In-line package –40 °C to +85 °C P82B96PN P82B96PN SOT97-1
8-pin plastic small outline package –40 °C to +85 °C P82B96TD P82B96T SOT96-1
8-pin plastic thin shrink small outline package –40 °C to +85 °C P82B96DP 82B96 SOT505-1

NOTE:

1. Standard packing quantities and other packaging data are available at www.philipslogic.com/packaging.

BLOCK DIAGRAM

+V

(2–15 V)

CC

8

Sx (SDA)

Sy (SCL)

1

7

P82B96

GND

FUNCTIONAL DESCRIPTION

The P82B96 has two identical buffers allowing buffering of both of

2

the I

C (SDA and SCL) signals. Each buffer is made up of two logic
signal paths, a forward path from the I
the buffered bus, and a reverse signal path from the buffered bus
input to drive the I

2

C-bus interface.

Thus these paths are:

1. Sense the voltage state of the I

this state to the pin Tx (Ty resp.), and

2. Sense the state of the pin Rx (Ry) and pull the I

whenever Rx (Ry) is LOW.

The rest of this discussion will address only the “x” side of the buffer:
the “y” side is identical.

2

The I

C pin (Sx) is designed to interface with a normal I2C-bus.

The logic threshold voltage levels on the I2C-bus are independent of
the IC supply V

The maximum I2C-bus supply voltage is 15 V and

CC

the guaranteed static sink current is 3 mA.
The logic level of Rx is determined from the power supply voltage

V

of the chip. Logic LOW is below 42 % of VCC, and logic HIGH is

CC

above 58 % of V

: with a typical switching threshold of half V

CC

2

C interface pin which drives

2

C pin Sx (or Sy) and transmit

2

C pin LOW

CC.

3

Tx (TxD, SDA)

2

Rx (RxD, SDA)

5

Ty (TxD, SCL)

6

Ry (RxD, SCL)

4

SU01012

Tx is an open collector output without ESD protection diodes to VCC.
It may be connected via a pull-up resistor to a supply voltage in
excess of V
larger current sinking capability than a normal I

as long as the 15 V rating is not exceeded. It has a

CC,

2

C device, being able
to sink a static current of greater than 30 mA, and typical 100 mA
dynamic pull-down capability as well.

A logic LOW is only transmitted to Tx when the voltage at the I
pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I
(Sx) to be pulled to a logic LOW level in accordance with I
requirements (max. 1.5 V in 5 V applications) but not low enough to
be looped back to the Tx output and cause the buffer to latch LOW.

The minimum LOW level this chip can achieve on the I
LOW at Rx is typically 0.8 V.

If the supply voltage V

fails, then neither the I2C nor the Tx output

CC

will be held LOW. Their open collector configuration allows them to
be pulled up to the rated maximum of 15 V even without V
present. The input configuration on Sx and Rx also present no
loading of external signals even when V

is not present.

CC

The effective input capacitance of any signal pin, measured by its
effect on bus rise times, is less than 7 pF for all bus voltages and
supply voltages including V

CC

= 0 V.

2

C-bus

2

C

2

C-bus by a

CC

2

C

2004 Mar 29

3

Philips Semiconductors Product data

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P82B96Dual bi-directional bus buffer

MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages with respect to pin GND (pin 4).

SYMBOL

VCC to GND
V

bus

V

Tx

V

Rx

I
R

tot

T

stg

T

amb

Supply voltage range V

CC

Voltage range on I2C Bus, SDA or SCL
Voltage range on buffered output
Voltage range on receive input
DC current (any pin)
Power dissipation
Storage temperature range
Operating ambient temperature range

CHARACTERISTICS

At T

= 25 °C; Voltages are specified with respect to GND with VCC = 5 V unless otherwise stated.

amb

SYMBOL

Power Supply

V

CC

I

CC

I

CC

I

CC

Supply voltage (operating)
Supply current, buses HIGH
Supply current at VCC = 15 V, buses HIGH
Additional supply current per Tx or Ty LOW

Bus pull-up (load) voltages and currents

VSx, V

Sy

ÁÁÁ

ISx, I

Sy

ISx, I

Sy

ÁÁÁ

ISx, I

Sy

ISx, I

Sy

ÁÁÁ

VTx, V

Ty

ITx, I

Ty

ITx, I

Ty

ÁÁÁ

ITx, I

Ty

Maximum input/output voltage level

БББББББББ

Static output loading on I2C-bus (Note 1)

Dynamic output sink capability on I2C-bus

БББББББББ

Leakage current on I2C-bus

Leakage current on I2C-bus

БББББББББ

Maximum output voltage level
Static output loading on buffered bus

Dynamic output sink capability, buf fered bus

БББББББББ

Leakage current on buffered bus

Input Currents

ISx, I

Sy

ÁÁÁ

IRx, I

Ry

IRx, I

Ry

Input current from I2C-bus

БББББББББ

Input current from buffered bus

Leakage current on buffered bus input

Output Logic LOW Levels

VSx, V

Sy

VSx, V

Sy

ÁÁÁ

dVSx/dT,
dV

/dT

Sy

Output logic level LOW, on normal I2C bus
(Note 2)

Output logic level LOW, on normal I2C bus

БББББББББ

(Note 2)
Temperature coefficient of output LOW

levels (Note 2)

PARAMETER

PARAMETER

CONDITIONS

Open collector;

2

I

C-bus and VRx, VRy = HIGH

ББББББББ

VSx, VSy = 1.0 V;
V

, VRy = LOW

Rx

VSx, VSy > 2 V;

, VRy = LOW

V

ББББББББ

Rx

VSx, VSy = 5 V;
V

, VRy = HIGH

Rx

VSx, VSy = 15 V;
V

, VRy = HIGH

ББББББББ

Rx

Open collector
VTx, V

V

= 0.4 V;

Ty

, VSy = LOW on I2C-bus = 0.4 V

Sx

VTx, VTy > 1 V
V

, VSy = LOW on I2C-bus = 0.4 V

Sx

ББББББББ

VTx, VTy = VCC = 15 V;
V

, VSy = HIGH

Sx

bus LOW
V

ББББББББ

, V

= HIGH

Rx

Ry

bus LOW

, VRy = 0.4 V

V

Rx

VRx, V

= V

Ry

CC

ISx, ISy = 3 mA

ISx, ISy = 0.2 mA

ББББББББ

ISx, ISy = 0.2 mA

MIN.

–0.3
–0.3
–0.3
–0.3

—

—
–55
–40

MIN.

2.0
—
—
—

—

ÁÁ

0.2

7

ÁÁ

—

—

ÁÁ

—
—

60

ÁÁ

—

—

ÁÁ

—

—

0.8

670

ÁÁ

—

TYP.

—

0.9

1.1

1.7

—

Á

—

18

Á

—

1

Á

—
—

100

Á

1

–1

Á

–1

1

0.88

730

Á

–1.8

MAX.

+18
+18
+18
+18
250
300

+125

+85

MAX.

15

1.8

2.5

3.5

15

Á

3

—

Á

1

—

Á

15
30

—

Á

—

—

Á

—

—

1.0

790

Á

—

UNIT

V
V
V
V

mA

mW

°C
°C

UNIT

V
mA
mA
mA

V

ÁÁ

mA

mA

ÁÁ

µA

µA

ÁÁ

V
mA

mA

ÁÁ

µA

µA

ÁÁ

µA

µA

V

mV

ÁÁ

mV/K

2004 Mar 29

4

Philips Semiconductors Product data

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P82B96Dual bi-directional bus buffer

SYMBOL

PARAMETER

CONDITIONS

Input logic switching threshold voltages

VSx, V

Sy

VSx, V

Sy

dVSx/dT,
dV

/dT

ÁÁÁ

Sy

VRx, V

Ry

VRx, V

Ry

VRx, V

Ry

Input logic voltage LOW (Note 3)
Input logic level HIGH threshold (Note 3)
Temperature coefficient of input thresholds

БББББББББ

Input logic HIGH level
Input threshold
Input logic LOW level

On normal I2C-bus
On normal I2C-bus

ББББББББÁÁÁ

Fraction of applied V
Fraction of applied V
Fraction of applied V

CC
CC
CC

Logic level threshold difference

VSx, V

Sy

ÁÁÁ

Input/Output logic level difference (Note 1)

БББББББББ

VSX output LOW at 0.2 mA –
V

input HIGH max

ББББББББ

SX

NOTES:

1. The minimum value requirement for pull-up current, 200 µA, guarantees that the minimum value for V
minimum V
the tolerances on absolute levels allow a small probability the LOW from one S

has no consequences for normal applications. In any design the S

would be very susceptible to induced noise and would not support all I

2. The output logic LOW depends on the sink current. For scaling, see

input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While

SX

pins of different ICs should never be linked because the resulting system

X

2

C operating modes.

Application Note AN255

output is recognized by an SX input of another P82B96 this

X

.

3. The input logic threshold is independent of the supply voltage.

CHARACTERISTICS

At T

= 25 °C; Voltages are specified with respect to GND with V

amb

SYMBOL

PARAMETER

Bus Release on VCC Failure

VSx, VSy,
V

, V

ÁÁÁ

Tx

Ty

dV/dT

V

voltage at which all buses are

CC

guaranteed to be released

ББББББББББ

Temperature coefficient of guaranteed release
voltage

Buffer response time

T

fall delay

VSx to V

ÁÁÁ

VSy to V
T

rise delay

ÁÁÁ

VSx to V
VSy to V

ÁÁÁ

T

fall delay

ÁÁÁ

VRx to V
VRy to V

ÁÁÁ

T

rise delay

VRx to V

ÁÁÁ

VRy to V

Buffer time delay on F ALLING input between
V

= input switching threshold,

Tx
Ty

Tx
Ty

Sx
Sy

ББББББББББ

Sx

and V

output falling 50%.

Tx

Buffer time delay on RISING input between

ББББББББББ

V

= input switching threshold,

Sx

and V

output reaching 50% V

Tx

ББББББББББ

Buffer time delay on F ALLING input between

ББББББББББ

V

= input switching threshold,

Rx

and V

output falling 50%.

Sx

ББББББББББ

Buffer time delay on RISING input between
V

Sx
Sy

= input switching threshold,

Rx

ББББББББББ

and V

output reaching 50% V

Sx

Input capacitance

C

in

Effective input capacitance of any signal pin
measured by incremental bus rise times

NOTES ON RESPONSE TIME

The fall-time of V
The fall-time of V
The rise-time of V
The rise-time of V

from 5 V to 2.5 V in the test is approximately 15 ns.

TX

from 5 V to 2.5 V in the test is approximately 50 ns.

SX

from 0 V to 2.5 V in the test is approximately 20 ns.

TX

from 0.9 V to 2.5 V in the test is approximately 70 ns.

SX

CC

CC

= 5 V unless otherwise stated.

CC

CONDITIONS

ББББББÁÁÁ

MIN.

RTx pull-up = 160 Ω,
no capacitive load, V

ББББББ

RTx pull-up = 160 Ω,

ББББББ

no capacitive load, V

ББББББ

RSx pull-up = 1500 Ω, no

ББББББ

capacitive load, V

ББББББ

CC

CC

CC

= 5 V

= 5 V

= 5 V

ÁÁ

ÁÁ

ÁÁ

ÁÁ

ÁÁ

RSx pull-up = 1500 Ω,
no capacitive load, V

ББББББ

CC

= 5 V

ÁÁ

–2

Á

—

—

85

Á

MAX.

600

—
—

Á

—
—

0.42

—

Á

MAX.

1

Á

—

—

Á

—

Á

Á

—

Á

Á

—

Á

7

MIN.

—

700

TYP.

640
650

—

0.58
—

0.5

—

50

ÁÁ

output LOW will always exceed the

SX

TYP.

—

—

—

—

—

—

—

—

ÁÁ

–4

70

ÁÁ

90

ÁÁ

ÁÁ

250

ÁÁ

ÁÁ

270

ÁÁ

—

UNIT

mV
mV

mV/K

ÁÁ

V
V
V

mV

ÁÁ

UNIT

V

ÁÁ

mV/K

ns

ÁÁ

ns

ÁÁ

ÁÁ

ns

ÁÁ

ÁÁ

ns

ÁÁ

pF

2004 Mar 29

5

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

TYPICAL APPLICATIONS

See

AN460

and

AN255

for more application detail.

+V

(2–15 V)

CC

+5 V

R1

I2C
SDA

Tx

(SDA)

Rx

1/2 PB2B96

(SDA)

Figure 1. Interfacing an ‘I2C’ type of bus with different logic levels.

‘SDA’

(NEW LEVELS)

SU01013

3.3–5 V

+V

CC1

R4

R5

2

I

C

SDA

I2C
SDA

+V

CC

R2

R3

+5 V

R1

Rx

(SDA)

Tx

(SDA)

1/2 P82B96

SU01014

Figure 2. Galvanic isolation of I2C nodes via opto-couplers

MAIN ENCLOSURE REMOTE CONTROL ENCLOSURE

12 V

LONG CABLES

12 V

3.3–5 V

SCL

SDA

2004 Mar 29

3.3–5 V

P82B96

12 V

Figure 3. Long distance I2C communications

6

SCL

3.3–5 V

SDA

P82B96

SU01708

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

V

V

CC1

CC1

+V CABLE DRIVE

SCL

I2C/DDC
MASTER

SDA

GND

V

CC

R

X

S

X

S

Y

T

X

R

Y

T

Y

470 kΩ

P82B96

470 kΩ

PC/TV RECEIVER/DECODER BOX

BC
847B

4K7

100 nF

BC
847B

R

G

B

+V CABLE DRIVE

100 kΩ

V

CC

R

3 – 20 m CABLES

I2C/DDC

X

T

X

R

Y

T

Y

S

X

S

Y

V

2

I

C/DDC

SLAVE

CC2

SCL

SDA

P82B96

GND

MONITOR/FLAT TV

VIDEO SIGNALS

su01785

Figure 4. Extending a DCC bus

Figure 4 shows how a master I2C-bus can be protected against
short circuits or failures in applications that involve plug/socket
connections and long cables that may become damaged. A simple
circuit is added to monitor the SDA bus and if its LOW time exceeds
the design value then the master bus is disconnected. P82B96 will
free all its I/Os if its supply is removed, so one option is to connect
its V

to the output of a logic gate from, say, the 74LVC family. The

CC

SDA and SCL lines could be timed and V

disabled via the gate if

CC

one or other lines exceeds a design value of ‘LOW’ period as in

Figure 28 of AN255

choice of V
can be used. If the SDA line is held LOW, the 100 nF capacitor will
charge and the R
exceeds V
practice means simply releasing it.

CC

In this example the SCL line is made uni-directional by tying the R
pin to VCC. The state of the buffered SCL line cannot affect the

. If the supply voltage of logic gates restricts the

supply then the low-cost discrete circuit in Figure 4

CC

input will be pulled towards VCC. When it

y

/2 the Ry input will set the Sy input HIGH, which in

x

master clock line which is allowed when clock-stretching is not
required. It is simple to add an additional transistor or diode to
control the R

input in the same way as Ry when necessary. The +V

x

cable drive can be any voltage up to 15 V and the bus may be run at
a lower impedance by selecting pull-up resistors for a static sink
current up to 30 mA. V
connected devices. Because DDC uses relatively low speeds
(<100 kHz), the cable length is not restricted to 20 m by the I

CC1

and V

may be chosen to suit the

CC2

2

C

signalling, but it may be limited by the video signalling.
Figure 5 shows that P82B96 can achieve high clock rates over long

cables. While calculating with lumped wiring capacitance yields
reasonable approximations to actual timing, even 25 meters of cable

is better treated using transmission line theory. Flat ribbon cables
connected as shown, with the bus signals on the outer edge, will
have a characteristic impedance in the range 100 – 200 Ω. For
simplicity they cannot be terminated in their characteristic
impedance but a practical compromise is to use the minimum
pull-up allowed for P82B96 and place half this termination at each
end of the cable. When each pull-up is below 330 Ω, the rising edge
waveforms have their first voltage ‘step’ level above the logic
threshold at Rx and cable timing calculations can be based on the
fast rise/fall times of resistive loading plus simple one-way
propagation delays. When the pull-up is larger, but below 750 Ω, the
threshold at Rx will be crossed after one signal reflection. So at the
sending end it is crossed after 2 times the one-way propagation
delay and at the receiving end after 3 times that propagation delay.
For flat cables with partial plastic dielectric insulation (by using outer
cores) the one-way propagation delays will be about 5 ns/meter.
The 10% to 90% rise and fall times on the cable will be between
20 ns and 50 ns, so their delay contributions are small. There will be
ringing on falling edges that can be damped, if required, using
Schottky diodes as shown.

When the Master SCL HIGH and LOW periods can be programmed
separately , e.g. using control registers I2SCLH and I2SCLL of
89LPC932, the timings can allow for bus delays. The LOW period
should be programmed to achieve the minimum 1300 ns plus the
net delay in the slave’s response data signal caused by bus and
buffer delays. The longest data delay is the sum of the delay of the
falling edge of SCL from master to slave and the delay of the rising
edge of SDA from slave data to master. Because the buffer will
‘stretch’ the programmed SCL LOW period, the actual SCL

2004 Mar 29

7

Philips Semiconductors Product data

V

V

R1

R2

P82B96Dual bi-directional bus buffer

frequency will be lower than calculated from the programmed clock
periods. In the example for 25 meters the clock is stretched 400 ns,
the falling edge of SCL is delayed 490 ns and the SDA rising edge is
delayed 570 ns. The required additional LOW period is
(490 + 570) = 1060 ns and the I

2

C-bus specifications already
include an allowance for a worst case bus risetime 0 to 70% of
425 ns. (The bus risetime can be 300 ns 30% to 70%, which means
it can be 425 ns 0–70%. The 25-meter cable delay times as quoted
already include all rise/fall times.) Therefore, the micro only needs to
be programmed with an addtional (1060 – 400 – 425) = 235 ns,
making a total programmed LOW period 1535 ns. The programmed
LOW will the be stretched by 400 ns to yield an actual bus LOW
time of 1935 ns, which, allowing the minimum HIGH period of
600 ns, yields a cycle period of 2535 ns or 394 kHz.

R

X

T

X

R

Y

+V CABLE DRIVE

R1R1

I2C

MASTER

V

CC1

R2

V

CC

SCL

R2

S

X

Note that in both the 100-meter and 250-meter examples the
capacitive loading on the I

2

C-buses at each end is within the

maximum allowed Standard mode loading of 400 pF, but exceeds

the Fast mode limit. This is an example of a ‘hybrid’ mode because it

relies on the response delays of Fast mode parts but uses
(allowable) Standard mode bus loadings with rise times that
contribute significantly to the system delays. The cables cause large
propagation delays so these systems need to operate well below the
400 kHz limit but illustrate how they can still exceed the 100 kHz
limit provided all parts are capable of Fast mode operation. The
fastest example illustrates how the 400 kHz limit can be exceeded
provided master and slave parts have delay specifications smaller
than the maximum allowed. Many Philips slaves have delays shorter
than 600 ns, but none have that guaranteed.

V

CC2

R2

V

R1R1

R

X

T

X

R

Y

CC

R2

S

SCL

X

I2C

SLAVE(S)

GND

SDA

C2 C2

S

Y

P82B96

T

Y

CABLE

PROPAGATION

DELAY ' 5 ns/m

BAT54A BAT54A

T

Y

P82B96

C2 C2

SDA

S

Y

GND

su01786

Figure 5. Driving ribbon or flat telephone cables

EXAMPLES OF BUS CAPABILITY (refer to Figure 5)

SET MASTER

+

CC1

+V

CABLE

+

CC2

C2 CABLE CABLE CABLE

(pF) LENGTH CAPACITANCE DELAY

5 V 12 V 5 V 750 2.2 k 400 250 m

5 V 12 V 5 V 750 2.2 k 220 100 m

Not applicable

(delay based)

Not applicable

(delay based)

1.25 µs 600 ns 4000 ns 120 kHz

500 ns 600 ns 2600 ns 185 kHz

NOMINAL SCL

HIGH

PERIOD

PERIOD

LOW

3.3 V 5 V 3.3 V 330 1 k 220 25 m 1 nF 125 ns 600 ns 1500 ns 390 kHz

3.3 V 5 V 3.3 V 330 1 k 100 3 m 120 pF 15 ns 600 ns 1000 ns 500 kHz 600 ns

EFFECTIVE

BUS
CLOCK
SPEED

MAXIMUM

SLAVE

RESPONSE

DELAY

Normal spec.

400 kHz

parts

Normal spec.

400 kHz

parts

Normal spec.

400 kHz

parts

2004 Mar 29

8

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

CALCULATING SYSTEM DELAYS AND BUS CLOCK FREQUENCY FOR A FAST MODE SYSTEM

LOCAL MASTER BUS BUFFERED EXPANSION BUS REMOTE SLAVE BUS

V

CCM

MASTER

2

I

SCL

C I2C

GND/0 V

A) FALLING EDGE OF SCL AT MASTER IS DELAYED BY THE BUFFERS AND BUS FALL TIMES

EFFECTIVE DELAY OF SCL AT SLAVE = 255 + 17 V

V

CCB

Rm Rb Rs

Sx Tx/Rx Tx/Rx Sx

P82B96 P82B96

Cm = MASTER BUS
CAPACITANCE

Cb = BUFFERED BUS
WIRING CAPACITANCE

+ (2.5 + 4 × 109 Cb) V

CCM

(ns) C = F, V = VOLTS

CCB

SCL

Cs = SLAVE BUS
CAPACITANCE

SLAVE

V

CCS

su01787

Figure 6.

LOCAL MASTER BUS BUFFERED EXPANSION BUS

V

CCM

MASTER

SCL

Rm

V

CCB

Rb

Sx Tx/Rx Tx/Rx

P82B96

2

I

C

Cm = MASTER BUS
CAPACITANCE

GND/0 V

B) RISING EDGE OF SCL AT MASTER IS DELAYED (CLOCK STRETCH) BY BUFFER AND BUS RISE TIMES

EFFECTIVE DELAY OF SCL AT MASTER = 270 + RmCm + 0.7RbCb (ns), C = F, R = Ω

Cb = BUFFERED BUS
WIRING CAPACITANCE

Figure 7.

su01788

2004 Mar 29

9

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

LOCAL MASTER BUS BUFFERED EXPANSION BUS REMOTE SLAVE BUS

V

CCM

MASTER

2

I

SDA

C I2C

GND/0 V

C) RISING EDGE OF SDA AT SLAVE IS DELAYED BY THE BUFFERS AND BUS RISE TIMES

EFFECTIVE DELAY OF SDA AT MASTER = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) (ns), C = F, R = Ω

V

CCB

Rm Rb Rs

Sx Tx/Rx Tx/Rx Sx

P82B96 P82B96

Cm = MASTER BUS
CAPACITANCE

Figures 6, 7, and 8 show the P82B96 used to drive extended bus
wiring, with relatively large capacitance, linking two Fast mode

2

I

C-bus nodes. It includes simplified expressions for making the
relevant timing calculations for 3.3/5 V operation. Because the
buffers and the wiring introduce timing delays, it may be necessary
to decrease the nominal SCL frequency below 400 kHz. In most
cases the actual bus frequency will be lower than the nominal
Master timing due to bit-wise stretching of the clock periods.

The delay factors involved in calculation of the allowed bus speed
are:

A) The propagation delay of the Master signal through the buffers

and wiring to the Slave. The important delay is that of the falling
edge of SCL because this edge ‘requests’ the data or
Acknowledge from a Slave.

B) The effective stretching of the nominal LOW period of SCL at the

Master caused by the buffer and bus rise times

C) The propagation delay of the Slave’s response signal through the

buffers and wiring back to the Master . The important delay is
that of a rising edge in the SDA signal. Rising edges are always
slower and are therefore delayed by a longer time than falling
edges. (The rising edges are limited by the passive pull-up while
falling edges are actively driven)

The timing requirement in any I

2

C system is that a Slave’s data
response (which is provided in response to a falling edge of SCL)
must be received at the Master before the end of the corresponding
low period of SCL as appears on the bus wiring at the Master. Since
all Slaves will, as a minimum, satisfy the worst case timing
requirements of a 400 kHz part, they must provide their response

within the minimum allowed clock LOW period of 1300 ns. Therefore

in systems that introduce additional delays it is only necessary to

Cb = BUFFERED BUS
WIRING CAPACITANCE

Figure 8.

extend that minimum clock low period by any “effective” delay of the
Slave’s response. The effective delay of the slaves response = total
delays in SCL falling edge from the Master reaching the Slave (A) –
the effective delay (stretch) of the SCL rising edge (B) + total delays
in the Slave’s response data, carried on SDA, reaching the
Master (C).

The Master microcontroller should be programmed to produce a
nominal SCL LOW period = (1300 + A – B + C) ns, and should be
programmed to produce the nominal minimum SCL HIGH period of
600 ns. Then a check should be made to ensure the cycle time is
not shorter than the minimum 2500 ns. If found necessary, just
increase either clock period.

Due to clock stretching, the SCL cycle time will always be longer
than (600 + 1300 + A + C) ns.

Example:
The Master bus has an RmCm product of 100 ns and V
The buffered bus has a capacitance of 1 nF and a pull-up resistor of

160 ohms to 5 V giving an RbCb product of 160 ns. The Slave bus
also has an RsCs product of 100 ns.

The microcontroller LOW period should be programmed to
≥ (1300 + 372.5 – 482 + 472) ns, that is ≥ 1662.5 ns.

Its HIGH period may be programmed to the minimum 600 ns.
The nominal microcontroller clock period will be

≥ (1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of
442 kHz.

The actual bus clock period, including the 482 ns clock stretch
effect, will be below (nominal + stretch) = (2262.5 + 482) ns or
≥ 2745 ns, equivalent to an allowable frequency of 364 kHz.

SDA

Cs = SLAVE BUS
CAPACITANCE

SLAVE

CCM

V

CCS

su01789

= 5 V.

2004 Mar 29

10

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

SCL

SDA

3.3–5 V

S

X

3.3–5 V

S

Y

ch1: freq = 624 kHz

P82B96

12 V

12 V

TWISTED-PAIR TELEPHONE WIRES,
USB, OR FLAT RIBBON CABLES.
UP TO 15 V LOGIC LEVELS,

T

X

R

X

12 V

T

Y

R

Y

P82B96 P82B96 P82B96 P82B96

SXS

NO LIMIT TO THE NUMBER OF CONNECTED BUS DEVICES.

SXS

Y

SCL/SDASCL/SDA

SXS

Y

Y

SCL/SDA

INCLUDE VCC AND GND.

3.3 V 3.3 V

S

Y

S

X

SDA
SCL

su01709

Figure 9. I2C multi-point applications

ch1: freq = 624 kHz

Tx

Sx

10 V

5 V

Rx

Sx

CH1!2.00V = AVG
CH2!2.00V = BWL MTB 200 ns – 0.98dvch1+

Horiz: 200 ns/div. VertL 2 V/div.

SU01069

Figure 10. Propagation Sx to Tx — Sx pull-up to 5V,

Tx pull-up to V

CC

= 10 V

0 V

CH1!2.00V = AVG
CH2!2.00V = BWL MTB 200 ns – 0.98dvch1+

Horiz: 200 ns/div. VertL 2 V/div.

SU01070

Figure 11. Propagation Rx to Sx — Sx pull-up to 5V,

Rx pull-up to V

CC

= 10 V

2004 Mar 29

11

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

2004 Mar 29

12

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1

2004 Mar 29

13

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

2004 Mar 29

14

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

REVISION HISTORY

Rev Date Description

_4 20040329 Product data (9397 750 12932). Supersedes data of 2003 Apr 02 (9397 750 11351).

Modifications:

•Page 2:

– Features section re-written.

– Add “TSSOP” to heading for pin configurations

•Page 3, Ordering information table: correct description of TSSOP8 package.

•Page 5, (continued) Characteristics table, Note 1,

– third sentence:

from “... the LOW from on S
to “... the LOW from one S

– fourth sentence:

from “In any design the S
to “In any design the S

•Figure 4: Change 2 transistors to bipolar type. Add dashed line between V

and VCC to indicate optional/allowed links.

•Figure 5: Add dashed line between V

links.

•Page 8, table “Examples of bus capability”:

– cable capacitance 1 nF:

change LOW period from “1600 ns” to “1500 ns”
change Effective bus clock speed from “380 kHz” to “390 kHz”

– change cable capacitance “120 nF” to “120 pF”

•Add title “Calculating system delays and bus clock frequency for a Fast mode system” on page 9.

•Add V

label to Figures 6, 7 and 8.

CCB

•Page 10, “Example:” paragraphs 3, 5 and 6: values corrected in equations.

•Add signal names to Figure 9.

•Add package outline drawing SOT505-1.

_3 20030402 Product data (9397 750 11351); ECN 853-2241 29602 dated 28 February 2003.

_2 20030226 Product data (9397 750 11093); ECN 853-2241 29410 of 22 January 2003;

_1 20010306 Product data (9397 750 08122); ECN 853-2241 25758 of 2001 Mar 06.

Supersedes data of 2003 Jan 22 (9397 750 11093)

supersedes data of 2001 Mar 06 (9397 750 08122)

output ...”

X

output ...”

X

pins of different ICs because the resulting ...”

X

pins of different ICs should never be linked because the resulting ...”

X

and VCC, and between V

CC1

and VCC, and between V

CC1

and VCC to indicate optional/allowed

CC2

CC2

2004 Mar 29

15

Philips Semiconductors Product data

P82B96Dual bi-directional bus buffer

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.

Data sheet status

Level

I

Data sheet status

Objective data

[1]

Product

[2] [3]

status

Development

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

II

III

[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Preliminary data

Product data

http://www.semiconductors.philips.com.

Qualification

Production

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see

the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be

expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com . Fax: [phone]

For sales offices addresses send e-mail to:
[e-mail].

Document order number: 9397 750 12932

 Koninklijke Philips Electronics N.V. 2004

All rights reserved. Printed in U.S.A.

Date of release: 03-04

Philips
Semiconductors

2004 Mar 29

16