Philips P80C562EBA-02, P80C562EFA-02, P80C562EHA-02 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

P83C562; P80C562

8-bit microcontroller

Product specification			1997 Apr 16
File under Integrated Circuits, IC20

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

CONTENTS

1FEATURES

2GENERAL DESCRIPTION

3ORDERING INFORMATION

4BLOCK DIAGRAM

5FUNCTIONAL DIAGRAM

6PINNING INFORMATION

6.1Pinning

6.2Pin description

7FUNCTIONAL DESCRIPTION

8MEMORY ORGANIZATION

8.1Program Memory

8.2Addressing

9I/O FACILITIES

10PULSE WIDTH MODULATED OUTPUTS

10.1Prescaler Frequency Control Register (PWMP)

10.2Pulse Width Register 0 (PWM0)

10.3Pulse Width Register 1 (PWM1)

11 ANALOG-TO-DIGITAL CONVERTER (ADC)

11.1Analog input pins

11.2ADC Control Register (ADCON)

12 TIMER/ COUNTERS

12.1Timer 0 and Timer 1

12.2Timer T2 Capture and Compare Logic

12.2.1T2 Control Register (TM2CON)

12.2.2Capture Control Register (CTCON)

12.2.3Interrupt Flag Register (TM2IR)

12.2.4Set Enable Register (STE)

12.2.5Reset/Toggle Enable register (RTE)

12.3Watchdog Timer (T3)

13SERIAL I/O

14INTERRUPT SYSTEM

14.1Interrupt Vectors

14.2Interrupt priority

14.3Interrupt Enable and Priority Registers

14.3.1Interrupt Enable Register 0 (IEN0)

14.3.2Interrupt Enable register 1 (IEN1)

14.3.3Interrupt priority register 0 (IP0)

14.3.4Interrupt Priority Register 1 (IP1)

15 REDUCED POWER MODES

15.1Idle and Power-down operation

15.1.1Idle mode

15.1.2Power-down mode

15.2 Power Control Register (PCON)

16OSCILLATOR CIRCUITRY

17RESET CIRCUITRY

17.1Power-on-reset

18INSTRUCTION SET

19LIMITING VALUES

20DC CHARACTERISTICS

21AC CHARACTERISTICS

22PACKAGE OUTLINES

23SOLDERING

23.1Introduction

23.2Reflow soldering

23.3Wave soldering

23.4Repairing soldered joints

24DEFINITIONS

25LIFE SUPPORT APPLICATIONS

1997 Apr 08

2

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

1 FEATURES

∙80C51 Central Processing Unit

∙8 kbytes ROM, expandable externally to 64 kbytes

∙256 bytes RAM, expandable externally to 64 kbytes

∙Two standard 16-bit timer/counters

∙An additional 16-bit timer/counter coupled to four capture registers and three compare registers

∙An 8-bit ADC with 8 multiplexed analog inputs

∙Two 8-bit resolution, Pulse Width Modulated outputs

∙Five 8-bit I/O ports plus one 8-bit input port shared with analog inputs

∙Full-duplex UART compatible with the standard 80C51

∙On-chip Watchdog Timer

∙Oscillator frequency: 3.5 to 16 MHz.

2 GENERAL DESCRIPTION

The P80C562/P83C562 (hereafter generally referred to as P8xC562) single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family.

The P8xC562 has the same instruction set as the 80C51. Two versions of the derivative exist:

∙With 8 kbytes mask-programmable ROM

∙ROMless version of the P8xC562.

3 ORDERING INFORMATION

This I/O intensive device provides architectural enhancements to function as a controller in the field of automotive electronics, specifically engine management and gear box control.

The P8xC562 contains a non-volatile 8 kbyte read only program memory, a volatile 256 byte read/write data memory, six 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), an additional 16-bit timer coupled to capture and compare latches, a fourteen-source, two-priority-level, nested interrupt structure, an 8-input ADC, a dual DAC with pulse width modulated outputs, a serial interface (UART), a Watchdog Timer and on-chip oscillator and timing circuits. For systems that require extra capability, the P8xC562 can be expanded using standard TTL compatible memories and logic.

The device also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 45 two-byte and

17 three-byte. With a 16 MHz crystal, 58% of the instructions are executed in 0.75 μs and 40% in 1.5 μs. Multiply and divide instructions require 3 μs.

	TYPE NUMBER		PACKAGE		FREQUENCY	TEMPERATURE
		NAME	DESCRIPTION	VERSION	RANGE (MHz)	RANGE (°C)
	P80CE562EHA(1)	PLCC68	plastic leaded chip carrier; 68 leads	SOT188-2	3.5 to 16	−40 to +125
	P80C562EBA(1)					0 to +70
	P80C562EFA(1)					−40 to +85
	P83C562EHA/nnn(2)					−40 to +125
	P83C562EBA/nnn(2)					0 to +70
	P83C562EFA/nnn(2)					−40 to +85

Notes

1.ROMless type.

2.ROM coded type; nnn denotes the ROM code number.

1997 Apr 08

3

Apr 1997

PWM1

ADC0 to ADC7

08

VDD

VSS

T0

T1

INT0

INT1

PWM0

AVSS

AVDD AVREF−

AVREF+ STADC

3

3

3

3

5

XTAL1

T0, T1

PROGRAM

DATA

XTAL2

TWO 16-BIT

MEMORY

MEMORY

DUAL

TIMER/

CPU

ADC

8 KBYTES

256 BYTES

PWM

EVENT

EA

COUNTERS

ROM

RAM

PCB

ALE

80C51

P8xC562

core

excluding

8 - bit

PSEN

ROM/RAM

internal bus

WR

3

4

16

RD

3

AD0 to AD7

FOUR

T2

THREE

T3

PARALLEL

16-BIT

COMPARA -

0

SERIAL

8-BIT

16-BIT

16

I/O PORTS

16-BIT

COMPARA -

TOR

WATCH -

&

UART

I/O

CAPTURE

TIMER/

TORS

OUTPUT

DOG

PORT

PORTS

EVENT

A8 to A15

EXT. BUS

LATCHES

WITH

SELECTION

TIMER

COUNTER

REGISTERS

2

		3	3			1		1	4
P0	P1 P2 P3	TXD	RXD	P5	P4	CT0I to CT3I	T2	RT2	CMSR0 to CMSR5	RST	EW
									CMT0, CMT1

1	alternative functions of port 1	3	alternative function of port 3	5	alternativefullpagewidth	function of port 5
						MBH348
0	alternative function of port 0	2	alternative function of port 2	4	alternative function of port 4
					handbook,

Fig.1 Block diagram.

DIAGRAM BLOCK 4

microcontroller bit-8

P80C562 P83C562;

Semiconductors Philips

specification Product

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562
5 FUNCTIONAL DIAGRAM

				alternative function
	XTAL1		0	AD0
	XTAL2		1	AD1
	EA		2	AD2	LOW ORDER
			3	AD3
					ADDRESS
	PSEN		4	PORT 0	AND
				AD4
	ALE		5	AD5	DATA BUS
			6	AD6
	PWM0		7	AD7
	PWM1		0	CT0I
	AVSS		1	CT1I
			2	CT2I
	AV DD		3	CT3I
	AVREF +		4	PORT 1
				T2
	AVREF −		5	RT2
alternative function			6
			7
	STADC
ADC0	0		0	A8
ADC1	1	P8xC562	1	A9
ADC2	2		2	A10	HIGH ORDER
ADC3	3		3	A11
					ADDRESS
ADC4	PORT 5		4	PORT 2
	4			A12	BUS
ADC5	5		5	A13
ADC6	6		6	A14
ADC7	7		7	A15
CMSR0	0		0	RXD/DATA
CMSR1	1		1	TXD/CLOCK
CMSR2	2		2	INT0
CMSR3	3		3	INT1
CMSR4	PORT 4		4	PORT 3
	4			T0
CMSR5	5		5	T1
CMT0	6		6	WR
CMT1	7		7	RD
	RST		VSS
	EW		VDD
		MBH347

Fig.2 Functional diagram.

1997 Apr 08

5

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

6 PINNING INFORMATION

6.1Pinning

						P4.2/CMSR2		P4.1/CMSR1		P4.0/CMSR0		EW		PWM1		PWM0		STADC		V		P5.0/ADC0		P5.1/ADC1		P5.2/ADC2		P5.3/ADC3		P5.4/ADC4		P5.5/ADC5		P5.6/ADC6		P5.7/ADC7		AV
																				DD																		DD
						9		8		7		6		5		4		3		2		1		68		67		66		65		64		63		62		61
P4.3/CMSR3			10																																					60		AVSS
P4.4/CMSR4			11																																					59		AVREF+
P4.5/CMSR5			12																																					58		AVREF−
P4.6/CMT0			13																																					57		P0.0/AD0
P4.7/CMT1			14																																					56		P0.1/AD1
	RST		15																																					55		P0.2/AD2
P1.0/CT0I			16																																					54		P0.3/AD3
P1.1/CT1I			17																																					53		P0.4/AD4
P1.2/CT2I			18																P8xC562																					52		P0.5/AD5
P1.3/CT3I			19																																					51		P0.6/AD6
P1.4/T2			20																																					50		P0.7/AD7
P1.5/RT2			21																																					49		EA
	P1.6		22																																					48		ALE
P1.7			23																																					47		PSEN
P3.0/RXD			24																																					46		P2.7/A15
P3.1/TXD			25																																					45		P2.6/A14
P3.2/INT0			26																																					44		P2.5/A13
			27					28		29		30		31		32		33	34			35		36		37		38		39		40		41		42		43

P3.3/INT1

P3.4/T0

P3.5/T1

P3.6/WR

P3.7/RD

n.c.

n.c.

XTAL2

XTAL1

V

V

n.c.

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

SS

SS

MBH349

Fig.3 Pinning configuration for PLCC68 (SOT188-2) package.

1997 Apr 08

6

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

6.2Pin description

Table 1 PLCC68 (SOT188-2)

To avoid latch-up at Power-on, the voltage at any pin at any time must lie within the range VDD + 0.5 V to VSS − 0.5 V.

SYMBOL

PIN

DESCRIPTION

VDD

2

Power supply, digital part (+5 V). Power supply pins during normal operation and

power reduction modes.

STADC

3

Start ADC operation: Input starting analog-to-digital conversion (ADC operation can

also be started by software). This pin must not float.

4

Pulse Width Modulation output 0.

PWM0

5

Pulse Width Modulation output 1.

PWM1

6

Enable Watchdog Timer: enable for Watchdog Timer and disable Power-down mode.

EW

This pin must not float.

P4.0/CMSR0

7 to 12

P4.0 to P4.5: 8-bit quasi-bidirectional I/O port lines;

to

CMSR0 to CMSR5: Compare and Set/Reset outputs for Timer T2.

P4.5/CMSR5

P4.6/CMT0

13

P4.6 to P4.7: 8-bit quasi-bidirectional I/O port lines;

CMT0 to CMT1: Compare and toggle outputs for Timer T2.

P4.7/CMT1

14

RST

15

Reset: Input to reset the P8x562; also generated when the Watchdog Timer overflows.

P1.0/CT0I

16 to 19

P1.0 to P1.3: 8-bit quasi-bidirectional I/O port lines;

to

CT0I to CT3I: Capture timer inputs for Timer 2.

P1.3/CT3I

P1.4/T2

20

P1.4: 8-bit quasi-bidirectional I/O port line;

T2: T2 event input (rising edge triggered).

P1.5/RT2

21

P1.5: 8-bit quasi-bidirectional I/O port line;

RT2: T2 timer reset input (rising edge triggered)

P1.6 to P1.7

22 to 23

P1.6 to P1.7: 8-bit quasi-bidirectional I/O port lines, open-drain.

P3.0/RXD

24

P3.0: 8-bit quasi-bidirectional I/O port line;

RXD: Serial input port.

P3.1/TXD

25

P3.1: 8-bit quasi-bidirectional I/O port line;

TXD: Serial output port.

26

P3.2: 8-bit quasi-bidirectional I/O port line;

P3.2/INT0

INT0:

External interrupt input 0.

27

P3.3: 8-bit quasi-bidirectional I/O port line;

P3.3/INT1

INT1:

External interrupt input 1.

P3.4/T0

28

P3.4: 8-bit quasi-bidirectional I/O port line;

T0: Timer 0 external input.

P3.5/T1

29

P3.5: 8-bit quasi-bidirectional I/O port line;

T1: Timer 1 external input.

30

P3.6: 8-bit quasi-bidirectional I/O port line;

P3.6/WR

WR:

External Data Memory Write strobe.

31

P3.7: 8-bit quasi-bidirectional I/O port line;

P3.7/RD

RD:

External Data Memory Read strobe.

n.c.

32, 33

Not connected.

XTAL2

34

Crystal Oscillator Output: output of the inverting amplifier that forms the oscillator.

Left open-circuit when an external oscillator clock is used.

1997 Apr 08

7

Philips Semiconductors

Product specification

8-bit microcontroller

P83C562; P80C562

SYMBOL

PIN

DESCRIPTION

XTAL1

35

Crystal Oscillator Input: input to the inverting amplifier that forms the oscillator, and

input to the internal clock generator. Receives the external oscillator clock signal when

an external oscillator is used.

VSS

36, 37

Digital ground pins.

n.c.

38

Not connected.

P2.0/A08

39 to 46

P2.0 to P2.7: 8-bit quasi-bidirectional I/O port lines;

to

A08 to A15: High-order address byte for external memory.

P2.7/A15

47

Program Store Enable: read strobe to the external program memory via Port 0 and 2.

PSEN

Is activated twice each machine cycle during fetches from external program memory.

When executing out of external program memory two activations of

PSEN

are skipped

during each access to external data memory.

PSEN

is not activated (remains HIGH)

during no fetches from external program memory.

PSEN

can sink/source 8 LSTTL

inputs and can drive CMOS inputs without external pull-ups.

ALE

48

Address Latch Enable: latches the low byte of the address during access of external

memory in normal operation. It is activated every six oscillator periods except during an

external data memory access. ALE can sink/source 8 LSTTL inputs and can drive

CMOS inputs without an external pull-up. To prohibit the toggling of the ALE pin (RFI

noise reduction) the RFI bit in the Power Control Register must be set by software.

49

External Access: if, during RESET,

is HIGH the CPU executes out of the internal

EA

EA

program memory provided the program Counter is less than 8192. If, during RESET,

EA

is LOW the CPU executes out of external program memory via Port 0 and Port 2.

EA

is not allowed to float.

EA

is latched during RESET and don’t care after RESET.

P0.7/AD7

50 to 57

P0.7 to P0.0: 8-bit open drain bidirectional I/O port lines;

to

AD7 to AD0: Multiplexed Low-order address and Data bus for external memory.

P0.0/AD0

AVREF-

58

Low-end of ADC (analog-to-digital conversion) reference resistor.

AVREF+

59

High-end of ADC (analog-to-digital conversion) reference resistor.

AVSS

60

Ground, analog part. For ADC receiver and reference voltage.

AVDD

61

Power supply, analog part (+5 V). For ADC receiver and reference voltage.

P5.7/ADC7

62 to 68,

P5.7 to P5.0: 8-bit input port lines;

to

1

ADC7 to ADC0: eight analog ADC inputs

P5.0/ADC0

1997 Apr 08

8

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

7 FUNCTIONAL DESCRIPTION

The P8xC562 is a stand-alone high-performance microcontroller designed for use in real-time applications such as instrumentation, industrial control and specific automotive control applications.

In addition to the 80C51 standard functions, the device provides a number of dedicated hardware functions for these applications.

The P8xC562 is a control-oriented CPU with on-chip program and data memory. It can be extended with external program memory up to 64 kbytes. It can also access up to 64 kbytes of external data memory.

For systems requiring extra capability, the P8xC562 can be expanded using standard memories and peripherals.

The P8xC562 has two software selectable modes of reduced activity for further power reduction − Idle and Power-down. The Idle mode freezes the CPU while allowing the RAM, timers, serial ports and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator causing all other chip functions to be inoperative.

8 MEMORY ORGANIZATION

The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 64 kbyte external data memory, 256 byte internal data memory and the

64 kbyte internal and external program memory.

The internal data memory is divided into 3 sections: the lower 128 bytes of RAM, the upper 128 bytes of RAM and the 128 byte Special Function Register memory

(see Fig.4). Figure 5 shows the Special Function Registers memory map. Internal RAM locations 0 to 127 are directly and indirectly addressable. Internal RAM locations 128 to 155 are only indirectly addressable. The Special Function Register locations 128 to 255 are only directly addressable.

The internal data RAM contains four register banks (each with eight registers), 128 addressable bits, a scratch pad area and the stack. The stack depth is limited by the available internal data RAM and its location is determined by the 8-bit Stack Pointer. All registers except the Program Counter and the four 8-register banks reside in the Special Function Register address space. These memory mapped registers include arithmetic registers, pointers, I/O ports, interrupt system registers, ADC and PWM registers, timers and serial port registers. There are

120 addressable bit locations in the SFR address space.

The P8xC562 contains 256 bytes of internal data RAM and 52 Special Function Registers. It provides a non-paged program memory address space to accommodate relocatable code. Conditional branches are performed relative to the Program Counter.

The register-indirect jump permits branching relative to a 16-bit base register with an offset provided by an 8-bit index register. 16-bit jumps and calls permit branching to any location in the contiguous 64 kbyte program memory address space.

8.1Program Memory

The program memory address space of the P83C562 consists of internal and external memory. The P83C562 has 8 kbytes of program memory on-chip. The program memory can be externally expanded up to 64 kbytes. If the EA pin is held HIGH, the P83C562 executes out of the internal program memory unless the address exceeds 1FFFH then locations 2000H through to 0FFFFH are fetched from the external program memory. If the EA pin is held LOW, the P83C562 fetches all instructions from the external memory. Figure 4 illustrates the program memory address space.

By setting a mask programmable security bit (i.e. user dependent) the ROM content is protected i.e. it cannot be read at any time by any test mode or by any instruction in the external program memory space. The MOVC instructions are the only ones which have access to program code in the internal or external program memory. The EA input is latched during reset and is ‘don’t care’ after reset. This implementation prevents from reading internal program code by switching from the external program memory to internal program memory during MOVC instruction or an instruction that handles immediate data. Table 2 lists the access to internal and external program memory by the MOVC instructions when the security bit has been set to a logic 1. If the security bit has been set to a logic 0 there are no restrictions for the MOVC instructions.

Table 2 Memory access by the MOVC instruction

	MOVC	PROGRAM MEMORY ACCESS
	INSTRUCTION	INTERNAL	EXTERNAL
	MOVC in internal	YES	YES
	program memory
	MOVC in external	NO	YES
	program memory

1997 Apr 08

9

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

8.2Addressing

The P8xC562 has five methods for addressing source operands:

∙Register

∙Direct

∙Register-Indirect

∙Immediate

∙Base-Register plus Index-Register-Indirect.

The first three methods can be used for addressing destination operands. Most instructions have a 'destination/source' field that specifies the data type, addressing methods and operands involved.

For operations other than MOVs, the destination operand is also a source operand.

Access to memory addressing is as follows:

∙Registers in one of the four 8-register banks through Register, Direct or Register-Indirect

∙256 bytes of internal data RAM through Direct or Register-Indirect. Bytes 0 to 127 may be addressed directly/indirectly. Bytes 128 to 155 share their address locations with the SFR registers and so may only be addressed indirectly as data RAM

∙Special Function Registers through Direct at address locations 128 to 255

∙External data memory through Register-Indirect

∙Program memory look-up tables through Base-Register plus Index-Register-Indirect.

The P8xC562 is classified as an 8-bit device since the internal ROM, RAM, Special Function Registers, Arithmetic Logic Unit and external data bus are all 8-bits wide. It performs operations on bit, nibble, byte and double-byte data types.

Facilities are available for byte transfer, logic and integer arithmetic operations. Data transfer, logic and conditional branch operations can be performed directly on Boolean variables to provide excellent bit handling.

64K

EXTERNAL	64K

8192

8191

8191

OVERLAPPED SPACE

INTERNAL

EXTERNAL

255

SPECIAL

INDIRECT ONLY

FUNCTION

(EA = 1)

(EA = 0)

REGISTERS

127

DIRECT AND

INDIRECT

0

0

0

0

INTERNAL DATA MEMORY

EXTERNAL

PROGRAM MEMORY

MBC745

DATA MEMORY

Fig.4 Memory map.

1997 Apr 08

10

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

			DIRECT
REGISTER			BYTE
MNEMONIC	BIT ADDRESS	ADDRESS (HEX)
T3			FFH
PWMP			FEH
PWM1			FDH
PWM0			FCH

										F8H
IP1	FF	FE		FD	FC	FB	FA	F9	F8
B										F0H
	F7	F6		F5	F4	F3	F2	F1	F0
RTE										EFH
STE										EEH
# TMH2										EDH
# TML2										ECH
CTCON										EBH
TM2CON										EAH
IEN1	EF	EE		ED	EC	EB	EA	E9	E8	E8H
ACC	E7	E6		E5	E4	E3	E2	E1	E0	E0H
										DBH
			Reserved for I2C-bus							DAH
										D9H
										D8H
										D0H
PSW	D7	D6		D5	D4	D3	D2	D1	D0
# CTH3										CFH
# CTH2										CEH
# CTH1										CDH
# CTH0										CCH
CMH2										CBH
CMH1										CAH
CMH0										C9H
TM2IR	CF	CE		CD	CC	CB	CA	C9	C8	C8H
# ADCH										C6H
ADCON										C5H
# P5										C4H

SFRs containing directly addressable bits

P4 C7 C6 C5 C4 C3 C2 C1 C0 C0H

MBH346

# denotes read-only registers

Fig.5 Special Function Register memory map.

1997 Apr 08

11

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

				DIRECT
	handbook, full pagewidth	REGISTER		BYTE
		MNEMONIC	BIT ADDRESS	ADDRESS (HEX)

IP0									B8H
	BF	BE	BD	BC	BB	BA	B9	B8
P3									B0H
	B7	B6	B5	B4	B3	B2	B1	B0
# CTL3									AFH
# CTL2									AEH
# CTL1									ADH
# CTL0									ACH
CML2									ABH
CML1									AAH
CML0									A9H
IEN0
	AF	AE	AD	AC	AB	AA	A9	A8	A8H
P2	A7	A6	A5	A4	A3	A2	A1	A0	A0H		SFRs containing
S0BUF									99H		directly addressable
											bits
S0CON	9F	9E	9D	9C	9B	9A	99	98	98H
P1	97	96	95	94	93	92	91	90	90H
TH1									8DH
TH0									8CH
TL1									8BH
TL0									8AH
TMOD									89H
									88H
TCON	8F	8E	8D	8C	8B	8A	89	88
PCON									87H
DPH									83H
DPL									82H
SP									81H
P0	87	86	85	84	83	82	81	80	80H
# denotes read-only registers									MGA151

Fig.6 Special Function Register memory map (continued).

1997 Apr 08

12

Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

9 I/O FACILITIES

The P8xC562 has six 8-bit ports. Ports 0 to 3 are the same as in the 80C51, with the exception of the additional functions of Port 1. The parallel I/O function of Port 4 is equal to that of Ports 1, 2 and 3. Port 5 has a parallel input port function, but has no function as an output port.

Ports 0 to 5 perform the following alternative functions:

Port 0 Provides the multiplexed low-order address and data bus used for expanding the P8xC562 with standard memories and peripherals.

Port 1 is used for a number of special functions:

∙4 capture inputs (or external interrupt request inputs if capture information is not utilized)

∙External counter input

∙External counter reset input.

Port 2 Provides the high-order address bus when expanding the P8xC562 with external program memory and/or external data memory.

Port 3 Pins can be configured individually to provide:

∙External interrupt request inputs

∙Counter inputs

∙Serial port receiver input and transmitter output

Port 4 Can be configured to provide signals indicating a match between timer counter T2 and its compare registers.

Port 5 May be used in conjunction with the ADC interface. Unused analog inputs can be used as digital inputs. As Port 5 lines may be used as inputs to the ADC, these digital inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines when driven by analog signals. Channel-to-channel crosstalk should be taken into consideration when both digital and analog signals are simultaneously input to Port 5 (see Chapter 20).

All ports are bidirectional with the exception of Port 5 which is an input port. Alternative function bits which are not used may be used as normal bidirectional I/O pins.

The generation or use of a Port 1, Port 3 or Port 4 pin as an alternative function is carried out automatically by the P8xC562 provided the associated Special Function Register bit is set HIGH.

In addition to the standard 8-bit ports, the I/O facilities of the P8xC562 also include a number of special I/O lines.

∙Control signals to READ and WRITE external data memory.

	strong pull-up	+5 V
	2 oscillator
	periods	p2
	p1	p3
		I/O PIN
		PORT
Q
from port latch	n
		I1
input data
	INPUT	MLA513
read port pin	BUFFER

Fig.7 I/O buffers in the P8xC562 (Ports 2, 3, 4 and P1.0 to P1.5).

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Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

10 PULSE WIDTH MODULATED OUTPUTS

Two pulse width modulated output channels are provided with the P8xC562. These channels output pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP which generates the clock for the counter. Both the prescaler and counter are common to both PWM channels. The 8-bit counter counts modulo 255 i.e. from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two registers: PWM0 and PWM1.

Provided the contents of either of these registers is greater than the counter value, the output of PWM0 or PWM1 is set LOW. If the contents of these registers are equal to, or less than the counter value, the output will be HIGH.

The pulse width ratio is therefore defined by the contents of the registers PWM0 and PWM1.

The pulse width ratio is in the range of 0 to 255/255 and may be programmed in increments of 1/255.

The repetition frequency fPWM, at the PWMn outputs is

fOSC

given by: f = ------------------------------------------------------------

PWM 2 × ( 1 + PWMP) × 255

When using an oscillator frequency of 16 MHz for example, the above formula would give a repetition frequency range of 123 Hz to 31.4 kHz.

By loading the PWM registers with either 00H or FFH, the PWM outputs can be retained at a constant HIGH or LOW level respectively. When loading FFH to the PWM registers, the 8-bit counter will never actually reach this value. Both PWMn output pins are driven by push-pull drivers, and are not shared with any other function.

handbook, full pagewidth
			PMW0
I				OUTPUT
N			8-BIT COMPARATOR		PWM0
				BUFFER
T
	f osc
E
R
N
A	1/2	PRESCALER	8-BIT COUNTER
L
B
U		PWMP
S
			8-BIT	OUTPUT	PWM1
			COMPARATOR	BUFFER
			PWM1
					MBC746

Fig.8 Functional diagram of Pulse Width Modulated outputs.

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Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

10.1Prescaler Frequency Control Register (PWMP)

Table 3	Prescaler Frequency Control Register (SFR address FEH)
7		6	5	4	3		2	1	0
PWMP.7		PWMP.6	PWMP.5	PWMP.4	PWMP.3		PWMP.2	PWMP.1	PWMP.0
Table 4	Description of PWMP bits
BIT		SYMBOL			DESCRIPTION
7		PWMP.7	Prescaler division factor.
to		to	The prescaler division factor = (PWMP) + 1.
0		PWMP.0

10.2Pulse Width Register 0 (PWM0)

Table 5 Pulse Width Register 0 (SFR address FCH)

7	6	5	4			3		2	1	0
PWM0.7	PWM0.6	PWM0.5	PWM0.4			PWM0.3		PWM0.2	PWM0.1	PWM0.0
Table 6 Description of PWM0 bits
BIT	SYMBOL					DESCRIPTION
7	PWM0.7	Pulse width ratio.					( PWMn)
to	to
0	PWM0.0	LOW/HIGH ratio of PWMn signals = 255 –( PWMn)-----------------------------------------

10.3Pulse Width Register 1 (PWM1)

Table 7 Pulse Width Register 1 (SFR address FDH)

7	6	5	4			3		2	1	0
PWM1.7	PWM1.6	PWM1.5	PWM1.4			PWM1.3		PWM1.2	PWM1.1	PWM1.0
Table 8 Description of PWM1 bits
BIT	SYMBOL					DESCRIPTION
7	PWM1.7	Pulse width ratio.					( PWMn)
to	to
0	PWM1.0	LOW/HIGH ratio of PWMn signals = 255 –( PWMn)-----------------------------------------

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Philips Semiconductors	Product specification
8-bit microcontroller	P83C562; P80C562

11 ANALOG-TO-DIGITAL CONVERTER (ADC)

The completion of the 8-bit ADC conversion is flagged by ADCI in the ADCON register and the result is stored in Special Function Register ADCH.

An ADC conversion in progress is unaffected by an external or software ADC start. The result of a completed conversion remains unaffected provided ADCI = 1. While ADCS = 1 or ADCI = 1, a new ADC start will be blocked and consequently lost.

An ADC conversion already in progress is aborted when the Idle or Power-down mode is entered. The result of a completed conversion (ADCI = 1) remains unaffected when entering the Idle mode.

If ADCI is cleared by software and ADCS is set at the same time, a new analog-to-digital conversion with the same channel number, may be started. However, it is recommended to reset ADCI before ADCS is set.

11.1Analog input pins

The analog input circuitry consists of an 8-input analog multiplexer and an ADC with 8-bit resolution. The analog reference voltage and analog power supplies are connected via separate input pins. The conversion takes 24 machine cycles i.e. 18 μs at an oscillator frequency of 16 MHz.

The ADC is controlled using the ADC Control Register (ADCON). Input channels are selected by the analog multiplexer, using bits AADR.0 to AADR.2 in ADCON.

ADC0

STADC

ADC1

analog reference

ADC2

ADC3

ANALOG INPUT

8-BIT ADC

ADC4

MULTIPLEXER

supply (analog part)

ADC5

ADC6

ground (analog part)

ADC7

ADCON	0	1	2	3	4	5	6	7		0	1	2	3	4	5	6	7	ADCH

INTERNAL BUS	MBH350

Fig.9 Functional diagram of analog input.

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