Philips oq2541hp DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

OQ2541HP; OQ2541U

SDH/SONET data and clock
recovery unit STM1/4/16
OC3/12/48 GE

Product specification
Supersedes data of 1999 Mar 19
File under Integrated Circuits, IC19

1999 May 27

Philips Semiconductors Product specification

SDH/SONET data and clock recovery unit

OQ2541HP; OQ2541U

STM1/4/16 OC3/12/48 GE

FEATURES

• Data and clock recovery up to 2.5 Gbits/s

• Multirate configurable (155, 622, 1250 or 2500 Mbits/s)

• Differential data input with 2.5 mV (p-p) typical

sensitivity

• Differential Current-Mode Logic (CML) data and clock
outputs with 50 Ω driving capability

• Adjustable CML output level

• Loop mode for system testing

• Bit error rate related loss of signal detection

• Few external components needed

• Single supply voltage

• Power dissipation 350 mW (typical value)

• LQFP48 plastic package.

ORDERING INFORMATION

TYPE

NUMBER

OQ2541HP LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
OQ2541U − bare die; 2360 × 2360 × 380 µm −

NAME DESCRIPTION VERSION

APPLICATIONS

• Data and clock recovery in STM1/OC3, STM4/OC12
and STM16/OC48 transmission systems

• Data and clock recovery in Gigabit Ethernet (GE)
transmission systems.

DESCRIPTION

The OQ2541 is a data and clock recovery IC intended for
use in Synchronous Digital Hierarchy (SDH) and
Synchronous Optical Network (SONET) systems.
The circuit recovers data and extracts the clock signal
from an incoming bitstream up to 2.5 Gbits/s. It can be
configured for use in STM1/OC3, STM4/OC12,
STM16/OC48 and Gigabit Ethernet systems.

PACKAGE

1999 May 27 2

Philips Semiconductors Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

BLOCK DIAGRAM

handbook, full pagewidth

DIN

DINQ

33

34

LOS

39

ALEXANDER

PHASE

DETECTOR

enable

DOUT622

DOUT1250

27

FREQUENCY

DIVIDER 1

DOUT155

28

1/2/4/16

OQ2541

OQ2541HP; OQ2541U

AREF

ENL

30

CLOCK

OUTPUT

48

DATA
AND

1

42

DOUT

43

DOUTQ

45

COUT

46

COUTQ

6

DLOOP

7

DLOOPQ

3

CLOOP

4

CLOOPQ

CREF

CREFQ

i.c.

21
22

5

13, 18, 19,
36, 40

2, 5, 8, 10, 11, 14, 17,

17

20, 23, 26, 29, 32, 35,
38, 41, 44, 47

GND

FREQUENCY

WINDOW

DETECTOR

(1000 ppm)

+

∫ dt

FREQUENCY

DIVIDER 2

64/128

12 24 25

9

DREF19LOCK

CAPDOQDREF39

CAPUPQ

proportional

path

integrating

path

130 pF130 pF

1516

VCRO

2.5 GHz

POWER

CONTROL

V

EE1

V

EE2

31

37

MBH972

PC

Fig.1 Block diagram.

1999 May 27 3

Philips Semiconductors Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

PINNING

SYMBOL PIN DESCRIPTION

ENL 1 loop mode enable input (active LOW)
GND 2 ground; note 1
CLOOP 3 clock output in loop mode (differential)
CLOOPQ 4 inverted clock output in loop mode (differential)
GND 5 ground; note 1
DLOOP 6 data output in loop mode (differential)
DLOOPQ 7 inverted data output in loop mode (differential)
GND 8 ground; note 1
DREF19 9 reference frequency select input 1 (see Table 2)
GND 10 ground; note 1
GND 11 ground; note 1
LOCK 12 phase lock detection output
i.c. 13 internally connected; note 2
GND 14 ground; note 1
CAPUPQ 15 external loop filter capacitor connection
CAPDOQ 16 external loop filter capacitor return connection
GND 17 ground; note 1
i.c. 18 internally connected; note 2
i.c. 19 internally connected; note 2
GND 20 ground; note 1
CREF 21 reference clock input (differential)
CREFQ 22 inverting reference clock input (differential)
GND 23 ground; note 1
DREF39 24 reference frequency select input 2 (see Table 2)
V

EE1

GND 26 ground; note 1
DOUT1250 27 STM mode select input 1 (see Table 3)
DOUT622 28 STM mode select input 2 (see Table 3)
GND 29 ground; note 1
DOUT155 30 STM mode select input 3 (see Table 3)
V

EE2

GND 32 ground; note 1
DIN 33 data input (differential)
DINQ 34 inverting data input (differential)
GND 35 ground; note 1
i.c. 36 internally connected; note 2
PC 37 control output for negative power supply
GND 38 ground; note 1
LOS 39 loss of signal detection output
i.c. 40 internally connected; note 2

25 negative supply voltage (−3.3 V); note 3

31 negative supply voltage (−3.3 V); note 3

OQ2541HP; OQ2541U

1999 May 27 4

Philips Semiconductors Product specification

SDH/SONET data and clock recovery unit

OQ2541HP; OQ2541U

STM1/4/16 OC3/12/48 GE

SYMBOL PIN DESCRIPTION

GND 41 ground; note 1
DOUT 42 data output in normal mode (differential)
DOUTQ 43 inverted data output in normal mode (differential)
GND 44 ground; note 1
COUT 45 clock output in normal mode (differential)
COUTQ 46 inverted clock output in normal mode (differential)
GND 47 ground; note 1
AREF 48 reference voltage input for controlling voltage swing on data and clock outputs

Notes

1. ALL GND pins or pads must be bonded; do not leave one single GND pin or pad unconnected.

2. ALL pins or pads denoted ‘i.c.’ should not be connected. Connections to these pins or pads degrade device
performance.

3. ALL VEE pins or pads must be bonded; do not leave one single VEE pin or pad unconnected.

handbook, full pagewidth

ENL

GND

CLOOP

CLOOPQ

GND

DLOOP

DLOOPQ

GND

DREF19

GND
GND

LOCK

COUTQ

GND

COUT

46

45

15

16

CAPUPQ

CAPDOQ

GND
44

OQ2541HP

17

GND

AREF

GND

48

47

1
2
3
4
5
6
7
8

9
10
11
12

13

14

i.c.

DOUT

DOUTQ
43

42

18

19

i.c.

i.c.

GND
41

20

GND

i.c.
40

21

CREF

GND

LOS
39

38

22

23

GND

CREFQ

PC

24 37

DREF39

36
35
34
33
32
31
30
29
28
27
26
25

MBH971

i.c.
GND
DINQ
DIN
GND

V

EE2
DOUT155
GND
DOUT622
DOUT1250
GND
V

EE1

Fig.2 Pin configuration.

1999 May 27 5

Philips Semiconductors Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

FUNCTIONAL DESCRIPTION

The OQ2541 recovers data and clock signals from an
incoming high speed bitstream. The input signal on
pins DIN and DINQ is buffered and amplified by the input
circuitry (see Fig.1). The signal is then fed to the Alexander
phase detector where the phase of the incoming data
signal is compared with that of the internal clock. If the
signals are out of phase, the phase detector generates
correction pulses (up or down) that shift the phase of the
Voltage Controlled Ring Oscillator (VCRO) output in
discrete amounts (∆ϕ) until the clock and data signals are
in phase. The technique used is based on principles first
proposed by J.D.H. Alexander, hence the name of the
phase detector.

Data sampling

The eye pattern of the incoming data is sampled at three
instants A, T and B (see Fig.3). When clock and data
signals are synchronized (locked):

• A is the centre of the data bit

• T is in the vicinity of the next transition

• B is in the centre of the bit following the transition.

If the same level is recorded at both A and B, a transition
has not occurred and no action is taken regardless of the
level T. However, if levels A and B are different a transition
has occurred and the phase detector uses level T to
determine whether the clock was too early or too late with
respect to the data transition.

If levels A and T are the same, but different from level B,
the clock was too early and needs to be slowed down a
little. The Alexander phase detector then generates a
down pulse which stretches a single output pulse from the
ring oscillator by approximately 0.25% which is 1 ps of the
400 ps bit period in the STM16/OC48 mode. This forces
the VCRO to run at a slightly lower frequency for one bit
period. The phase of the clock signal is thus shifted
fractionally with respect to the data signal.

handbook, halfpage

DATADATA

OQ2541HP; OQ2541U

If, on the other hand, levels B and T are the same but
different from level A, the clock was too late and needs to
be speeded up for synchronization. The phase detector
generates an up pulse forcing the VCRO to run at a slightly
higher frequency (+0.25%) for one bit period. The phase of
the clock signal is shifted with respect to the data signal (as
above, but in the opposite direction). Only the proportional
path is active while these phase adjustments are being
made. Because the instantaneous frequency of the VCRO
can be changed only in one of two discrete steps
(±0.25%), this type of loop is also known as a Bang/Bang
Phase-Locked Loop (PLL).

If not only the phase but also the frequency of the VCRO
is incorrect, a long train of up or down pulses will be
generated. This pulse train is integrated to generate a
control voltage that is used to shift the centre frequency of
the VCRO. Once the correct frequency has been
established, only the phase will need to be adjusted for
synchronization. The proportional path adjusts the phase
of the clock signal, whereas the integrating path adjusts
the centre frequency.

Frequency window detector

The frequency window detector checks the VCRO
frequency which must be within a 1000 ppm (parts per
million) window around the required frequency.

It compares the output of frequency divider 2 with the
reference frequency on pins CREF and CREFQ
(19.44 or 38.88 MHz; see Table 2). If the VCRO frequency
is found to be outside this window, the frequency window
detector disables the Alexander phase detector and forces
the VCRO output to a frequency within the window.
The phase detector then starts acquiring lock again.
Because of the loose coupling of 1000 ppm, the reference
frequency does not need to be highly accurate or stable.
Any crystal based oscillator that generates a reasonably
accurate frequency (e.g. 100 ppm) will do.

Since sampling point A is always in the centre of the eye
pattern when the data and clock signals are in phase
(locked), the values recorded at this point are taken as the
retrieved data. The data and clock signals are available at
the CML output buffers, which are capable of driving a
50 Ω load.

ATB

CLOCK

MGK143

Fig.3 Data sampling.

1999 May 27 6

RF data and clock input circuit

The schematic of the input circuit is shown in Fig.4.

RF data and clock output circuit

The schematic of the output circuit is shown in Fig.5.

Philips Semiconductors Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

handbook, halfpage

50 Ω50 Ω

MGL669

DINQ,
CREFQ

DIN,

CREF

VEE

OQ2541HP; OQ2541U

100 Ω100 Ω

DOUTQ, COUTQ
DOUT, COUT

V

AREF

V

EE

MGL670

Fig.4 RF data and clock input circuit.

Power supply and power control loop

The OQ2541 contains an on-board voltage regulator.
An external power transistor is needed to deliver the
supply to this circuit. The required external circuit is
straightforward, and can be built using a few components.
A suitable circuit with a power supply of−4.5 V is illustrated
in Fig.6.

A different configuration could be used, as long as the
power supply rejection ratio is greater than 60 dB for all
frequencies. The inductor is a RF choke with an
impedance greater than 50 Ω at frequencies higher than
2 MHz. Any transistor with a β > 100 and enough current
sink capability can be used.

The OQ2541 can also be used with a power supply of

−5.0 or −5.2 V. The only adaptation to be made to the
power control circuit is to change the emitter resistor R1
(see Table 1).

Table 1 Value of resistor R1.

POWER SUPPLY RESISTOR R1

−4.5 V 2.0 Ω

−5.0 V 6.8 Ω

−5.2 V 8.2 Ω

Fig.5 RF data and clock output circuit.

Output amplitude reference

The voltage swing at the CML compatible output stages
(pins DOUT, DOUTQ, COUT, COUTQ, DLOOP,
DLOOPQ, CLOOP and CLOOPQ) can be controlled by
adjusting the voltage on pin AREF (see Fig.7). An internal
voltage divider of 500 Ω and 16 kΩ connected between
ground and VEE initially fixes this level.

In most applications the outputs will be DC-coupled to a
load of 50 Ω. The output level regulation circuit will
maintain a 200 mV (p-p) single-ended swing across this
load. The voltage on pin AREF is half the single-ended
peak-to-peak value of the output signal (−100 mV).
No adjustments are necessary with DC-coupling.

If the outputs are AC-coupled, the voltage on pin AREF is
half the single-ended peak-to-peak value of the output

R

+

signal multiplied by a factor

where R

is the external load and Ro is the output

L

LRo

-------------------­R

L

impedance of the OQ2541 (100 Ω).

1999 May 27 7

Philips Semiconductors Product specification



SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

handbook, full pagewidth

2 Ω

100 nF

1 kΩ

BAND GAP
REFERENCE

V

EE

β > 100

R1
2 Ω

1
kΩ

PC

3.3
nF

GND

1 µF

OQ2541HP; OQ2541U

on chip

off chip

(1)

L1

−4.5 V

MGL732

(1) L1 = RF choke type Murata BLM21 or equivalent.

Fig.6 Schematic diagram of OQ2541 power control loop.

handbook, halfpage

500 Ω

16 kΩ R

GND

AREF

V

EE

off chipon chip

V

AREF

AREF

MGL667

If the outputs are AC-coupled, the formulae for calculating
the required voltage on pin AREF and the value of the
resistor connected between pins AREF and VEE as
follows:

RLRo+

V

AREF

-------------------­R

L

×–=

swing

(1)

0.5V

and:

V

EE



R1

×

---------------- -

R

AREF

=

----------------------------------------------------------------

–

1

V







R1





×

------- ­R2





where R1 = 500 Ω, R2 = 16 kΩ and V

AREF

V

EE

---------------- ­V

AREF

1–

(2)

1–

= −3.3 V.

EE

To maintain a single-ended swing of 200 mV (p-p) across
a 50 Ω AC-coupled load, the voltage on pin AREF must be

100 mV–

50 + 100()Ω

× 300 mV–=

-----------------------------------

50 Ω

Fig.7 Functionality of pin AREF.

1999 May 27 8

This can be achieved by connecting a 7.3 kΩ resistor
between pins AREF and V

EE

.

Philips Semiconductors Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

External capacitor for loop filter

The loop filter is an integrator with a built-in capacitance of
2 × 130 pF. An external capacitance of 200 nF must be
connected between pins CAPUPQ and CAPDOQ to
ensure loop stability while the frequency window detector
is active.

Loop mode enable

The loop mode is provided for system testing (see Fig.8).
The loop mode is enabled by applying a voltage lower than

0.8 V (TTL LOW-level) to pin
mode: the outputs on pins DLOOP, DLOOPQ, CLOOP
and CLOOPQ are switched on.

If a voltage higher than 2.0 V (TTL HIGH-level) is applied
to pin ENL, then pins DOUT, DOUTQ, COUT and COUTQ
are switched on while pins DLOOP, DLOOPQ, CLOOP
and CLOOPQ are disabled to minimize power
consumption.

If pin ENL is connected to VEE(−3.3 V), all outputs are
enabled.

handbook, halfpage

off chip on chip

ENL

GND

V

EE

Fig.8 Input circuit of pin ENL.

ENL. This selects the loop

36 kΩ

DECODER

LOGIC

MGL668

OQ2541HP; OQ2541U

Pin LOCK is an open-collector TTL output and should be
pulled up with a 10 kΩ resistor to a positive supply voltage.
If the VCO frequency is within a 1000 ppm window around
the desired frequency, pin LOCK will remain at a
HIGH-level. If no reference clock is present, or the VCO is
outside the 1000 ppm window, pin LOCK will be at a
LOW-level. The logic level on pin LOCK does not indicate
locking of the PLL to the incoming data; this is indicated by
the signal on pin LOS.

Loss of signal detection

The Loss Of Signal (LOS) function is closely related to the
functionality of the Alexander phase detector; see Fig.3 for
the meaning of A, B and T in this section.

In the functional description it is described that the phase
detector does not take any action if the value at sample
points A and B are the same, because there has not been
any transition. However, if levels A and B are the same but
different from level T, this still means there has not been
any transition, but level T has got the wrong level
somehow. This is probably due to noise or bad signal
integrity, which will lead to a bit error. Hence the
occurrence of this particular situation is an indication for bit
errors. If too many of these bit errors occur per time and
the PLL is gradually losing lock, the LOS alarm is asserted.
The LOS alarm assert level is around a Bit Error Rate
(BER) for BER = 5 ⋅ 10
BER = 1 ⋅ 10−3.

The LOS function will only work properly if the input signal
is larger than the input offset of the OQ2541; otherwise,
the signal will be masked by the input offset and
interpreted as consecutive bits of the same sign, thus
obstructing a proper LOS detection. In practice an optical
front-end device with a noise level (RMS value) larger than
the specified offset of the OQ2541 will ensure a proper
LOS indication.

The LOS detection is BER related, but neither dependent
on the data stream content, nor protocol. Therefore, an
SDH/SONET data stream is no prerequisite for a proper
LOS function. Since the LOS function of the OQ2541 is
derived from digital signals, it is a good supplement to an
analog, amplitude based, LOS indication.

−2

and the de-assert level is around

Lock detection

Pin LOCK should be interpreted as an indication for the
presence of the reference clock on pin CREF and for
properly functioning of the acquisition aid (frequency
window detector).

1999 May 27 9

Pin LOS is an open-collector TTL compatible output.
A pull-up resistor should be connected to a positive supply
voltage.

Pin LOS will be at a HIGH-level (TTL) if the data signal is
absent on pins DIN and DINQ or if BER > 5 ⋅ 10−2;
otherwise pin LOS will be at a LOW-level if BER < 1 ⋅ 10−3.

Philips Semiconductors Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

Reference frequency select

A reference clock signal of 19.44 or 38.88 MHz must be
connected to pins CREF and CREFQ. It should be noted
that the reference frequency should be either

39.0625 MHz or 19.53125 MHz in a Gigabit Ethernet
system. Pins DREF19 and DREF39 are used to select the
appropriate output frequency at frequency divider 2
(see Table 2).

To minimize the adverse influence of reference clock
crosstalk, a differential signal with an amplitude from
75 to 150 mV (p-p) is advised.

Since the reference clock is only used as an acquisition aid
for the PLL of the frequency window detector, the quality
of the reference clock (i.e. phase noise) is not important.
There is no phase noise specification imposed on the
reference clock generator and even frequency stability
may be in the order of 100 ppm. In general, most
inexpensive crystal based oscillators are suitable.

When the OQ2541 is used in an application with a fixed
reference clock frequency, it is best to connect the planes
of pins DREF19 and DREF39 with a short trace or a via to
the plane of pin GND or pin V
clock frequency is required in the application, the pins can
be controlled through low ohmic switching FETs,
e.g. BSH103 or equivalent (low R

Table 2 Reference frequency selection

FREQUENC

Y (MHz)

DIVISION

FACTOR

38.88 64 ground V

19.44 128 V

. If a selectable reference

EE

).

DSon

LEVEL ON PIN

DREF19 DREF39

EE

EE

V

EE

OQ2541HP; OQ2541U

Due to the nature of the PLL, the very wide tuning range is
a necessity for proper lock behaviour over the guaranteed
temperature range, aging and batch to batch spread.

Though it might seem that the OQ2541 is capable of
recovering other bit rates than SDH/SONET and Gigabit
Ethernet rates (STM1/OC3, STM4/OC12, STM16/OC48
and 1250 Mbits/s), the behaviour can not be guaranteed.

The required SDH/SONET bit rate is selected by
connecting pins DOUT155, DOUT622 and DOUT1250
to ground or to the supply voltage VEE (see Table 3):

• For STM16/OC48 (2488.32 Mbits/s) operation:
all three pins must be connected to ground

• For Gigabit Ethernet (1250 Mbits/s) operation:
pin DOUT1250 must be connected to V

• For STM4/OC12 (622.08 Mbits/s) operation:
pins DOUT1250 and DOUT622 must be connected to
VEE (the dividers are daisy chained)

• For STM1/OC3 (155,52 Mbits/s) operation:
all three pins must be connected to VEE.

The connections to VEE and ground carry a current of a few
milliamperes and should have low resistance and
inductance, so short printed-circuit board tracks are
recommended. In some cases a decoupling capacitor near
the selection pins can be necessary to provide a clean
return path for RF signals.

When the OQ2541 is used in an application with a fixed
data rate, it is best to connect the planes of
pins DOUT155, DOUT622 and DOUT1250 with a short
trace or a via to the plane of pin GND or pin VEE. If a
selectable reference clock frequency is required in the
application, the pins can be controlled through low-ohmic
switching FETs, e.g. BSH103 or equivalent (low R

EE

DSon

).

STM mode selection

The VCRO has a very large tuning range. However, the
performance of the OQ2541 is optimized for SDH/SONET
bit rates.

Table 3 STM mode select

MODE

BIT RATE

(Mbits/s)

STM1/OC3 155.52 16 V

DIVISION

FACTOR

DOUT155 DOUT622 DOUT1250

EE

STM4/OC12 622.08 4 ground V
Gigabit Ethernet 1250.00 2 ground ground V

LEVEL ON PIN

V

EE
EE

V

EE

V

EE
EE

STM16/OC48 2488.32 1 ground ground ground

1999 May 27 10

Philips Semiconductors Product specification

SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48 GE

Application with positive supply voltage

Due to the versatile design of the OQ2541 the device can
also operate in a positive supply voltage application,
although some pins have a different mode of operation.

This section deals with these differences and supports the
user with achieving a successful application of the
OQ2541 in a +5 V environment.

A

PPLICATION DIAGRAM

A sample application diagram can be found in Fig.29.
It should be noted that all pins GND are now connected to
VCC and all pins VEE are connected to the regulated
voltage from the power controller.

O

UTPUT SELECTION

In a positive supply voltage application, the loop mode is
the default RF output. Due to the decoding logic on
pin ENL, it is only possible to select the loop mode outputs
or enable all the outputs.

If pin ENL is connected to VCC (+5 V), only the loop mode
outputs are active (see Table 4). When pin ENL is
connected to VEE (the voltage is approximately 3.3 V
below VCC) all outputs become active. In the positive
supply voltage application the normal mode outputs can
not be selected, unless the voltage on pin ENL is 2 V
above the positive supply voltage (VCC).

CAUTION

Do not to connect pin ENL to ground, because this will
destroy the IC.

OQ2541HP; OQ2541U

LOSS OF SIGNAL AND LOCK DETECTION
In the negative supply application, pins LOS and LOCK

are open-collector outputs that require pull-up resistors to
a positive supply voltage.

In the positive supply application, the pull-up voltage would
need to be higher then the positive supply voltage and the
signals on pins LOS and LOCK would not be TTL
compatible any more. However, the internal circuit on
pins LOS and LOCK can be used in a current mirror
configuration (see Fig.9). This requires only an external
PNP transistor (e.g. BC857 or equivalent) to mirror the
current. A 10 kΩ pull-down resistor from the collector of the
external transistor to ground yields a TTL compatible
signal again, albeit inverted. Table 5 shows the meaning of
the LOS and LOCK flag, when used in the positive supply
application.

handbook, halfpage

MGL671

Fig.9 Signal out for LOS and LOCK indication in a

positive supply voltage application.

GND

LOS,
LOCK

off chipon chip

+5 V

BC857

signal out

10 kΩ

Table 4 Output selection in a positive supply voltage application

OUTPUT

MODE LEVEL ON PIN ENL

Loop V
Loop and normal V
Normal V

CC

(VCC− 3.3 V) active active

EE

CC

(+5 V) active −

+2V − active

DLOOP, DLOOPQ,

CLOOP AND CLOOPQ

DOUT, DOUTQ,

COUT AND COUTQ

Table 5 LOS and LOCK indication in a positive supply voltage application

SIGNAL DESCRIPTION LEVEL TTL

LOS active loss of signal: BER > 5 ⋅ 10

−2

LOS inactive no loss of signal: BER < 1 ⋅ 10

−3

0 V (ground) LOW

+5 V (VCC) HIGH
LOCK active reference clock present and VCRO inside 1000 ppm window 0 V (ground) LOW
LOCK inactive no reference clock present or VCRO outside 1000 ppm window +5 V (V

) HIGH

CC

1999 May 27 11