Philips OQ2541HP Datasheet
INTEGRATED CIRCUITS
DATA SH EET
OQ2541HP
SDH/SONET data and clock
recovery unit STM1/4/16
OC3/12/48
Preliminary specification
Supersedes data of 1998 Feb 09
File under Integrated Circuits, IC19
1999 Mar 19
Philips Semiconductors Preliminary specification
SDH/SONET data and clock recovery unit
OQ2541HP
STM1/4/16 OC3/12/48
FEATURES
• Data and clock recovery up to 2.5 Gbits/s (STM1/OC3,
STM4/OC12 and STM16/OC48)
• Differential data input with 2.5 mV peak-to-peak typical
sensitivity
• Differential CML (Current-Mode Logic) data and clock
outputs with 50 Ω driving capability
• Adjustable CML output level
• Loop mode for system testing
• BER related LOS detection
• Few external components needed
• LQFP48 plastic package
• Power dissipation typical 350 mW
• Single supply voltage.
ORDERING INFORMATION
TYPE
NUMBER
OQ2541HP LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
NAME DESCRIPTION VERSION
DESCRIPTION
The OQ2541HP is a data and clock recovery IC intended
for use in SDH (Synchronous Digital Hierarchy) and
SONET (Synchronous Optical Network) systems.
The circuit recovers data and extracts the clock signal from
an incoming bitstream up to 2.5 Gbits/s. It can be
configured for use in STM1/OC3, STM4/OC12 and
STM16/OC48 systems.
APPLICATIONS
• Data and clock recovery in STM1/OC3, STM4/OC12
and STM16/OC48 transmission systems (up to
2.5 Gbits/s).
PACKAGE
1999 Mar 19 2
Philips Semiconductors Preliminary specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48
BLOCK DIAGRAM
handbook, full pagewidth
DCSQ
DIN
DINQ
36
33
34
LOS
39
ALEXANDER
PHASE
DETECTOR
enable
DOUT_622
DOUT_1250
27
FREQUENCY
DIVIDER 1
1/2/4/16
OQ2541HP
DOUT_155
28
30
AREF
DATA
CLOCK
OUTPUT
48
AND
ENL
OQ2541HP
1
42
43
45
46
6
7
3
4
DOUT
DOUTQ
COUT
COUTQ
DLOOP
DLOOPQ
CLOOP
CLOOPQ
CREF
CREFQ
21
22
17 2
2, 5, 8, 10, 11, 14, 17,
20, 23, 26, 29, 32, 35,
38, 41, 44, 47
GND
FREQUENCY
WINDOW
DETECTOR
(1000 ppm)
FREQUENCY
12 24 25, 31
DREF_19LOCK
+
DIVIDER 2
64/128
9
CAPDOQDREF_39
∫ dt
CAPUPQ
proportional
path
integrating
path
130 pF130 pF
1516
VCRO
2.5 GHz
POWER
CONTROL
V
EE
37
MBH972
PC
Fig.1 Block diagram.
1999 Mar 19 3
Philips Semiconductors Preliminary specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48
PINNING
SYMBOL PIN DESCRIPTION
ENL 1 loop mode enable input (active low)
GND 2 ground
CLOOP 3 clock output in loop mode (differential)
CLOOPQ 4 inverted clock output in loop mode (differential)
GND 5 ground
DLOOP 6 data output in loop mode (differential)
DLOOPQ 7 inverted data output in loop mode (differential)
GND 8 ground
DREF_19 9 reference frequency select input (see Table 1)
GND 10 ground
GND 11 ground
LOCK 12 phase lock detection output
i.c. 13 internally connected (leave open)
GND 14 ground
CAPUPQ 15 external loop filter capacitor
CAPDOQ 16 external loop filter capacitor return
GND 17 ground
i.c. 18 internally connected (leave open)
i.c. 19 internally connected (leave open)
GND 20 ground
CREF 21 reference clock input (differential)
CREFQ 22 inverting reference clock input (differential)
GND 23 ground
DREF_39 24 reference frequency select input (see Table 1)
V
EE
GND 26 ground
DOUT_1250 27 STM mode select input (see Table 2)
DOUT_622 28 STM mode select input (see Table 2)
GND 29 ground
DOUT_155 30 STM mode select input (see Table 2)
V
EE
GND 32 ground
DIN 33 data input (differential)
DINQ 34 inverting data input (differential)
GND 35 ground
i.c. 36 internally connected (leave open)
PC 37 negative power supply control signal output
GND 38 ground
LOS 39 loss-of-signal detection output
i.c. 40 internally connected (leave open)
25 negative supply voltage
31 negative supply voltage
OQ2541HP
1999 Mar 19 4
Philips Semiconductors Preliminary specification
SDH/SONET data and clock recovery unit
OQ2541HP
STM1/4/16 OC3/12/48
SYMBOL PIN DESCRIPTION
GND 41 ground
DOUT 42 data output in normal mode (differential)
DOUTQ 43 inverted data output in normal mode (differential)
GND 44 ground
COUT 45 clock output in normal mode (differential)
COUTQ 46 inverted clock output in normal mode (differential)
GND 47 ground
AREF 48 reference voltage input for controlling voltage swing on data and clock outputs
handbook, full pagewidth
ENL
GND
CLOOP
CLOOPQ
GND
DLOOP
DLOOPQ
GND
DREF_19
GND
GND
LOCK
COUTQ
GND
47
14
GND
COUT
46
45
15
16
CAPUPQ
CAPDOQ
GND
44
OQ2541HP
17
GND
AREF
48
1
2
3
4
5
6
7
8
9
10
11
12
13
i.c.
DOUT
DOUTQ
43
42
18
19
i.c.
i.c.
GND
41
20
GND
i.c.
40
21
CREF
GND
LOS
39
38
22
23
GND
CREFQ
PC
36
35
34
33
32
31
30
29
28
27
26
25
24 37
MBH971
DREF_39
i.c.
i.c.
GND
DINQ
DIN
GND
V
EE
DOUT_155
GND
DOUT_622
DOUT_1250
GND
V
EE
Fig.2 Pin configuration.
1999 Mar 19 5
Philips Semiconductors Preliminary specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48
FUNCTIONAL DESCRIPTION
The OQ2541HP recovers data and clock signals from an
incoming high speed bitstream. The input signal on DIN,
DINQ is buffered and amplified by the input circuitry.
The signal is then fed to the Alexander phase detector
where the phase of the incoming data is compared with
that of the internal clock. If the signals are out of phase, the
phase detector generates (UP or DOWN) correction
pulses that shift the phase of the VCRO (Voltage
Controlled Ring Oscillator) output in discrete amounts, ∆ϕ,
until the clock and data signals are in phase.
The technique used is based on principles first proposed
by J.D.H. Alexander, hence the phase detector’s name.
The eye pattern of the incoming data is sampled at three
instants A, T and B (see Fig.3). When clock and data
signals are synchronized (locked), A is in the centre of the
data bit, T is in the vicinity of the next transition, and B is in
the centre of the bit following the transition. If the same
level is recorded at both A and B, a transition has not
occurred and no action is taken regardless of the value
at T. If A and B are different, however, a transition has
occurred and the phase detector uses the value at T to
determine whether the clock was too early or too late with
respect to the data transition. If A and T are the same, but
different from B, the clock was too early and needs to be
slowed down a little. The Alexander phase detector then
generates a DOWN pulse which stretches a single output
pulse from the ring oscillator by approximately 0.25% (or
1 ps in STM16 mode; 1 ps is 0.25% of the 400 ps bit
period). This forces the VCRO to run at a slightly lower
frequency for one bit period. The phase of the clock is thus
shifted fractionally with respect to the data.
OQ2541HP
of the clock signal, while the integrating path adjusts the
centre frequency.
The frequency window detector checks that the VCRO
frequency is within a 1000 ppm (parts per million) window
around the required frequency. It compares the output of
frequency divider 2 with the reference frequency at CREF,
CREFQ (19.44 MHz or 38.88 MHz as available; see
Table 1). If the VCRO frequency is found to be outside this
window, the frequency window detector disables the
Alexander phase detector and forces the VCRO output to
a frequency within the window. The phase detector then
starts acquiring lock again. Because of the loose coupling
(1000 ppm), the reference frequency doesn’t need to be
highly accurate or stable. Any crystal based oscillator that
generates a reasonably accurate frequency (e.g. 100ppm)
will do.
Since sampling point A is always in the centre of the eye
pattern when the data and clock signals are in phase
(locked), the values recorded at this point are taken as the
retrieved data. The data and clock signals are available at
the CML output buffers, which are capable of driving a
50 Ω load.
handbook, halfpage
DATADATA
ATB
CLOCK
MGK143
Fig.3 Data sampling.
If, on the other hand, B and T are the same but different
from A, the clock was too late and needs to be speeded up
for synchronization. The phase detector generates an UP
pulse forcing the VCRO to run at a slightly higher
frequency (+0.25%) for one bit period. The phase of the
clock is shifted with respect to the data (as above, but in
the opposite direction). Only the proportional path is active
while these phase adjustments are being made. Because
the instantaneous frequency of the VCRO can be changed
only in one of two discrete steps (±0.25%), this type of loop
is also known as a Bang/Bang PLL.
If not only the phase but also the frequency of the VCRO
is incorrect, a long train of UP or DOWN pulses will be
generated. This pulse train is integrated to generate a
control voltage that is used to shift the centre frequency of
the VCRO. Once the correct frequency has been
established, the phase will need to be adjusted for
synchronization. The proportional path adjusts the phase
1999 Mar 19 6
Power Control (PC)
The OQ2541HP contains an on-board voltage regulator.
An external power transistor is needed to deliver supply
current, IEE, to this circuit. The required external circuit is
straightforward, and can be built using a few components.
A suitable circuit is depicted in Fig.21. A different
configuration could be used, as long as the power supply
rejection ratio is greater than 60 dB for all frequencies.
The inductor is a (lossy) 1 µH RF-choke (EMI) with an
impedance greater than 50 Ω at frequencies higher than
2 MHz. Any transistor with a β > 100 and enough current
sink capability can be used.
The OQ2541HP can also be used with a -5V or -5.2V
supply voltage. The only adaption that has to be made to
the Power Control circuit is resistor R of 2Ω. This should
be 6.8Ω with a -5V supply and 8.2Ω with a -5.2V supply.
Philips Semiconductors Preliminary specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48
handbook, full pagewidth
BAND GAP
REFERENCE
V
100 nF
2 Ω
1 kΩ
EE
β > 100
R1
2 Ω
kΩ
OQ2541HP
OQ2541
PC
3.3
1
nF
1 µF
L1
MGK141
−4.5 V
Fig.4 Schematic diagram of OQ2541HP power control loop.
Output amplitude reference (AREF)
The voltage swing at the CML compatible output stages
DOUT, DOUTQ; COUT, COUTQ; DLOOP, DLOOPQ and
CLOOP, CLOOPQ can be controlled by adjusting the
voltage at the AREF pin. An internal voltage divider of
500 Ω and16 kΩ between GND and VEE initially fixes this
level.
In most applications the outputs will be DC coupled to a
load, which can be as low as 50 Ω (±0.20%). The output
level regulation circuit will maintain a 200 mV
peak-to-peak single-ended swing across this load.
The voltage at AREF is half the single-ended peak-to-peak
value of the output signal (or −100 mV in this case).
No adjustments are necessary with DC coupling.
If the outputs are AC coupled, however, the voltage at
AREF is half the single-ended peak-to-peak value of the
+
R
output signal multiplied by a factor
where R
is the external load and Ro is the output
L
LRo
-------------------R
L
impedance of the OQ2541HP.
This can be achieved by connecting a 7.3 kΩ resistor
between AREF and V
EE
.
The formulae for calculating the required voltage at AREF
and the external resistance needed between AREF and
V
when the outputs are AC coupled are:
EE
V
AREF
RLRo+
-------------------R
1
V
×–=
-- -
swing
2
L
(1)
and:
V
EE
R1
×
---------------- V
R
AREF
=
----------------------------------------------------------------
–
1
AREF
R1
×
------- R2
where R1 = 500 Ω, R2 = 16 kΩ and V
V
EE
---------------- V
AREF
1–
(2)
1–
= −3.3 V. R
EE
AREF
is connected between AREF and VEE.
To maintain a 200 mV peak-to-peak single-ended swing
across a 50 Ω AC coupled load, the voltage at AREF must
100 mV– 50 Ω 100 Ω+()×
be .
-------------------------------------------------------------------------
1999 Mar 19 7
50 Ω
300 mV–=
Philips Semiconductors Preliminary specification
SDH/SONET data and clock recovery unit
STM1/4/16 OC3/12/48
Loop mode enable (ENL)
Loop mode is provided for system testing. Loop mode is
enabled by applying a voltage lower than 0.8 V (TTL LOW)
to the ENL pin. This selects loop mode outputs DLOOP,
DLOOPQ and CLOOP, CLOOPQ. If a voltage greater than
2.0 V (TTL HIGH) is applied to ENL, then DOUT, DOUTQ
and COUT, COUTQ are switched in while DLOOP,
DLOOPQ and CLOOP, CLOOPQ are disabled to minimize
power consumption. If ENL is connected to VEE(−3.3 V),
all outputs are enabled.
External capacitor for loop filter (CAPUPQ; CAPDOQ)
The loop filter is an integrator with a built in capacitance of
2 × 130 pF. An external 200 nF capacitance must be
connected between CAPUPQ and CAPDOQ to ensure
loop stability while the frequency window detector is
active.
Lock detection (LOCK)
The LOCK pin should be interpreted as an indication if the
reference clock (CREF) is present and if the acquisition aid
(frequency window detector) is working properly.
The LOCK pin is an open collector TTL output and should
be pulled up with a 10kΩ resistor to the positive supply.
If the VCO frequency is within a 1000 ppm window around
the desired frequency the LOCK pin will go HIGH. If no
reference clock is present, or the VCO is outside the 1000
ppm window, the LOCK pin will be LOW. The logic level of
LOCK does not indicate if the PLL is locked onto the
incoming data; this is indicated by the LOS signal.
OQ2541HP
Loss-of-signal detection (LOS)
The Loss of Signal (LOS) function is closely related to the
Alexander Phase Detector functionality. Refer to Fig.3 for
the meaning of A,B and T in this section.
In the functional description it is described that the phase
detector doesn’t take any action if the value at sample
points A and B is the same, because there hasn’t been any
transition. However, if the values at A and B are the same,
but different from T, this still means there hasn’t been any
transition, but somehow T got the wrong value. This is
probably due to noise or bad signal integrity, which will
lead to a Bit Error. Hence the occurrence of this particular
situation is an indication for Bit Errors. If too many of these
Bit Errors occur per time and the PLL is gradually losing
lock, the LOS alarm is asserted. The LOS assert level is
around a Bit Error Rate (BER) of 5⋅10
level is around BER of 1⋅10-3.
The LOS detection is BER related, but neither dependent
of datastream content, nor protocol. Therefore, a
SDH/SONET datastream is no prerequisite for a proper
LOS function. Since the LOS function of the OQ2541HP is
derived from digital signals, it is a good supplement to an
analog, amplitude based, LOS indication.
The LOS alarm is an open collector TTL compatible
output. A pull-up resistor should be connected to a positive
supply. LOS will be HIGH (TTL) if the data signal is absent
at DIN, DINQ or BER is > 5⋅10-2, otherwise it will be LOW
(BER < 1⋅10-3).
-2
and the de-assert
Reference frequency select (DREF_19, DREF_39)
A reference clock signal (either 19.44 MHz or 38.88 MHz, whichever is available) must be connected to CREF and
CREFQ. Pins DREF_19 and DREF_39 are used to select the appropriate output frequency at frequency divider 2. Since
the reference clock is only used as acquisition aid for the PLL (Frequency Window Detector), the quality of the reference
clock is not important. There is no phase noise specification imposed on the reference clock generator and even
frequency stability may be in the order of 100 ppm. In general most inexpensive crystal based oscillators are suitable.
Table 1 Reference Frequency Select
FREQUENCY
MHz
19.44 128 V
38.88 64 GND V
1999 Mar 19 8
DIV # DREF_19 DREF_39
EE
V
EE
EE
Philips Semiconductors Preliminary specification
SDH/SONET data and clock recovery unit
OQ2541HP
STM1/4/16 OC3/12/48
STM mode select (DOUT_155, DOUT_622, DOUT_1250)
All three mode select pins should be connected to GND for STM16 (2488.32 Mbits/s) operation. The dividers are daisy
chained, so both DOUT_1250 and DOUT_622 must be connected to VEE in STM4 (622.08 Mbits/s) mode. All three pins
must be connected to VEE in STM1 mode (see Table 2). The connections to VEE and GND should have low resistance
and inductance; short PCB tracks are recommended.
Table 2 STM Mode Select
MODE
STM1 155.52 16 V
STM4 622.08 4 GND V
STM16 2488.32 1 GND GND GND
BIT RATE
Mbits/s
DIV # DOUT_155 DOUT_622 DOUT_1250
EE
V
EE
EE
V
EE
V
EE
1999 Mar 19 9
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