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OM6211

48 × 84 dot matrix LCD driver

Product specification
File under Integrated Circuits, IC12

2002 Jan 17

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

CONTENTS

1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 PIN FUNCTIONS

7.1 ROW 0 to ROW 47 row driver outputs

7.2 COL 0 to COL 83 column driver outputs

7.3 V

7.4 V

7.5 V

and V

SS1

to V

DD1
LCDOUT

: negative power supply rails

SS2

: positive power supply rails

DD3

, V

LCDIN

and V

LCDSENSE

: LCD power

supply

7.6 V

OS4

to V

: calibration inputs

OS0

7.7 SDIN: serial data input

7.8 SDOUT: serial data output

7.9 SCLK: serial clock input

7.10 SCE: chip enable

7.11 OSC: oscillator

7.12 MX: horizontal mirroring

7.13 ID3 and ID4: identification inputs

7.14 RES: reset

7.15 T1, T2, T3, T4, T5 and T6: test pins
8 BLOCK DIAGRAM FUNCTIONS

8.1 Oscillator

8.2 Serial interface control

8.3 Command decoder

8.4 Display data RAM (DDRAM)

8.5 Timing generator

8.6 Address Counter (AC)

8.7 Display address counter

8.8 V

generator

LCD

8.9 Bias voltage generator

8.10 LCD row and column drivers

8.11 Reset
9 FUNCTIONAL DESCRIPTION

9.1 Reset

9.2 Power-down

9.3 LCD voltage selector

9.4 Oscillator

9.5 Timing

9.6 Column driver outputs

9.7 Row driver outputs

9.8 Drive waveforms

9.9 Bias system

9.10 Voltage multiplier control

9.11 Temperature compensation

9.12 V

generator

LCD

10 INITIALIZATION

10.1 Initialization sequence

10.2 Frame frequency calibration (OC)
11 ADDRESSING

11.1 Addressing

11.2 Serial interface

11.2.1 Write mode

11.2.2 Read mode
12 INSTRUCTIONS

12.1 Instruction set
13 LIMITING VALUES
14 HANDLING
15 DC CHARACTERISTICS
16 AC CHARACTERISTICS

16.1 Serial interface timing

16.2 Reset timing
17 APPLICATION INFORMATION
18 MODULE MAKER PROGRAMMING

18.1 V

calibration

LCD

18.2 VPR default value

18.3 Seal bit

18.4 OTP architecture

18.5 Serial interface commands

18.5.1 Enable OTP

18.5.2 CALMM

18.5.3 Load factory default

18.5.4 Refresh

18.6 Example of filling the shift register

18.7 Programming flow

18.8 Programming specification
19 BONDING PAD LOCATIONS
20 DEVICE PROTECTION DIAGRAM
21 TRAY INFORMATION
22 DATA SHEET STATUS
23 DEFINITIONS
24 DISCLAIMERS

2002 Jan 17 2

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

1 FEATURES

• Single-chip LCD controller/driver

• 48 row, 84 column outputs

• Display data RAM 48 × 84 bits

• 3-line serial interface, maximum 4.0 Mbit/s

• On-chip:

– Generation of LCD supply voltage V

LCD

– Generation of intermediate LCD bias voltages
– Oscillator (requires no external components).

• CMOS compatible inputs

• Mux rate1:48

• Logic supply voltage range V

DD1

to VSS:

– 1.7 to 2.3 V.

• Supply voltage range for high voltage part V

DD2

to VSS:

– 2.5 to 4.5 V.

• LCD supply voltage range V

LCD

to VSS:

– 4.5 to 9.0 V.

• Low power consumption (typical 90 µA), suitable for
battery operated systems

• External reset

• Temperature compensation of V

• Temperature range: T

amb

LCD

= −40 to +85 °C

• Manufactured in N-well silicon gate CMOS process.

2 APPLICATIONS

• Battery powered telecommunication systems.

3 GENERAL DESCRIPTION

The OM6211 is a low power CMOS LCD row/column
driver, designed to drive a dot matrix graphic display of
48 rows and 84 columns. All necessary functions for the
display are provided in a single chip, including on-chip
generation ofLCDsupply and bias voltages, resulting in a
minimum of external components and low power
consumption. The OM6211 interfaces to microcontrollers
via a 3-line serial interface.

4 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

OM6211U/2/F1 tray chip with bumps in tray −

2002 Jan 17 3

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

5 BLOCK DIAGRAM

V

handbook, full pagewidth

DD1

V

DD2VDD3

COL0 to COL83

ROW0 to ROW47

V
V

T4, T5,

T1, T2,

ID3, ID4

V

LCDIN

V

LCDsense

V

LCDOUT
V

OS

SCLK

SDOUT

SS1
SS2

T6

T3

MX

[

4:0

SDIN

84

COLUMN DRIVERS

3

3

2

BIAS

VOLTAGE

GENERATOR

V

LCD

GENERATOR

5

]

SERIAL INTERFACE

CONTROL

OM6211

DATA LATCHES

DISPLAY DATA RAM

48 × 84 bits

COMMAND

DECODER

SCE

SHIFT REGISTER

48

ROW DRIVERS

RESET

OSCILLATOR

TIMING

GENERATOR

DISPLAY
ADDRESS
COUNTER

ADDRESS

COUNTER

RES

OSC

MGU272

Fig.1 Block diagram.

2002 Jan 17 4

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

6 PINNING

SYMBOL PAD DESCRIPTION

V

OS4

3 input pin 4 for V

LCD

calibration

V

OS3

4 input pin 3 for V

LCD

calibration

V

OS2

5 input pin 2 for V

LCD

calibration

V

OS1

6 input pin 1 for V

LCD

calibration

V

OS0

7 input pin 0 for V

LCD

calibration
T6 8 to 11 test input 6
RES 16 external reset input

(active LOW)
T5 17 test input 5
T4 18 test input 4
T3 19 test output 3
T2 20 test output 2
T1 21 test output 1
SCE 22 chip enable input

(active LOW)
V

SS2

V

SS1

23 to 30 ground

31 to 38 ground
OSC 40 oscillator input
SDOUT 41 serial data output

SYMBOL PAD DESCRIPTION

SDIN 42 serial data input
SCLK 43 serial clock input
ID4 44 module identification input
ID3 45 module identification input
MX 46 horizontal mirroring input
V

DD1

V

DD2

47 to 52 logic supply voltage
53 to 60 voltage multiplier supply

voltage

V

DD3

61 to 64 voltage multiplier supply

voltage

V

LCDSENSE

65 V

generator regulation

LCD

input

V

LCDOUT

V

LCDIN

ROW 0 to

66 to 72 V

generator output

LCD

73 to 78 LCD supply voltage input

89 to 112 LCD row driver outputs

ROW 23
COL0to

113 to 196 LCD column driver outputs

COL 83
ROW 47 to

197 to 220 LCD row driver outputs

ROW 24

1,12 to 15,

dummy pads

39, 79,

81 to 88

and

221 to 225

7 PIN FUNCTIONS

7.1 ROW 0 to ROW 47 row driver outputs

These pads output the display row signals.

7.2 COL 0 to COL 83 column driver outputs

These pads output the display column signals.

7.3 V

Negative power supply rails V

SS1

and V

: negative power supply rails

SS2

SS1

and V

must be

SS2

connected together, hereafter referred to as VSS. When a
pin has to be connected externally to VSS, then pin V

SS1

should be used.

7.4 V

Positivepowersupplyrails: V
V

DD3

connected together, hereafter referred to as V

DD1

to V

: positive power supply rails

DD3

for voltage multiplier. V

forlogicsupply,V

DD1

and V

DD2

DD3

must be

DD2

DD2

.

and

2002 Jan 17 5

7.5 V

LCDOUT

, V

LCDIN

and V

LCDSENSE

: LCD power

supply

If the internal V
must be connected together. If not (V
disabledand an external voltageisapplied to V
V

must be left open-circuit, V

LCDOUT

connected to V

generator is used, then all three pins

LCD

generator is

LCD

LCDIN

must be

LCDIN

, V

DD2

and V

LCDSENSE

should be applied

DD3

),then

according to the specified voltage range. The following
settings are also required: HVE = 0, S1= 1 and S0=0.

7.6 V

Five pull-up input pins for on-glass V

OS4

to V

: calibration inputs

OS0

calibration. Each

LCD

pin may be connected to VSS, which corresponds to
logic 0, or left open-circuit, which corresponds to logic 1.
All five pins define a 5-bit two’s complement number
ranging from −16 to 15 decimal (from 10000 to 01111).
The default value, with all pins connected to VSS, is
0 decimal (00000).

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

In order to reduce current consumption related to the
pull-up circuitry, the 5-bit number is stored in a register
when exiting the Power-down mode. The pull-up circuitry
is then disabled. Additionally, the register is refreshed by
each HVE command.

7.7 SDIN: serial data input

Serial data input.

7.8 SDOUT: serial data output

Serial data output (3-state, push-pull). If bidirectional data
transmission is required, SDOUT and SDIN should be
connected externally. If the read mode is not used,
SDOUT should be left open-circuit.

7.9 SCLK: serial clock input

Serial clock input.

7.10 SCE: chip enable

Chip enable input, active LOW. If SCE is HIGH, the SCLK
pulses are ignored.

7.11 OSC: oscillator

External clock input. The external clock is active only in a
special test mode, so in the application it is not available.
In normal mode (the internal on-chip oscillator used) this
input must be connected to VSS. If OSC is held HIGH, the
internal oscillator is disabled.

8 BLOCK DIAGRAM FUNCTIONS

8.1 Oscillator

The on-chip oscillator provides the clock signal for the
display system. It has no external components.

8.2 Serial interface control

Detects the serial interface protocol, commands and
display data bytes. The serial interface converts the data
input (serial-to-parallel) as well as the output bits.

8.3 Command decoder

Decodes all commands.

8.4 Display Data RAM (DDRAM)

The OM6211 contains a 48 × 84 bit static RAM which
stores the display data. The RAM is divided into six banks
of 84 bytes (6 × 8 × 84 bits). During RAM access, data is
transferred to the RAM via the serial interface. There is a
directcorrespondencebetween the X address and column
output number.

8.5 Timing generator

The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations of the serial
interface.

8.6 Address Counter (AC)

7.12 MX: horizontal mirroring

Horizontal mirroring input. When MX = 1 the X address
space is mirrored.

7.13 ID3 and ID4: identification inputs

LCD module identification inputs. Their state can be read
out via the serial interface in order to identify the module
version.

7.14 RES: reset

External reset pin. When LOW the chip will be reset as
defined in Section 9.1. The initialization by the RES pin is
always required during power-on. Timing for the RES pin
is illustrated in Fig.18.

7.15 T1, T2, T3, T4, T5 and T6: test pins

Test pins. Inthe application T4 and T5 mustbe connected
toVSS.T1, T2, T3 and T6 must be left open-circuit(T6 has
a pull-down resistor).

2002 Jan 17 6

The address counter assigns addresses to the display
data RAM for writing. The X address (X6to X0) and the
Y address (Y2to Y0) are set separately. After a write
operation the address counter is automatically
incremented by 1.

8.7 Display address counter

The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status(all dotson/off, normal/inverse video) is
set via the serial interface.

8.8 V

generator

LCD

A voltage multiplier (charge pump) with a programmable
number of stages. Internal capacitors are used for the
voltage multiplier, therefore only decoupling capacitors for
V

LCD

and V

are required.

DD2

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

8.9 Bias voltage generator

Generates 4 intermediate LCD bias voltages. The bias
system is selectable; see Section 9.9.

8.10 LCD row and column drivers

The OM6211 contains 48 row and 84 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. Figure 3 shows typical waveforms.

8.11 Reset

A reset initializes the chip. It can be performed either by
the RES pin being LOW or by a command.

handbook, full pagewidth

V

V
V

DD2

DD1

DD2, 3

V

DD1

9 FUNCTIONAL DESCRIPTION

The OM6211 is a low power LCD driver designed to
interface with microprocessors/microcontrollers and a
wide variety of LCDs.

The host microprocessor or microcontroller and the
OM6211 are connected via a serial interface. The internal
oscillator requires no external components. The
appropriate intermediate bias voltages for the multiplexed
LCD waveforms are generated on-chip. The only other
connections required to complete the system are to the
power supplies (V
capacitors for decoupling V

V

LCD

DD1

, V

DD2

, VSS and V

and V

LCD

) and suitable

LCD

.

DD2

RES
SCE

SCLK

SDA
V

SS

HOST

MICROPROCESSOR/

MICROCONTROLLER

V

SS

84 column drivers

48 row drivers

V

SS1, 2

OM6211

Fig.2 Typical system configuration.

LCD

PANEL

MGU273

2002 Jan 17 7

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

9.1 Reset

TheOM6211 has no internalPower-onreset, only external
reset and reset by command. After power-on an external
reset is required. A reset initiated either from the RES pin
or by command will initialize the chip to the following
starting conditions:

• Power-down mode (DON = 0 and DAL = 1):
– Internal oscillator stopped
– The V

(HVE = 0) and V

generator (HV generator) is switched off

LCD

is 3-state

LCDOUT

– Display is off and all LCD outputs are internally

connected to VSS (DON = 0)

– Display all points is on (DAL = 1).

• Serial interface initialized; write mode

• Display normal video (E = 0)

• Address counter X6to X0=0;Y2to Y0= 0; display start

line Z5to Z0= 0; no Y mirroring (MY = 0)

1

• Bias system

• V

selection V

LCD

⁄7 (BS2to BS0= 100)

PR7

to V

PR0

=0

• Voltage multiplication factor 4 (S1and S0= 10)

• Temperature control mode TC3 (TC1and TC0= 11)

• Frequency not calibrated and OC = 0

• RAM data is unchanged (after power-up undefined).

9.3 LCD voltage selector

The practical value for V
V

with a defined LCD threshold voltage (Vth),

off(rms)

is determined by equating

LCD

typically when the LCD exhibits approximately 10%
contrast.

9.4 Oscillator

The internal logic operation and the multi-level drive
signals of the OM6211 are clocked by the built-in RC
oscillator. No external components are required. The
oscillator is in operation as long as the chip is not in
Power-down mode.

9.5 Timing

The timing of the OM6211 organizesthe internal data flow
of the device. The timing also generates the LCD frame
frequency that is derived from the clock frequency
generated by the internal clock generator.

9.6 Column driver outputs

The LCD drive section includes 84 column outputs, which
should be connected directly to the LCD. The column
output signals are generated in accordance with the
multiplexed row signals and with the data in the display
latch. If less than 84 columns are required, the unused
column outputs should be left open-circuit.

9.2 Power-down

The chip is in Power-down mode if the display is off
(DON = 0) and display all points is on (DAL = 1),
regardless of the order in which both bits are set. During
the Power-down mode almost all static currents are
switched off (no internal oscillator, no timing and no LCD
segment drive system), and all LCD outputs are internally
connected to VSS. The V

generator is switched off (but

LCD

HVEis not affected).The serial interfacefunction remains.
RAM data is unchanged. When exiting the Power-down
mode, the VOS value is stored in a register.

9.7 Row driver outputs

The LCD drive section includes 48 row outputs, which
should be connected directly to the LCD. If less than
48 rows are required, the unused row outputs should be
left open-circuit.

2002 Jan 17 8

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

9.8 Drive waveforms

ROW 0
R0 (t)

ROW 1
R1 (t)

COL 0
C0 (t)

COL 1
C1 (t)

V
V3 − V

LCD

SS

V
V
V

V
V
V

V
V
V

V
V
V

V
V
V

V
V
V

V
V
V

V
V
V

LCD
2
3

4
5
SS

LCD
2
3

4
5
SS

LCD
2
3

4
5
SS

LCD
2
3

4
5
SS

frame n frame n + 1

V

state1

V

state2

(t)
(t)

V

− V

LCD

V

V

V

(t) = C1(t) − R0(t).

state1

V

(t) = C1(t) − R1(t).

state2

state1

state2

(t)

(t)

0 V

V3 − V

V

LCD

V3 − V

V

LCD

0 V

V3 − V

2

SS

− V

2

2

2

012345678... ... 47 012345678... ... 47

Fig.3 Typical LCD driver waveforms.

2002 Jan 17 9

V4 − V

0 V

VSS − V

V4 − V

− V

LCD

V4 − V

0 V
VSS − V

V4 − V

− V

LCD

MGU274

5

5

LCD

5

5

LCD

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

9.9 Bias system

The bias voltage levels are set in the ratio of
R-R-nR-R-R. Different multiplex rates require
different factors of n. This is programmed by BS2to BS0.
For optimum bias values, n can be calculated from the
following equation:

n Mux rate 3–=

; where Mux rate is 48.

Changing the bias system from the optimum setting will
have a consequence on the contrast and viewing angle.

Table 1 Programming the required bias system

BS

2

BS

1

BS

0

0114
1003
1012

Table 2 LCD bias voltages for

SYMBOL

V1 V
V2
V3
V4
V5
V6 V

1

⁄6bias,1⁄7bias and1⁄8bias.

1

⁄6BIAS FOR1⁄7BIAS FOR1⁄8BIAS

FOR

LCD

5

⁄6V

LCD

4

⁄6V

LCD

2

⁄6V

LCD

1

⁄6V

LCD

SS

One reason to depart from the optimum would be to
reduce the required V
contrast and V

must be found for any particular

LCD

voltage. A compromise between

LCD

application.
In the OM6211 one of three possible values of the bias

1

system can be selected. The value

n BIAS MODE

1

⁄

8

1

⁄

7

1

⁄

6

⁄7 is default.

TYPICAL MUX

RATES

1 : 55 and 1 : 48

1:33
1:24

BIAS VOLTAGE

V

LCD

6

⁄7V

LCD

5

⁄7V

LCD

2

⁄7V

LCD

1

⁄7V

LCD

V

SS

V

LCD

7

⁄8V

LCD

6

⁄8V

LCD

2

⁄8V

LCD

1

⁄8V

LCD

V

SS

9.10 Voltage multiplier control

The OM6211 incorporates a software configurable voltage multiplier. After reset (
4V

. Other voltage multiplier factors are set via the serial interface (S1and S0).

DD2

Table 3 HV generator multiplication

S

1

S

0

002V
013V
104V
1 1 not available

2002 Jan 17 10

RES) the voltage multiplier is set to

MULTIPLICATION

DD2
DD2
DD2

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

9.11 Temperature compensation

Due to thetemperature dependencyof the liquid crystals viscosity, the LCDcontrolling voltage(V
at lower temperatures to maintain optimum contrast. Figure 4 shows V

as a function of temperature for a typical high

LCD

multiplex rate liquid.
In the OM6211 the temperature coefficient of V

can be selected from 4 values by setting bits TC1and TC0,

LCD

see Tables 4 and 8.

handbook, full pagewidth

9.12 V

generator

LCD

Thebinary number V

V

LCD

Fig.4 V

representingthe operating voltage

OP

as a function of liquid crystal temperature (typical values).

LCD

can be set by the serial interface command and can be
adjusted (calibrated) by 5 input pins according to the
following formula:

V

OP

V

+=

PRVOS

(1)

where:

is an 8-bit unsigned number set by the serial

• V

PR

interface command

• VOS is a 5-bit two’s complement number set by the
5 input pins V

OS4

to V

, see Table 9

OS0

• VOP is an 8-bit unsigned number used internally for
generation of the LCD supply voltage V

To avoid numerical overflow the allowed values of V

LCD

.

PR

should be limited to the range 32 to 225 (decimal).
The corresponding voltage at the reference temperature,

T

, can be calculated as follows:

nom

V

LCD(Tnom)

The generated voltage at V

aVOPb×+()=

is dependent on the

LCD

(2)

V

LCD

T

nom

aV

+ b×()1TC TT

OP

, a and b foreach temperaturecoefficient are given in
Table 4. The maximum voltage that can be generated is
dependent on the voltage of V
current.

As the programming range for the internally generated
V

allows values abovethe maximumallowed V

LCD

user has to ensure while setting the VPR register and
selecting the Temperature Compensation, that under all
conditions and including all tolerances the V
maximum 9 V will never be exceeded.

For a particular liquid crystal, the optimum value of V
can be calculated for a givenmultiplex rate. Fora Mux rate
of 1 : 48, the optimum operating voltage of the liquid
crystal can be calculated as follows;

V

LCD

where V

148+

---------------------------------------



21

×



is the thresholdvoltage of theliquid crystal used.

th

–

1

---------­48

T

MGT848

× 6.06 Vth×==

V

DD2

th

temperature, programmed Temperature Coefficient (TC)
and the programmedvoltage at thereference temperature
(T

).

nom

) must beincreased

LCD

–()×+[]×=

nom

and the display load

LCD

limit of

LCD

(3)

, the

LCD

(4)

2002 Jan 17 11

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

Table 4 Typical values for parameters of the HV generator programming

SYMBOL TC0 TC1 TC2 TC3 UNIT

a 4.57 4.28 4.04 3.79 V
b 30.0 28.0 26.5 25.0 mV
T

nom

TC 0 −0.25 −0.5 −0.75 10

27 27 27 27 °C

-3

/°C

Example: to achieve V
Example for calibration: Before calibration VPR= 180 was applied, but the measured voltage was V

To decrease V

by 100 mV the best value for VOSis −4 decimal (11100 binary in the two’s complement notation). So

LCD

= 8.3 V at temperature T

LCD

for TC3 it is necessary to set VPR= 180 (decimal).

nom

LCD

= 8.4 V.

after calibration with VOS= −4 the proper VPR value is still 180.
As VOS is used for calibration and the default value is 0, for selecting the value of VPR it can always be considered that

VOS=0.

handbook, full pagewidth

V

LCD

b

MGT847

a

00 01 02

V

to V

OP7

programming, (00H to FFH).

OP0

03 04 05 06

. . . . . . FD FE FF

Fig.5 V

programming of OM6211.

LCD

2002 Jan 17 12

V

OP

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

10 INITIALIZATION

10.1 Initialization sequence

After reset (RES) it is recommended to initialize the V

LCD

generator using the following sequence; a starting state of
HVE = 0, DON = 0 and DAL = 1 is assumed:

1. Set the required VOP and, if required, the voltage
multiplier S1and S

0

2. SetDAL = 0to leave thePower-downstate (in order to
precharge the charge pump V

is set to V

LCD

DD2

)

3. Waitfor at least 1 msand set HVE = 1to switch-on the
V

generator

LCD

4. Set DON = 1 to switch the display on.

10.2 Frame frequency calibration (OC)

The OM6211 incorporates frame frequency calibration via
software. The calibrationis achievedby tuning the internal
oscillator. After reset the frame frequency calibration is
disabled (OC = 0). The calibration can only be performed
if the driver is not in Power-down mode. The calibration is
started by setting OC = 1 via the serial interface (start
command) and will be stopped by setting OC = 0 (stop
command). The time between start and stop of the
calibration must be 200 ms to give a frame frequency of
80 Hz. Any variation in calibration time (deviation from
200 ms) results in a corresponding variation in frame
frequency. During calibration all other commands are
allowed.

The calibration may be repeated and is always performed
with the previously calibrated frequency. Through
repeated calibrations a better accuracy can be expected
and, most especially, the temperature drift can be
compensated for. A minimum time delay of 500 ms
between consecutive calibration events is necessary
(between stop and start).

The calibration will always be performed if the calibration
time is between 190 and 210 ms. If, however, the
calibration time is lower then 58 ms or higher than 690 ms
(orthe stop commanddoesnot occur at all),the calibration
attemptisignored and the previously selectedfrequencyis
maintained. For the remaining values of the calibration
time(from 58 to 190 ms andfrom 210 to 690 ms) itcannot
be determined if the calibration will be performed or
ignored.

11 ADDRESSING

11.1 Addressing

Data is downloaded in bytes into the RAM matrix of
OM6211 as illustrated in Figs 6 and 7. The display RAM
has a matrix of 48 × 84 bits. The columns are addressed
by the address pointer. The address ranges are
X = 0 to 83 (1010011) and Y = 0 to 5 (101). Addresses
outside of these ranges are not allowed. The X address
increments after each byte (see Fig.7). After the last
X address (X = 83) X wrapsaround to 0 and Y increments
toaddress the next row.Afterthe very lastaddress(X = 83
and Y = 5) the address pointers wrap around to address
X = 0 and Y = 0.

The selection of the MX input allows horizontal mirroring:
whenMX = 1, the X addressspace is mirrored(see Fig.6).
When MX = 0 the mirroring is disabled. MX affects data
only during writing to the RAM, so after a change of MX
RAM data must be re-written.

The MY bit allows vertical mirroring: when MY = 1, then
the Y address space is mirrored. MY does not affect the
RAM content, but defines the way RAM data is written to
the display. A change of MY has an immediate effect on
the display.

Vertical scrolling of the display is controlled by the
Z address with a range from 0 to 47 (101111). The
Z address specifies which rows of the RAM are output to
which row outputs. The value of the Z address defines
which row of the RAM will be ROW 0 of the display (which
is normally the top row of the display). For example, if the
Z address is set to 31 (see Fig.8), then the data displayed
on ROW 0 of the display will be the data from ROW 31 of
the RAM and the data on ROW 1 will be from ROW 32 of
the RAM. When the MY is active (MY = 1), then the
Z address defines which row of the RAM is written to
ROW 47 of the display. For example, when the Z address
is set to 31, ROW 47 of the display would come from
ROW 31 of the RAM and ROW 46 from ROW 32 of the
RAM (see Fig.9).

The Z address does not affect the RAM content, but
defines the way RAM data is written to the display.
A change of Z address has an immediate effect on the
display.

2002 Jan 17 13

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

handbook, full pagewidth

LSB

MSB

MX = 0
MX = 1

0

83

X address

Fig.6 RAM format, addressing.

0

Y address

5

83

0

MGU275

handbook, full pagewidth

012

84 85 86
168 169 170
252 253 254
336 337 338
420 421 422

083X address

Fig.7 Sequence of writing data bytes into RAM.

2002 Jan 17 14

0

Y address

5503

MGT845

Philips Semiconductors Product specification

48 × 84 dot matrix LCD driver OM6211

MGU276

ROW 0

ROW 1

ROW 2

ROW 3

ROW 4

ROW 5

ROW 6

ROW 7

ROW 8

ROW 9

ROW 10

ROW 11

ROW 12

ROW 13

ROW 14

ROW 15

ROW 16

ROW 17

ROW 18

ROW 19

ROW 20

ROW 21

ROW 22

ROW 23

ROW 24

ROW 25

ROW 26

ROW 27

ROW 28

ROW 29

ROW 30

ROW 31

ROW 32

ROW 33

ROW 34

ROW 35

ROW 36

ROW 37

ROW 38

ROW 39

ROW 40

ROW 41

ROW 42

ROW 43

ROW 44

ROW 45

ROW 46

ROW 47

012345678

Z address when MY = 0

RAM DISPLAY

9

1011121314151617181920212223242526272829303132

Z address = 31

333435363738394041424344454647

Fig.8 Programming the Z address when MY = 0.

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2002 Jan 17 15

Y address

0

1

2

3

4

5