Philips OM6211 Technical data

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OM6211

INTEGRATED CIRCUITS

DATA SHEET

OM6211

48 × 84 dot matrix LCD driver

Product speciﬁcation			2002 Jan 17
File under Integrated Circuits, IC12

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

CONTENTS

1FEATURES

2APPLICATIONS

3GENERAL DESCRIPTION

4ORDERING INFORMATION

5BLOCK DIAGRAM

6PINNING

7PIN FUNCTIONS

7.1ROW 0 to ROW 47 row driver outputs

7.2COL 0 to COL 83 column driver outputs

7.3VSS1 and VSS2: negative power supply rails

7.4VDD1 to VDD3: positive power supply rails

7.5VLCDOUT, VLCDIN and VLCDSENSE: LCD power

supply

7.6VOS4 to VOS0: calibration inputs

7.7SDIN: serial data input

7.8SDOUT: serial data output

7.9SCLK: serial clock input

7.10SCE: chip enable

7.11OSC: oscillator

7.12MX: horizontal mirroring

7.13ID3 and ID4: identification inputs

7.14RES: reset

7.15T1, T2, T3, T4, T5 and T6: test pins

8	BLOCK DIAGRAM FUNCTIONS

8.1Oscillator

8.2Serial interface control

8.3Command decoder

8.4Display data RAM (DDRAM)

8.5Timing generator

8.6Address Counter (AC)

8.7Display address counter

8.8VLCD generator

8.9Bias voltage generator

8.10LCD row and column drivers

8.11Reset

9	FUNCTIONAL DESCRIPTION

9.1Reset

9.2Power-down

9.3LCD voltage selector

9.4Oscillator

9.5Timing

9.6Column driver outputs

9.7Row driver outputs

9.8Drive waveforms

9.9Bias system

9.10Voltage multiplier control

9.11Temperature compensation

9.12VLCD generator

10 INITIALIZATION

10.1Initialization sequence

10.2Frame frequency calibration (OC)

11 ADDRESSING

11.1Addressing

11.2Serial interface

11.2.1Write mode

11.2.2Read mode

12 INSTRUCTIONS

12.1Instruction set

13LIMITING VALUES

14HANDLING

15DC CHARACTERISTICS

16AC CHARACTERISTICS

16.1Serial interface timing

16.2Reset timing

17APPLICATION INFORMATION

18MODULE MAKER PROGRAMMING

18.1VLCD calibration

18.2VPR default value

18.3Seal bit

18.4OTP architecture

18.5Serial interface commands

18.5.1Enable OTP

18.5.2CALMM

18.5.3Load factory default

18.5.4Refresh

18.6Example of filling the shift register

18.7Programming flow

18.8Programming specification

19BONDING PAD LOCATIONS

20DEVICE PROTECTION DIAGRAM

21TRAY INFORMATION

22DATA SHEET STATUS

23DEFINITIONS

24DISCLAIMERS

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

1 FEATURES

∙Single-chip LCD controller/driver

∙48 row, 84 column outputs

∙Display data RAM 48 × 84 bits

∙3-line serial interface, maximum 4.0 Mbit/s

∙On-chip:

–Generation of LCD supply voltage VLCD

–Generation of intermediate LCD bias voltages

–Oscillator (requires no external components).

∙CMOS compatible inputs

∙Mux rate 1 : 48

∙Logic supply voltage range VDD1 to VSS:

–1.7 to 2.3 V.

∙Supply voltage range for high voltage part VDD2 to VSS:

–2.5 to 4.5 V.

∙LCD supply voltage range VLCD to VSS:

–4.5 to 9.0 V.

∙Low power consumption (typical 90 μA), suitable for battery operated systems

∙External reset

∙Temperature compensation of VLCD

∙Temperature range: Tamb = −40 to +85 °C

∙Manufactured in N-well silicon gate CMOS process.

4 ORDERING INFORMATION

2 APPLICATIONS

∙ Battery powered telecommunication systems.

3 GENERAL DESCRIPTION

The OM6211 is a low power CMOS LCD row/column driver, designed to drive a dot matrix graphic display of 48 rows and 84 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The OM6211 interfaces to microcontrollers via a 3-line serial interface.

TYPE NUMBER		PACKAGE

	NAME	DESCRIPTION	VERSION
	NAME	DESCRIPTION	VERSION

OM6211U/2/F1	tray	chip with bumps in tray	−

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

5 BLOCK DIAGRAM

	VDD1	VDD2	VDD3	COL0 to COL83	ROW0 to ROW47
VSS1				84	48
VSS2				COLUMN DRIVERS	ROW DRIVERS
				COLUMN DRIVERS	ROW DRIVERS
T4, T5,	3
T4, T5,
T6	3
T1, T2,	3		OM6211		SHIFT REGISTER
T3	2		OM6211
ID3, ID4	2
ID3, ID4
					RESET	RES
MX
		BIAS		DATA LATCHES	OSCILLATOR	OSC
VLCDIN		BIAS			OSCILLATOR	OSC
VLCDIN	VOLTAGE
	GENERATOR
					TIMING
					GENERATOR
VLCDsense				DISPLAY DATA RAM
VLCDsense		VLCD		48 × 84 bits
VLCDOUT		VLCD		48 × 84 bits	DISPLAY
VLCDOUT	GENERATOR				DISPLAY
VOS[4:0]	5				ADDRESS
VOS[4:0]					COUNTER
SCLK	SERIAL INTERFACE			COMMAND	ADDRESS
SDIN	SERIAL INTERFACE			COMMAND	ADDRESS
SDIN		CONTROL		DECODER	COUNTER
SDOUT		CONTROL		DECODER	COUNTER
SDOUT
						MGU272
		SCE

Fig.1 Block diagram.

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

6 PINNING

SYMBOL	PAD	DESCRIPTION

VOS4	3	input pin 4 for VLCD
		calibration

VOS3	4	input pin 3 for VLCD
		calibration

VOS2	5	input pin 2 for VLCD
		calibration

VOS1	6	input pin 1 for VLCD
		calibration

VOS0	7	input pin 0 for VLCD
		calibration

T6	8 to 11	test input 6

	16	external reset input
RES	16	external reset input
		(active LOW)

T5	17	test input 5

T4	18	test input 4

T3	19	test output 3

T2	20	test output 2

T1	21	test output 1

	22	chip enable input
SCE	22	chip enable input
		(active LOW)

VSS2	23 to 30	ground
VSS1	31 to 38	ground
OSC	40	oscillator input

SDOUT	41	serial data output

7 PIN FUNCTIONS

7.1ROW 0 to ROW 47 row driver outputs

These pads output the display row signals.

7.2COL 0 to COL 83 column driver outputs

These pads output the display column signals.

7.3VSS1 and VSS2: negative power supply rails

Negative power supply rails VSS1 and VSS2 must be connected together, hereafter referred to as VSS. When a

pin has to be connected externally to VSS, then pin VSS1 should be used.

7.4VDD1 to VDD3: positive power supply rails

Positive power supply rails: VDD1 for logic supply, VDD2 and VDD3 for voltage multiplier. VDD2 and VDD3 must be connected together, hereafter referred to as VDD2.

SYMBOL	PAD		DESCRIPTION

SDIN	42		serial data input

SCLK	43		serial clock input

ID4	44		module identiﬁcation input

ID3	45		module identiﬁcation input

MX	46		horizontal mirroring input

VDD1	47 to	52	logic supply voltage
VDD2	53 to	60	voltage multiplier supply
			voltage

VDD3	61 to	64	voltage multiplier supply
			voltage

VLCDSENSE	65		VLCD generator regulation
			input

VLCDOUT	66 to	72	VLCD generator output
VLCDIN	73 to	78	LCD supply voltage input
ROW 0 to	89 to 112		LCD row driver outputs
ROW 23

COL 0 to	113 to	196	LCD column driver outputs
COL 83

ROW 47 to	197 to	220	LCD row driver outputs
ROW 24

	1, 12 to 15,		dummy pads
	39, 79,
	81 to	88
	and
	221 to	225

7.5VLCDOUT, VLCDIN and VLCDSENSE: LCD power

supply

If the internal VLCD generator is used, then all three pins must be connected together. If not (VLCD generator is

disabled and an external voltage is applied to VLCDIN), then VLCDOUT must be left open-circuit, VLCDSENSE must be connected to VLCDIN, VDD2 and VDD3 should be applied according to the specified voltage range. The following

settings are also required: HVE = 0, S1 = 1 and S0 = 0.

7.6VOS4 to VOS0: calibration inputs

Five pull-up input pins for on-glass VLCD calibration. Each pin may be connected to VSS, which corresponds to logic 0, or left open-circuit, which corresponds to logic 1. All five pins define a 5-bit two’s complement number ranging from −16 to 15 decimal (from 10000 to 01111). The default value, with all pins connected to VSS, is

0 decimal (00000).

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

In order to reduce current consumption related to the pull-up circuitry, the 5-bit number is stored in a register when exiting the Power-down mode. The pull-up circuitry is then disabled. Additionally, the register is refreshed by each HVE command.

7.7SDIN: serial data input

Serial data input.

7.8SDOUT: serial data output

Serial data output (3-state, push-pull). If bidirectional data transmission is required, SDOUT and SDIN should be connected externally. If the read mode is not used, SDOUT should be left open-circuit.

7.9SCLK: serial clock input

Serial clock input.

7.10SCE: chip enable

Chip enable input, active LOW. If SCE is HIGH, the SCLK pulses are ignored.

7.11OSC: oscillator

External clock input. The external clock is active only in a special test mode, so in the application it is not available. In normal mode (the internal on-chip oscillator used) this input must be connected to VSS. If OSC is held HIGH, the internal oscillator is disabled.

7.12MX: horizontal mirroring

Horizontal mirroring input. When MX = 1 the X address space is mirrored.

7.13ID3 and ID4: identiﬁcation inputs

LCD module identification inputs. Their state can be read out via the serial interface in order to identify the module version.

7.14RES: reset

External reset pin. When LOW the chip will be reset as defined in Section 9.1. The initialization by the RES pin is

always required during power-on. Timing for the RES pin is illustrated in Fig.18.

7.15T1, T2, T3, T4, T5 and T6: test pins

Test pins. In the application T4 and T5 must be connected to VSS. T1, T2, T3 and T6 must be left open-circuit (T6 has a pull-down resistor).

8 BLOCK DIAGRAM FUNCTIONS

8.1Oscillator

The on-chip oscillator provides the clock signal for the display system. It has no external components.

8.2Serial interface control

Detects the serial interface protocol, commands and display data bytes. The serial interface converts the data input (serial-to-parallel) as well as the output bits.

8.3Command decoder

Decodes all commands.

8.4Display Data RAM (DDRAM)

The OM6211 contains a 48 × 84 bit static RAM which stores the display data. The RAM is divided into six banks of 84 bytes (6 × 8 × 84 bits). During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between the X address and column output number.

8.5Timing generator

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations of the serial interface.

8.6Address Counter (AC)

The address counter assigns addresses to the display data RAM for writing. The X address (X6 to X0) and the Y address (Y2 to Y0) are set separately. After a write operation the address counter is automatically incremented by 1.

8.7Display address counter

The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on/off, normal/inverse video) is set via the serial interface.

8.8VLCD generator

A voltage multiplier (charge pump) with a programmable number of stages. Internal capacitors are used for the voltage multiplier, therefore only decoupling capacitors for VLCD and VDD2 are required.

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

8.9Bias voltage generator

Generates 4 intermediate LCD bias voltages. The bias system is selectable; see Section 9.9.

8.10LCD row and column drivers

The OM6211 contains 48 row and 84 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. Figure 3 shows typical waveforms.

8.11Reset

A reset initializes the chip. It can be performed either by the RES pin being LOW or by a command.

9 FUNCTIONAL DESCRIPTION

The OM6211 is a low power LCD driver designed to interface with microprocessors/microcontrollers and a wide variety of LCDs.

The host microprocessor or microcontroller and the OM6211 are connected via a serial interface. The internal oscillator requires no external components. The appropriate intermediate bias voltages for the multiplexed LCD waveforms are generated on-chip. The only other connections required to complete the system are to the

power supplies (VDD1, VDD2, VSS and VLCD) and suitable capacitors for decoupling VLCD and VDD2.

VLCD

VDD2

VDD2, 3

VDD1

84 column drivers

HOST

LCD

MICROPROCESSOR/

OM6211

48 row drivers

PANEL

MICROCONTROLLER

VSS

VSS1, 2

MGU273

RES

SCE

SCLK

SDA

VSS

Fig.2 Typical system configuration.

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

9.1Reset

The OM6211 has no internal Power-on reset, only external reset and reset by command. After power-on an external reset is required. A reset initiated either from the RES pin or by command will initialize the chip to the following starting conditions:

·Power-down mode (DON = 0 and DAL = 1):

–Internal oscillator stopped

–The VLCD generator (HV generator) is switched off (HVE = 0) and VLCDOUT is 3-state

–Display is off and all LCD outputs are internally connected to VSS (DON = 0)

–Display all points is on (DAL = 1).

·Serial interface initialized; write mode

·Display normal video (E = 0)

·Address counter X6 to X0 = 0; Y2 to Y0 = 0; display start line Z5 to Z0 = 0; no Y mirroring (MY = 0)

·Bias system 1¤7 (BS2 to BS0 = 100)

·VLCD selection VPR7 to VPR0 = 0

·Voltage multiplication factor 4 (S1 and S0 = 10)

·Temperature control mode TC3 (TC1 and TC0 = 11)

·Frequency not calibrated and OC = 0

·RAM data is unchanged (after power-up undefined).

9.2Power-down

The chip is in Power-down mode if the display is off (DON = 0) and display all points is on (DAL = 1), regardless of the order in which both bits are set. During the Power-down mode almost all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system), and all LCD outputs are internally connected to VSS. The VLCD generator is switched off (but HVE is not affected). The serial interface function remains. RAM data is unchanged. When exiting the Power-down mode, the VOS value is stored in a register.

9.3LCD voltage selector

The practical value for VLCD is determined by equating

Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10%

contrast.

9.4Oscillator

The internal logic operation and the multi-level drive signals of the OM6211 are clocked by the built-in RC oscillator. No external components are required. The oscillator is in operation as long as the chip is not in Power-down mode.

9.5Timing

The timing of the OM6211 organizes the internal data flow of the device. The timing also generates the LCD frame frequency that is derived from the clock frequency generated by the internal clock generator.

9.6Column driver outputs

The LCD drive section includes 84 column outputs, which should be connected directly to the LCD. The column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. If less than 84 columns are required, the unused column outputs should be left open-circuit.

9.7Row driver outputs

The LCD drive section includes 48 row outputs, which should be connected directly to the LCD. If less than

48 rows are required, the unused row outputs should be left open-circuit.

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

9.8Drive waveforms

VLCD

frame n

frame n + 1

Vstate1(t)

Vstate2(t)

ROW 0

R0 (t)

VSS

VLCD

ROW 1

R1 (t)

VSS

VLCD

COL 0

C0 (t)

VSS

VLCD

COL 1

C1 (t)

VLCD

VSS

V3 − VSS

Vstate1(t)

VLCD − V2

V4 − V5

0 V

V3 − V2

VSS − V5

V4 − VLCD

VLCD

− VLCD

V3 − VSS

Vstate2(t)

VLCD − V2

V4 − V5

0 V

V3 − V2

VSS − V5

V4 − VLCD

− VLCD

0 1 2 3 4 5 6 7 8...

... 47

0 1 2 3 4 5 6 7 8...

... 47

MGU274

Vstate1(t) = C1(t) − R0(t).

Vstate2(t) = C1(t) − R1(t).

Fig.3 Typical LCD driver waveforms.

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

9.9Bias system

The bias voltage levels are set in the ratio of

R - R - nR - R - R. Different multiplex rates require different factors of n. This is programmed by BS2 to BS0. For optimum bias values, n can be calculated from the following equation:

n = Mux rate –3 ; where Mux rate is 48.

Changing the bias system from the optimum setting will have a consequence on the contrast and viewing angle.

One reason to depart from the optimum would be to reduce the required VLCD voltage. A compromise between contrast and VLCD must be found for any particular application.

In the OM6211 one of three possible values of the bias system can be selected. The value 1¤7 is default.

Table 1 Programming the required bias system

BS2	BS1	BS0	n	BIAS MODE	TYPICAL MUX
BS2	BS1	BS0	n	BIAS MODE	RATES
					RATES

0	1	1	4	1¤8	1 : 55 and 1	: 48
1	0	0	3	1¤7	1 : 33
1	0	1	2	1¤6	1 : 24

Table 2 LCD bias voltages for 1¤6 bias, 1¤7 bias and 1¤8 bias.

SYMBOL		BIAS VOLTAGE

	FOR 1¤6 BIAS	FOR 1¤7 BIAS	FOR 1¤8 BIAS
	FOR 1¤6 BIAS	FOR 1¤7 BIAS	FOR 1¤8 BIAS
V1	VLCD	VLCD	VLCD
V2	5¤6VLCD	6¤7VLCD	7¤8VLCD
V3	4¤6VLCD	5¤7VLCD	6¤8VLCD
V4	2¤6VLCD	2¤7VLCD	2¤8VLCD
V5	1¤6VLCD	1¤7VLCD	1¤8VLCD
V6	VSS	VSS	VSS

9.10Voltage multiplier control

The OM6211 incorporates a software configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 4VDD2. Other voltage multiplier factors are set via the serial interface (S1 and S0).

Table 3 HV generator multiplication

S1	S0	MULTIPLICATION
0	0	2VDD2
0	1	3VDD2
1	0	4VDD2
1	1	not available

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

9.11Temperature compensation

Due to the temperature dependency of the liquid crystals viscosity, the LCD controlling voltage (VLCD) must be increased at lower temperatures to maintain optimum contrast. Figure 4 shows VLCD as a function of temperature for a typical high multiplex rate liquid.

In the OM6211 the temperature coefficient of VLCD can be selected from 4 values by setting bits TC1 and TC0, see Tables 4 and 8.

MGT848

VLCD

Fig.4 VLCD as a function of liquid crystal temperature (typical values).

9.12VLCD generator

The binary number VOP representing the operating voltage can be set by the serial interface command and can be

adjusted (calibrated) by 5 input pins according to the
following formula:
VOP = VPR + VOS	(1)

where:

·VPR is an 8-bit unsigned number set by the serial interface command

·VOS is a 5-bit two’s complement number set by the 5 input pins VOS4 to VOS0, see Table 9

·VOP is an 8-bit unsigned number used internally for generation of the LCD supply voltage VLCD.

To avoid numerical overflow the allowed values of VPR should be limited to the range 32 to 225 (decimal).

The corresponding voltage at the reference temperature, Tnom, can be calculated as follows:

VLCD(Tnom) = (a + VOP ´ b)

(2)

The generated voltage at VLCD is dependent on the temperature, programmed Temperature Coefficient (TC)

and the programmed voltage at the reference temperature (Tnom).

VLCD = (a + VOP ´ b) ´ [1 + TC ´ (T –Tnom)]

(3)

Tnom, a and b for each temperature coefficient are given in Table 4. The maximum voltage that can be generated is dependent on the voltage of VDD2 and the display load current.

As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user has to ensure while setting the VPR register and selecting the Temperature Compensation, that under all conditions and including all tolerances the VLCD limit of maximum 9 V will never be exceeded.

For a particular liquid crystal, the optimum value of VLCD can be calculated for a given multiplex rate. For a Mux rate of 1 : 48, the optimum operating voltage of the liquid crystal can be calculated as follows;

VLCD	1 +			48	=	6.06 ´ Vth	(4)
	= --------------------------------------- ´ Vth
	2 ´	æ	1	1 ö
		è		–----------
				48ø

where Vth is the threshold voltage of the liquid crystal used.

2002 Jan 17

Philips Semiconductors					Product speciﬁcation

48 × 84 dot matrix LCD driver						OM6211

Table 4 Typical values for parameters of the HV generator programming

SYMBOL	TC0	TC1	TC2	TC3		UNIT

a	4.57	4.28	4.04	3.79		V

b	30.0	28.0	26.5	25.0		mV

Tnom	27	27	27	27		°C
TC	0	−0.25	−0.5	−0.75		10-3/°C

Example: to achieve VLCD = 8.3 V at temperature Tnom for TC3 it is necessary to set VPR = 180 (decimal).

Example for calibration: Before calibration VPR = 180 was applied, but the measured voltage was VLCD = 8.4 V.

To decrease VLCD by 100 mV the best value for VOS is −4 decimal (11100 binary in the two’s complement notation). So after calibration with VOS = −4 the proper VPR value is still 180.

As VOS is used for calibration and the default value is 0, for selecting the value of VPR it can always be considered that VOS = 0.

handbook, full pagewidth										MGT847
VLCD
	b
a
00	01	02	03	04	05	06 . . .	. . .	FD	FE	FF
										VOP
VOP7 to VOP0 programming, (00H to FFH).

Fig.5 VLCD programming of OM6211.

2002 Jan 17

Philips Semiconductors	Product speciﬁcation

48 × 84 dot matrix LCD driver	OM6211

10 INITIALIZATION

10.1Initialization sequence

After reset (RES) it is recommended to initialize the VLCD generator using the following sequence; a starting state of HVE = 0, DON = 0 and DAL = 1 is assumed:

1.Set the required VOP and, if required, the voltage multiplier S1 and S0

2.Set DAL = 0 to leave the Power-down state (in order to precharge the charge pump VLCD is set to VDD2)

3.Wait for at least 1 ms and set HVE = 1 to switch-on the VLCD generator

4.Set DON = 1 to switch the display on.

10.2Frame frequency calibration (OC)

The OM6211 incorporates frame frequency calibration via software. The calibration is achieved by tuning the internal oscillator. After reset the frame frequency calibration is disabled (OC = 0). The calibration can only be performed if the driver is not in Power-down mode. The calibration is started by setting OC = 1 via the serial interface (start command) and will be stopped by setting OC = 0 (stop command). The time between start and stop of the calibration must be 200 ms to give a frame frequency of 80 Hz. Any variation in calibration time (deviation from 200 ms) results in a corresponding variation in frame frequency. During calibration all other commands are allowed.

The calibration may be repeated and is always performed with the previously calibrated frequency. Through repeated calibrations a better accuracy can be expected and, most especially, the temperature drift can be compensated for. A minimum time delay of 500 ms between consecutive calibration events is necessary (between stop and start).

The calibration will always be performed if the calibration time is between 190 and 210 ms. If, however, the calibration time is lower then 58 ms or higher than 690 ms (or the stop command does not occur at all), the calibration attempt is ignored and the previously selected frequency is maintained. For the remaining values of the calibration time (from 58 to 190 ms and from 210 to 690 ms) it cannot be determined if the calibration will be performed or ignored.

11 ADDRESSING

11.1Addressing

Data is downloaded in bytes into the RAM matrix of OM6211 as illustrated in Figs 6 and 7. The display RAM has a matrix of 48 × 84 bits. The columns are addressed by the address pointer. The address ranges are

X = 0 to 83 (1010011) and Y = 0 to 5 (101). Addresses outside of these ranges are not allowed. The X address increments after each byte (see Fig.7). After the last

X address (X = 83) X wraps around to 0 and Y increments to address the next row. After the very last address (X = 83 and Y = 5) the address pointers wrap around to address X = 0 and Y = 0.

The selection of the MX input allows horizontal mirroring: when MX = 1, the X address space is mirrored (see Fig.6). When MX = 0 the mirroring is disabled. MX affects data only during writing to the RAM, so after a change of MX RAM data must be re-written.

The MY bit allows vertical mirroring: when MY = 1, then the Y address space is mirrored. MY does not affect the RAM content, but defines the way RAM data is written to the display. A change of MY has an immediate effect on the display.

Vertical scrolling of the display is controlled by the Z address with a range from 0 to 47 (101111). The

Z address specifies which rows of the RAM are output to which row outputs. The value of the Z address defines which row of the RAM will be ROW 0 of the display (which is normally the top row of the display). For example, if the Z address is set to 31 (see Fig.8), then the data displayed on ROW 0 of the display will be the data from ROW 31 of the RAM and the data on ROW 1 will be from ROW 32 of the RAM. When the MY is active (MY = 1), then the

Z address defines which row of the RAM is written to ROW 47 of the display. For example, when the Z address is set to 31, ROW 47 of the display would come from ROW 31 of the RAM and ROW 46 from ROW 32 of the RAM (see Fig.9).

The Z address does not affect the RAM content, but defines the way RAM data is written to the display.

A change of Z address has an immediate effect on the display.

2002 Jan 17