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OM6208

65 x 96 pixels matrix grey-scale LCD driver

Product speciﬁcation Supersedes data of 2003 Jan 30

2003 feb 10

Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

CONTENTS

1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION

7.1 I/O buffers and interfaces

7.2 Oscillator

7.3 Address counter

7.4 Display data RAM

7.5 Display address counter

7.6 Timing generator

7.7 Data processing

7.8 High voltage generator

7.9 Bias voltage generator

7.10 Command decoder

7.11 Orthogonal function generator

7.12 Reset

7.13 Row drivers and column drivers 8 RAM ADDRESSING

8.1 Display data RAM structure

8.1.1 Horizontal/vertical addressing

8.1.2 Mirror Y

8.1.3 Mirror X 9 SERIAL INTERFACING

9.1 Serial peripheral interface

9.1.1 Write mode

9.1.2 Read mode

9.2 Serial interface (3-line)

9.2.1 Write mode

9.2.2 Read mode

9.2.3 Read data format 10 I2C-BUS INTERFACE

10.1 Characteristics of the I2C-bus (Hs-mode)

10.1.1 System configuration

10.1.2 Bit transfer

10.1.3 Start and stop conditions

10.1.4 Acknowledge

10.2 I2C-bus Hs-mode protocol

10.3 Command decoder

10.4 Read mode 11 INSTRUCTIONS

11.1 Description of command bits

11.2 Frame frequency setting and oscillator tuning

11.3 Initialization

11.4 Reset function

11.5 Power-down mode

11.6 Display Control

11.6.1 Horizontal mirroring

11.6.2 Vertical mirroring

11.7 Set Y address of RAM

11.8 Set X address of RAM

11.9 Bias levels

11.10 LCD drive voltage

11.10.1 LCD drive voltage generation

11.10.2 Temperature measurement

11.10.3 Temperature compensation

11.11 Grey-scale mode and black-and-white mode

11.12 N-line inversion and frame inversion 12 LIMITING VALUES 13 HANDLING 14 DC CHARACTERISTICS 15 AC CHARACTERISTICS 16 APPLICATION INFORMATION

16.1 Protection from light

16.2 Chip-on-glass displays

16.3 Application examples 17 MODULE MAKER PROGRAMMING

17.1 V

17.2 Factory defaults

17.2.1 Configuration derived from OTP cells

17.2.2 Defaults from interface registers

17.3 Seal bit

17.4 OTP architecture

17.4.1 OTP operational effects

17.5 Interface commands

17.5.1 CALMM instruction

17.5.2 Refresh instruction

17.6 Example of filling the shift register

17.7 Programming flow

17.8 Programming specification 18 DEVICE PROTECTION DIAGRAM 19 BONDING PAD INFORMATION 20 TRAY INFORMATION 21 DATA SHEET STATUS 22 DEFINITIONS 23 DISCLAIMERS 24 PURCHASE OF PHILIPS I2C COMPONENTS

calibration

LCD

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

1 FEATURES

• Single chip LCD Multiple Row Addressing (MRA) grey-scale/colour controller/driver

• Four grey levels/colours

• 65 row outputs and 96 column outputs

• Display Data RAM (DDRAM) 65 × 96 × 2 bits

• Selectable interface:

– 6.5 MHz 3-line or 4-line Serial Peripheral

Interface (SPI) – 6.5 MHz 3-line serial interface – High speed I2C-bus interface.

• On-chip: – Configurable voltage multiplier generating V

external V

– Four-segment V

also possible

LCD

temperature compensation

LCD

;

– Generation of intermediate LCD bias voltage – Oscillator requires noexternal components; external

clock input also possible

– Integrated charge pump capacitors (reducing total

system cost).

• External reset input

• Temperature read-back

• Selectable N-line inversion and frame inversion

• CMOS compatible inputs

• Logic supply voltage range 1.7 to 3.3 V

• High-voltage generator supply voltage range

2.4 to 4.5 V

• Display supply voltage range 5 to 9 V

• Low power consumption; suitable for battery operated

systems

• Programmable row pad mirroring for compatibility with Tape Carrier Packages (TCP) and with Chip-On Glass (COG) applications

• Status read which allows chip recognition

• Start address line; for example, for scrolling the

displayed image

• Slim chip layout; suitable for COG, COF and TCP applications

• Operating temperature range −40 to +85 °C.

2 APPLICATIONS

• Telecom equipment

• Portable instruments

• Point of sale terminals.

3 GENERAL DESCRIPTION

The OM6208 is a low power CMOS LCD controller driver, designed to drive a graphic display of 65 rows and 96 columns. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD supply and bias voltages, resulting in a minimum of external components and low power consumption. The OM6208 can be interfaced to microcontrollers via a serial bus and I2C-bus.

The OM6208 is manufactured in n-well CMOS technology. Operation is with the substrate at VSS potential.

4 ORDERING INFORMATION

PACKAGE

TYPE NUMBER

NAME DESCRIPTION VERSION

OM6208MU/2DA/1 − chip with bumps in tray −

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

5 BLOCK DIAGRAM

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LCDIN

OTPPROG

LCDSENSE

LCDOUT

V V V

V V

DD1 DD2 DD3

SS1 SS2

T1 T2 T3 T4 T5 T6 T7 T8

BIAS

VOLTAGE

GENERATOR

HIGH

VOLTAGE

GENERATOR

C0 to C95

COLUMN DRIVERS

DATA PROCESSING

DISPLAY DATA RAM

(DDRAM)

[65 × 96] × 2

ADDRESS COUNTER

COMMAND

DECODER

I/O BUFFERS and INTERFACES

OM6208

R0 to R64

ROW DRIVERS

ORTHOGONAL

FUNCTION

GENERATOR

RESET

OSCILLATOR

TIMING

GENERATOR

DISPLAY

ADDRESS

COUNTER

RES

OSC

ID3/SA0; ID4/SA1

] 1:0

[ PS

D/C

Fig.1 Block diagram.

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SCLH/SCE

SCLK

SDATA

SDO

MGW821

SDAH

SDAHOUT

Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

6 PINNING

SYMBOL PAD

LCDIN

LCDOUT

LCDSENSE

DD2

DD3

(1)

DESCRIPTION

5 to 8 LCD supply voltage input; note 2

9 to 15 LCD supply voltage output from high voltage generator; note 2

16 regulation input to high voltage generator; note 2 17 to 26 supply voltage 2; note 3 27 to 29 supply voltage 3; note 3

OSC 30 oscillator input; note 4 D/

C 31 data/command input/output; note 5 PS[1:0] 32 and 33 interface selection inputs V

DD1

SDAHOUT 44 I

34 to 39 supply voltage 1; note 3

C-bus data output; note 6

SCLK 46 serial data clock input; used in 3-line or 4-line SPI or 3-line serial interface

mode SDAH 52 I2C-bus data input; note 7 SDO 53 serial data output; note 8 SDATA 54 serial data input; note 9 V

SS2

SS1

55 to 61 ground 2 (analog ground); note 10

62 to 67 ground 1 (digital ground); note 10 MX 68 horizontal mirroring input T3 69 test outputs; note 11 T4 70 T1 71 T2 72 T5 73 T6 74

ID3/SA0; ID4/SA1 75 and 76 manufacturer device identiﬁcation/I V

DD1

SCE 83 I2C-bus clock input/serial chip enable input in 3-line or 4-line SPI mode; note 5

SCLH/ V

OTPPROG

77 supply voltage 1 (tie-off pad)

84 to 86 supply voltage input for OTP programming; note 13

C-bus slave address input pads; note 12

RES 88 external reset input; active low; must be applied to initialize the chip properly R32 to R64 105 to 137 LCD row driver outputs V

138 bias buffer output; note 14 T8 141 test outputs; note 11 T7 142 V

143 bias buffer output; note 14 C95 to C48 144 to 191 LCD column driver outputs C47 to C0 194 to 241 R31 to R0 247 to 278 LCD row driver outputs V

244 bias buffer outputs; note 14

245

246

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

Notes

1. Dummy pads are located at positions 1, 2, 4, 40 to 43, 45, 47 to 51, 78 to 82, 87, 89 to 92, 95 to 104, 139, 140, 192, 193, 242, 243, 279 and 280; alignment marks are located at positions 3 and 93; an alignment bump is located at position 94.

2. Positive power supply for the liquid crystal display (see also Figs 38, 39 and 40): a) If the internal voltage generator is used, pads V

LCDIN,VLCDSENSE

b) An external LCD supply voltage can be incorporated using the V

then switched off, pad V connected to the V

LCDIN

LCDOUT

input; V

must be open-circuit (not connected to pad V

should be applied according to the specified voltage range. In Power-down

DD2,3

mode, the external LCD supply voltage must be switched off.

3. V

DD2

and V

supply the internal voltage generator, both have the same voltage and may be connected together

DD3

outside of the chip; V

supplies the remainder of the chip. V

DD1

then care must be taken with respect to the supply voltage range.

4. When the on-chip oscillator is used, the OSC input must be connected to V then this is connected to the OSC input. If both the oscillator and external clock are inhibited by connecting pad OSC to V

, the display is not clocked and may be in a DC state. To avoid this, the chip should always be put into

SS1

Power-down mode before stopping the clock.

5. This input is not used with the 3-line serial interface and must be connected to V use.

6. SDAHOUT is the serial data acknowledge output from the I2C-bus interface. By connecting SDAHOUT to SDAH externally, the SDAH line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in COG applications because here the track resistance from the SDAHOUT pad to the system SDAH line can be significant and a potential divider can be generated by the bus pull-up resistor and the ITO track resistance. It is possible that during the acknowledge cycle the OM6208 will not be able to create a valid logic 0. By splitting the SDAH input from the SDAHOUT output the device could be used in a mode that ignores the acknowledgebit.ThereforeinCOGapplicationswheretheacknowledgecycleis required, it is necessary to minimize the track resistance from the SDAHOUT pad to the system SDAH line to guarantee a valid logic 0. When SDAHOUT is not used, it must be connected to V

7. When I2C-bus is not used, this pad must be connected to V

DD1

or V

SS1

DD1

8. SDO is a push-pull output; when it is intended to use the readback function of the OM6208, this pad must be connected to the SDATA pad, or used separately; when I2C-bus interface is selected, this pad should be connected to V

DD1

or V

SS1

9. When I2C-bus interface is selected this pin should be connected to V

10. Supply rails V

SS1

and V

must be connected together.

SS2

11. Test padsT1 to T8arenotaccessibletousers:T1, T2, T5 and T6 must be connected to VSS; T3,T4,T7and T8 must be open-circuit.

12. Module identification bits: these bits may be read back via the ‘read back’ instruction; when the I2C-bus interface is being used, these bits are the two LSBs of the slave address.

13. V

OTPROG

configuration, then V

can be connected to SCLH/SCE pad to reduce the external connections. If not connected in this

OTPROG

should be open-circuit during normal operation.

14. These pads are not accessible to users and must be left open-circuit; an explanation of the bias buffer function is given in Section 11.9.

DD1

or V

, V

and V

pad; the internal voltage generator must

LCDIN

and V

DD2

SS1

or V

DD1

must be connected together.

LCDOUT

) and pad V

LCDIN

can be connected together but

DD3

. If an external clock signal is used,

DD1

or V

SS1

DD1

SS1

LCDSENSE

when this interface is in

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

7 FUNCTIONAL DESCRIPTION

7.1 I/O buffers and interfaces

One of four industrial standard interfaces can be selected using the interface configuration inputs PS1 and PS0.

Table 1 Serial/I

C-bus interface selection

PS1 PS0 SELECTED INTERFACE

0 0 3-line SPI 0 1 4-line SPI 10I

C-bus interface

1 1 3-line serial interface

7.2 Oscillator

The on-chip oscillator provides the clock signal for the display system. No external components are required when the internal oscillator is used. An external clock signal, if used, is connected to this input.

7.3 Address counter

The Address Counter (AC) assigns addresses to the displaydataRAMforwriting. The X address X[6:0] and the Y address Y[4:0] are set separately.

7.6 Timing generator

The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data bus.

7.7 Data processing

The data processing block receives data from the RAM and the orthogonal function from the logic circuits, then selects the correct voltage level to be provided to the columns.

7.8 High voltage generator

The high voltage generator provides the programmed V

to the bias voltage generator block.

LCD

7.9 Bias voltage generator

Thebiasvoltagegeneratorgeneratesallthevoltagelevels required for the MRA driving system.

7.10 Command decoder

The command decoder identifies command words arriving at the interface and routes the data bytes that follow to their destination.

7.4 Display data RAM

The OM6208 contains a 65 × 96 × 2 bit static RAM which stores the display data. The display data RAM is divided into 17 banks of 96 bytes, although only two bits of the 17th bank are used. During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between X address and column output number.

7.5 Display address counter

The display is generated by simultaneously reading out the RAM content for two or four rows, depending on the current display size that is selected. This content will be processed with the corresponding set of two or four orthogonal functions and so generate the signals for switchingthepixelsofthedisplayonoroff according to the RAM content.

The display status (all dots on/all dots off and normal/inverse video) is set by the bits DON, DAL and E in the command Display control (see Table 8).

7.11 Orthogonal function generator

The orthogonal function generator generates a set of orthogonal functions suitable for the selected value of p (number of active rows).

7.12 Reset

The reset block handles the hardware reset input (RES) andsoftware reset and provides all internal blocks with the required reset signal.

7.13 Row drivers and column drivers

The OM6208 contains 65 row and 96 column drivers which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. A typical MRA driving scheme with waveforms for p = 4 is shown in Fig.2. The value of p represents the number of simultaneously selected rows.

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65 x 96 pixels matrix grey-scale LCD driver OM6208

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F1(t)

F2(t)

F3(t)

F4(t)

G1(t)

F1(t)

col(max)

col(min)

G1(t)

G1(t) = C [+ F1(t) − F2(t) − F3(t) + F4(t)

G1(t)

G2(t) G3(t)

]

F2(t)

F3(t)

F4(t)

col(max)

G1(t)

col(min)

Fig.2 Typical MRA LCD driver waveforms for p = 4.

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G1(t) = C [− F1(t) − F2(t) − F3(t) + F4(t)

MGW822

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

8 RAM ADDRESSING

Data is downloaded in bytes into the RAM matrix of the OM6208 as indicated in Fig.3. The display RAM has a matrix of 65 × 96 × 2 bits. The columns are addressed by the address pointer. The address ranges (decimal values)

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DOR = 1

LSB

MSB

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

P0 MSB

P0 LSB

P1 MSB

P1 LSB

P2 MSB

P2 LSB

P3 MSB

P3 LSB

P0 P1 P2 P3

bank 0

P1 P2 P3

bank 1

bank 2

bank 3

DOR = 0

LSB

MSB

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

P3 LSB

P3 MSB

P2 LSB

P2 MSB

P1 LSB

P1 MSB

P0 LSB

P0 MSB

. .

bank 13

bank 14

bank 15

X X X

bank 16

X X X

areX=0to95andY=0to16.TheYaddressrepresents the bank number. Addresses outside these ranges are not allowed.

The Data Order Bit (DOR) defines the bit order (LSB on top or MSB on top) for writing into the RAM.

LSB

MSB

top of LCD

R12

. . .

. .

LCD

R16

R52

R56

R60

R64

Fig.3 DDRAM-to-display mapping.

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

8.1 Display data RAM structure

The mode for storing data in the display data RAM is dependent on:

• Horizontal/vertical addressing mode set by bit V in the

‘RAM addressing mode’ instruction

• Data order set by bit DOR in the ‘data order’ instruction

• Mirror the X-axis set by input MX.

8.1.1 HORIZONTAL/VERTICAL ADDRESSING

Two different addressing modes are possible; horizontal addressing mode and vertical addressing mode.

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192 193 288 289 384

98 194 290 386385

In the horizontal addressing mode (V = 0) the X address increments after each byte. After the last X address (X = 95), X wraps around to 0 and Y increments to address the next row (see Fig.4).

In the vertical addressing mode (V = 1), the Y address increments after each byte. After the last Y address (Y = 16), Y wraps around to 0 and X increments to address the next column (see Fig.5).

After the very last address, the address pointers wrap around to address X = 0 and Y = 0 in both horizontal and vertical addressing modes.

19196 97

Y address

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1440

1441 1442

1536

1537

0 95X address

1535

161631

MGW824

Fig.4 Sequence of writing data bytes into RAM with horizontal addressing (V = 0).

017 118 219 320 421 522

16 33

0 95X address

Y address

161631

MGW825

Fig.5 Sequence of writing data bytes into the RAM with vertical addressing (V = 1).

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

8.1.2 MIRROR Y The Mirror Y (MY) bit allows vertical mirroring:

• When MY = 1, the Y address space is mirrored; the address Y = 0 is then located at the bottom of the display (see Fig.6)

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0 95X address

• When MY = 0, the mirroring is disabled and the address Y = 0 is located at top of the display (see Fig.7).

Refer also to Section 11.6.

Y address

MGW826

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Fig.6 RAM format addressing (MY = 1).

0 95X address

Y address

Fig.7 RAM format addressing (MY = 0).

MGW827

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

8.1.3 MIRROR X The Mirror X (MX) input allows a horizontal mirroring:

• When MX = 1, the X address space is mirrored; the address X = 0 is then located at the right side (X

max

the display (see Fig.8)

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95 0X address

) of

Y address

• When MX = 0, the mirroring is disabled and the address X = 0 is located at the left side (column 0) of the display (see Fig.9).

Refer also to Section 11.6.

MGW828

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Fig.8 RAM format addressing (MX = 1).

0 95X address

Y address

Fig.9 RAM format addressing (MX = 0).

MGW829

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

9 SERIAL INTERFACING

Communication with the microcontroller can occur via a clock-synchronized serial peripheral interface. It is possible to select two different 3-line (SPI and serial interface) or a 4-line SPI interface. Selection is done via the PS[1:0] inputs.

9.1 Serial peripheral interface

The Serial Peripheral Interface (SPI) is a 3-line or 4-line interface for communication between the microcontroller and the LCD driver chip. Three lines are common to both 3-line and 4-line SPI, these are SCE (chip enable), SCLK (serial clock) and SDATA (serial data). For the 4-line SPI a separate D/C line is added. The OM6208 is connected to the serial data I/O of the microcontroller by pads SDATA (data input) and SDO (data output) connected together.

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SCE

9.1.1 WRITE MODE

The display data/command indication may be controlled by software or by the D/C select pin. When the D/C pad is used, display data is transmitted when D/C is HIGH, and command data is transmitted when D/C is LOW (see Figs 10 and 11). When D/C is not used, the ‘display data length’instructionis used toindicatethata specific number of display data bytes (1 to 255) are to be transmitted (see Fig.11). The next byte after the display data string is handled as an instruction command.

When the 3-line SPI interface is used the display data/command is controlled by software (see Fig.12).

If SCE is pulled high during a serial display data stream, the interrupted byte is invalid data but all previously transmitted data is valid. The next byte received will be handled as an instruction command (see Fig.13).

D/C

SCLK

SDATA

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Fig.10 4-line SPI bus protocol; transmission of one byte.

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SCE

D/C

SCLK

SDATA DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MGW744

DB6 DB5

MGW745

Fig.11 4-line SPI bus protocol; transmission of several bytes.

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65 x 96 pixels matrix grey-scale LCD driver OM6208

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SCE

SCLK

SDATA DB7 DB6 DB5 DB4

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SCE

SCLK

SDATA

datadata data data data data

display data string

Fig.13 3-line SPI bus protocol: transmission interrupted by SCE.

DB2 DB1 DB0 DB2

display length instruction

and length data (two bytes)

data data

last

DB7 DB6 DB5 DB4 DB3 DB1 DB0

data

Fig.12 3-line SPI bus protocol; transmission of several bytes.

instruction

instructiondisplay data string

DB7DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB6 DB5 DB4

MGW746

MGW747

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

9.1.2 READ MODE The read mode of the interface means that the

microcontroller reads data from the OM6208. To do so the microcontroller first has to send a command, the read status command, and then OM6208 will respond by transmitting data on the SDO line. After that, SCE is required to go HIGH (see Fig.14).

The OM6208 samples the SDATA data at rising SCLK edges, but shifts SDO data at falling SCLK edges. Thus

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SCE

RES

SCLK

SDATA DB7 DB6 DB5 DB4 DB2DB3 DB1 DB0

the SDO data is available to be read by the microcontroller at rising SCLK edges.

After the read status command has been sent, the SDATA line must be set to 3-state (high-impedance) not later than at the falling SCLK edge of the last bit (see Fig.14).

For the read data format, see Section 9.2.3; the serial interface timing diagram is given in Chapter 15.

SDO

instruction

read out data

Fig.14 Read mode SPI 3- and 4-line interfaces.

DB2DB7 DB6 DB5 DB4 DB3 DB1 DB0

MGU629

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

9.2 Serial interface (3-line)

The serial interface is also a 3-line bidirectional interface for communication between the microcontroller and the LCD driver chip. The three lines are SCE (chip enable), SCLK(serialclock) and SDATA (serialdata).TheOM6208 is connected to the SDA of the microcontroller by the SDATA(datainput)andSDO (data output) pads which are connected together.

9.2.1 WRITE MODE The write mode of the interface means that the

microcontroller writes instructions and data to the OM6208. Each data packet contains a control bit D/C and a transmission byte. If D/C is LOW, the following byte is interpreted as command byte. The instruction set is given in Table 7. If D/C is HIGH, the following byte is stored in the display data RAM. After every data byte the address counter is incremented automatically. The general format of the write mode and the definition of the transmission byte is shown in Fig.15.

Any instruction can be sent in any order to the OM6208. The MSB is transmitted first. The serial interface is initialized when SCE is HIGH. In this state, SCLK clock

pulses have no effect and no power is consumed by the serial interface. A falling edge on SCE enables the serial interface and indicates the start of data transmission.

Figures 16, 17 and 18 show the protocol of the write mode:

• When SCE is HIGH, SCLK clocks are ignored. During the HIGH time of SCE the serial interface is initialized (see Fig.16)

• At the falling SCE edge, SCLK must be LOW (see Fig.32)

• SDATA is sampled at the rising edge of SCLK

• D/C indicates whether the byte is a command (D/C=0)

or RAM data (D/C = 1) byte; it is sampled with the first rising SCLK edge

• If SCE stays LOW after the last bit of a command/data byte, the serial interface is ready for the D/C bit of the next byte at the next rising edge of SCLK (see Fig.17)

• A reset pulse with RES interrupts the transmission. The data being written into the RAM may be corrupted. The registers are cleared. If SCE is LOW after the rising edge of RES, the serial interface is ready to receive the D/C bit of a command/data byte (see Fig.18).

D/C

(1)

transmission byte

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D7 D6 D5 D4 D3 D2 D1 D0

D/C

MSB LSB

D/C

(1) A transmission byte may be a command byte or a data byte.

transmission byte

Fig.15 Serial data stream, write mode.

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D/C

transmission byte

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65 x 96 pixels matrix grey-scale LCD driver OM6208

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SCE

SCLK

SDATA

D/C

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Fig.16 Write mode: a control bit followed by a transmission byte.

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SCE

SCLK

SDATA DB7D/C DB6 DB5 DB4 DB3 DB2

DB1 DB0

MGU630

DB7D/C DB6 DB5 DB4 DB3 DB2 DB1 DB0 D/C

transmission byte

Fig.17 Write mode: transmission of several bytes.

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SCE

RES

SCLK

SDATA DB7D/C DB6 DB5 DB4 DB7DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Fig.18 Write mode: interrupted by reset (RES).

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MGU631

DB6D/C D/C

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Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

9.2.2 READ MODE

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SCE

SCLK

SDATA

SDO

DB7D/C DB6 DB5 DB4

DB3 DB2 DB1 DB0

Fig.19 Read mode serial interface 3-line.

The read mode of the interface means that the microcontroller reads data from the OM6208. To do so the microcontroller first has to send a command, the read statuscommand,and then the followingbyteistransmitted in the opposite direction using SDO (see Fig.19). After that, SCE is required to go HIGH before a new command is sent.

The OM6208 samples the SDATA data at rising SCLK edges and shifts SDO data at falling SCLK edges. Thus the SDO data is available for the microcontroller to read at rising SCLK edges.

After the read status command has been sent, the SDATA linemustbe set to 3-state not later then at the falling SCLK edge of the last bit (see Fig.19).

D/C

DB7 DB6 DB5 DB4 DB3 DB2 DB1

DB0

MCE176

The 8th read bit is shorter than the others because it is terminated by the rising SCLK edge (see Fig.35). The last rising SCLK edge sets SDO to 3-state after the delay time t4.

9.2.3 READ DATA FORMAT

Regardless of which serial interface is used there are five bits that can be read (ID1 to ID4 and VM) and one temperatureregister.For the bits, one bit istransmittedper byte read and is selected by issuing the appropriate read instruction from the instruction set. Bits ID1 and ID2 are hard-wired so that ID1 always returns a logic 0 and ID2 always returns a logic 1. Bits ID3 and ID4 are the identification bits and are set via ID3/SA0 and ID4/SA1 pads. The format for the read bit, B, is shown in Table 2.

Table 2 Read data format

D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)

(1)

BBBBBBB

Note

1. x = undefined.

Table 3 Read temperature sensor Sending the instruction to read back the temperature sensor data will select the following status byte.

D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB)

(1)

TD[6] TD[5] TD[4] TD[3] TD[2] TD[1] TD[0]

Note

1. x = undefined.

2003 feb 10 18

Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

10 I2C-BUS INTERFACE

10.1 Characteristics of the I

C-bus (Hs-mode)

The I2C-bus Hs-mode is for bidirectional, two-line communication between different ICs or modules with speeds up to 3.4 MHz. The only difference between Hs-modeslavedevicesandF/S-modeslavedevicesisthe speed at which they operate, therefore the buffers on the SDAH output have an open drain. This is the same for

C-bus master devices which have an open-drain SDAH

I output and a combination of an open-drain pull-down and current source pull-up circuits on the SCLH output. Only the current source of one master is enabled at any one time and only during Hs-mode. Both lines must be connected to a positive supply via a pull-up resistor.

Data transfer may be initiated only when the bus is not busy.

SDA SCL

MASTER

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

TRANSMITTER/

RECEIVER

10.1.1 S

YSTEM CONFIGURATION

Definition (see Fig.20):

• Transmitter: the device that sends the data to the bus

• Receiver: the device that receives the data from the bus

• Master: the device that initiates a transfer, generates

clock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-master: more than one master can attempt to

control the bus at the same time without corrupting the message

• Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted

• Synchronisation: procedure to synchronize the clock signals of two or more devices.

SLAVE

MASTER

TRANSMITTER

MASTER

TRANSMITTER/

RECEIVER

MGA807

Fig.20 System configuration.

10.1.2 BIT TRANSFER One data bit is transferred during each clock pulse (see

Fig.21). The data on the SDAH line must remain stable

handbook, full pagewidth

SDA

SCL

data line

stable;

data valid

Fig.21 Bit transfer.

2003 feb 10 19

during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal.

change

of data

allowed

MBC621

Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

10.1.3 START AND STOP CONDITIONS BothdataandclocklinesremainHIGHwhenthe bus is not

busy (see Fig.22). A HIGH-to-LOW transition of the data

handbook, full pagewidth

SDA

SCL

START condition

Fig.22 Definition of START and STOP conditions.

10.1.4 ACKNOWLEDGE Each byte of 8 bits is followed by an acknowledge bit (see

Fig.23). The acknowledge bit is a HIGH signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the

line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P).

SDA

STOP condition

SCL

MBC622

slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

handbook, full pagewidth

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

START

condition

Fig.23 Acknowledge on the I2C-bus.

2003 feb 10 20

not acknowledge

acknowledge

acknowledgement

9821

clock pulse for

MBC602

Philips Semiconductors Product speciﬁcation

65 x 96 pixels matrix grey-scale LCD driver OM6208

10.2 I2C-bus Hs-mode protocol

TheOM6208 is a slave receiver/transmitter. If data is to be read from the device the SDAHOUT and SDAH pads must be connected for acknowledge to be used (see Table 1, note 6).

Hs-mode can only commence after the following conditions.

• START condition (S)

• 8-bit master code (00001XXX)

• not-acknowledge bit (A).

The master code has two functions as shown in Figs 24 and 25, it allows arbitration and synchronization between competing masters at F/S-mode speeds, resulting in one winner.Also the master code indicates the beginning of an Hs-mode transfer.

As no device is allowed to acknowledge the master code, then a master code transmission must be followed by a not-acknowledge (A). After this A bit, and the SCLH line has been pulled up to a HIGH level, the active master switches to Hs-mode and enables at tHthe current-source pull-up circuit for the SCLH signal (see Fig.25).

The active master will then send a repeated START condition (Sr) followed by a 7-bit slave address with a

W bit, and receives an acknowledge bit (A) from the

selected slave. After each acknowledge bit (A) or not-acknowledge bit (A) the active master disables its current-source pull-up circuit. The active master re-enables its current source again when all devices have released and the SCLH signal reaches a HIGH level. The rising of the SCLH is done by a resistor pull-up and so is slower, the last part of the SCLH rise time is speeded up because the current source is enabled. Data transfer only switches back to F/S-mode after a STOP (P) condition.

The write sequence that occurs after the Hs-mode is selected is shown in Fig.26. The sequence is initiated with a START (S) condition from the I2C-bus master which is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all the others will ignore the I2C-bus transfer.

After an acknowledgement cycle of a write (W), one or morecommandwordsfollowwhichdefinethestatusofthe addressed slaves. A command word consists of a control byte, which defines Co and D/C, plus a data byte (see Fig.26 and Table 4).

The last control byte is tagged with a cleared most significantbit,the continuation bit Co. Thecontrolanddata bytes are also acknowledged by all addressed slaves on the bus.

Table 4 Co and Sr deﬁnition

Co D/C R/W ACTION

0 −−

1 −−

− 0

− 1

Afterthelast control byte, dependingontheD/C bit setting, a series of display data bytes or command data bytes may follow. If the Sr bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. The data pointer is automatically updated and the data is directed to the intended OM6208 device. If the Sr bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed OM6208. At the end of the

last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a STOP or repeated START condition

another control byte will follow the data byte unless a STOP or repeated START condition

is received 0 data byte will be decoded and used to set up the device 1 data byte will return the status byte 0 data byte will be stored in the display RAM 1 RAM read back is not supported

transmission the I2C-bus master issues a STOP condition (P) and switches back to F/S-mode, however, to reduce the overhead of the master code, it i s possible that a master links a number of Hs-mode transfers, separated by repeated START conditions (Sr).

A read sequence (see Fig.27) follows after the Hs-mode is selected. The OM6208 will immediately start to output the requested data until a not acknowledge is transmitted by the master. The write access should be terminated by a repeated START condition so that the Hs-mode is not disabled.

2003 feb 10 21

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