Philips Semiconductors Linear Products |
Product specification |
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Addressable relay driver |
NE/SA5090 |
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DESCRIPTION
The NE/SA5090 addressable relay driver is a high-current latched driver, similar in function to the 9934 address decoder. The device has 8 open-collector Darlington power outputs, each capable of 150mA load current. The outputs are turned on or off by respectively loading a logic ª1º or logic ª0º into the device data input. The required output is defined by a 3-bit address. The device must be
enabled by a CE input line which also serves the function of further address decoding. A common clear input, CLR, turns all outputs off when a logic ª0º is applied. The device is packaged in a 16-pin plastic or Cerdip package.
FEATURES
•8 high-current outputs
•Low-loading bus-compatible inputs
•Power-on clear ensures safe operation
•Will operate in addressable or demultiplex mode
•Allows random (addressed) data entry
•Easily expandable
•Pin-compatible with 9334 (Siliconix or Fairchild)
PIN CONFIGURATION
D1, N Packages
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A0 |
1 |
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16 |
VCC |
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A1 |
2 |
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15 |
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CLR |
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A2 |
3 |
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14 |
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CE |
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Q0 |
4 |
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13 |
D |
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Q1 |
5 |
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12 |
Q7 |
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Q2 |
6 |
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11 |
Q6 |
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Q3 |
7 |
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10 |
Q5 |
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GND |
8 |
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9 |
Q4 |
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TOP VIEW
NOTE:
1. SOL - Released in Large SO package only.
APPLICATIONS
•Relay driver
•Indicator lamp driver
•Triac trigger
•LED display digit driver
•Stepper motor driver
BLOCK DIAGRAM
CLR |
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LATCH |
Q0 |
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CE |
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LATCH |
Q1 |
A0 |
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LATCH |
Q2 |
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A1 |
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LATCH |
Q3 |
1±OF±8 |
CONTROL |
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DECODER |
GATE |
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LATCH |
Q4 |
A2 |
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LATCH |
Q5 |
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D |
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LATCH |
Q6 |
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LATCH |
Q7 |
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INPUT STAGE |
OUTPUT STAGE |
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VCC
August 31, 1994 |
512 |
853-0892 13721 |
Philips Semiconductors Linear Products |
Product specification |
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Addressable relay driver |
NE/SA5090 |
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PIN DESIGNATION
PIN NO. |
SYMBOL |
NAME AND FUNCTION |
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1-3 |
A0-A2 |
A 3-bit binary address on these pins defines which of the 8 output latches is to receive the data. |
4-7, 9-12 |
Q0-Q7 |
The 8 device outputs. |
13 |
D |
The data input. When the chip is enabled, this data bit is transferred to the defined output such that: |
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ª1º turns output switch ªONº |
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ª0º turns output switch ªOFFº |
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14 |
CE |
The chip enable. When this input is low, the output latches will accept data. When CE goes high, all |
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outputs will retain their existing state, regardless of address of data input condition. |
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15 |
CLR |
The clear input. When CLR goes low all output switches are turned ªOFFº. The high data input will |
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override the clear function on the addressed latch. |
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ORDERING INFORMATION
DESCRIPTION |
TEMPERATURE RANGE |
ORDER CODE |
DWG # |
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16-Pin Plastic Small Outline Large (SOL) Package |
0 to +70°C |
NE5090D |
0171B |
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16-Pin Plastic Dual In-Line Package (DIP) |
0 to +70°C |
NE5090N |
0406C |
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16-Pin Plastic Dual In-Line Package (DIP) |
-40 to +85°C |
SA5090N |
0406C |
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16-Pin Plastic Small Outline Large (SOL) Package |
±40 to +85°C |
SA5090D |
0171B |
TRUTH TABLE
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INPUTS |
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OUTPUTS |
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MODE |
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D A A A |
Q Q Q Q Q Q Q Q |
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CL |
C |
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R |
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E |
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0 |
1 |
2 |
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
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L |
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H |
X |
X |
X |
X |
H |
H |
H |
H |
H |
H |
H |
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H |
Clear |
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L L L L L L |
H |
H H H H H H H |
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L L H L |
L L |
L |
H H H H H H H |
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L |
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L |
L |
H |
L |
L |
H |
H |
H |
H |
H |
H |
H |
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H |
Demultiplex |
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L L H |
H L L |
H L H H H H H H |
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L L L |
H H H |
H H H H H H H H |
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L L H H H H |
H H H H H H H L |
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H |
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H |
X |
X |
X |
X |
QN-1 |
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Memory |
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H L L L L L |
H QN-1 |
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H L H L |
L L |
L QN-1 |
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H |
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L |
L |
H |
L |
L |
QN-1 |
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H QN- |
1 |
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Addressable Latch |
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H L H |
H L L |
QN-1 L QN-1 |
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H L L |
H H H |
QN-1 |
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H |
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H L H H H H |
QN-1 |
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L |
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NOTES:
X=Don't care condition
QN-1=Previous output state
L=Low voltage level/ªONº output state
H=High voltage level/ªOFFº output state
August 31, 1994 |
513 |
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