Philips N74F241AD, N74F240AD, N74F241N, N74F241D, N74F241AN Datasheet
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INTEGRATED CIRCUITS
74F240/74F240A
Octal inverter buffer (3-State)
74F241/74F241A
Octal buffer (3-State)
Product specification
IC15 Data Handbook
1001 Jan 02
Philips Semiconductors Product specification
Buffers
74F240/74F240A/
74F241/74F241A
FEA TURES
• Octal bus interface
• 3-State buffer outputs sink 64mA
• 15mA source current
• Guaranteed output skew less than 2.0ns
(74F240A/74F241A)
• Reduced ground bounce (74F240A/74F241A)
• Reduced I
• Reduced loading (74F240A I
74F241A I
TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL)
74F240 4.3ns 37mA
74F240A 3.8ns 40mA
74F241 5.0ns 53mA
74F241A 4.5ns 32mA
(74F241A only)
CC
= 40µA)
IL
= 100µA,
IL
DESCRIPTION
The 74F240 and 74F241 are octal buffers that are ideal for
driving bus lines of buffer memory address registers. The
outputs are all capable of sinking 64mA and sourcing up to
15mA. The device features two output enables, each
controlling four of the 3–state outputs.
The 74F240A and 74F241A are functionally equivalent to
their non–A counterparts. They have been designed to
reduce effects of ground noise. Other advantages are noted
in the features.
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
= 5V ±10%, T
V
CC
20–pin plastic DIP N74F240N, N74F240AN, N74F241N, N74F241AN SOT146-1
20–pin plastic SOL N74F240D, N74F240AD, N74F241D, N74F241AD SOT163-1
20-pin plastic SSOP II N74F240DB SOT339-1
= 0°C to +70°C
amb
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
Data inputs (74F240) 1.0/1.67 20µA/1.0mA
Ian, Ibn Data inputs (74F240A) 1.0/0.167 20µA/100µA
Data inputs (74F241) 1.0/2.67 20µA/1.6mA
Data inputs (74F241A) 1.0/0.067 20µA/40µA
OEa, OEb Output enable inputs (active low) (74F240) 1.0/0.33 20µA/0.2mA
Output enable inputs (active low) (74F240A) 1.0/0.167 20µA/100µA
OEa, OEb Output enable input (74F241) 1.0/1.67 20µA/1.0mA
Output enable input (74F241A) 1.0/0.067 20µA/40µA
Yan, Ybn Data outputs (74F241, 74F241A) 750/106.7 15mA/64mA
Yan, Ybn Data outputs (74F240, 74F240A) 750/106.7 15mA/64mA
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
January 2, 1991 853–0355 01345
2
Philips Semiconductors Product specification
Buffers
PIN CONFIGURATION FOR 74F240/74F240A
1
OEa
2
Ia0
3
Yb0
4
Ia1
5
Y
b1
6
Ia2
7
Y
b2
8
Ia3
9
Yb3
10 11
GND
LOGIC SYMBOL FOR 74F240/74F240A
2 4 6 8 17 15 13 11
V
20
OEb
19
Y
18
17
Ib0
16
Y
15
Ib1
14
Y
13
Ib2
12
Ya3
Ib3
SF00320
CC
a0
a1
a2
74F240/74F240A/
74F241/74F241A
IEC/IEEE SYMBOL FOR 74F240/74F240A
1
19
17
15
13
11
LOGIC DIAGRAM FOR 74F240/74F240A
2
Ia0
EN1
EN2
2
4
6
8
2D
18
1
2
a0
Y
Ib0
18
16
14
12
3
5
7
9
SF00322
17
3
Yb0
Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3
119OEa
OEb
Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3
181614123579
VCC = Pin 20
GND = Pin 10
SF00321
FUNCTION TABLE FOR 74F240/74F240A
INPUTS OUTPUTS
OEa Ia OEb Ib Ya Yb
L L L L H H
L H L H L L
H X H X Z Z
Notes to function table for 74F240/74F240A
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance ”off” state
Ia1
Ia2
Ia3
OEa
VCC = Pin 20
GND = Pin 10
5
7
9
SF00323
Y
Yb2
Y
b1
b3
OE
Ib1
Ib2
Ib3
15
13
11
10
b
4
6
8
1
16
Y
a1
14
Ya2
12
Y
a3
January 2, 1991
3
Philips Semiconductors Product specification
Buffers
PIN CONFIGURATION FOR 74F241/74F241A
V
1
OEa
2
Ia0
3
Yb0
4
Ia1
5
Yb1
6
Ia2
7
Yb2
8
Ia3
9
Yb3
10 11
GND
LOGIC SYMBOL FOR 74F241/74F241A
2 4 6 8 17 15 13 11
20
19
18
17
16
15
14
13
12
SF00324
CC
OEb
Ya0
Ib0
Ya1
Ib1
Ya2
Ib2
Ya3
Ib3
74F240/74F240A/
74F241/74F241A
IEC/IEEE SYMBOL FOR 74F241/74F241A
1
19
2
4
6
8
17
15
13
11
LOGIC DIAGRAM FOR 74F241/74F241A
2
Ia0
EN1
EN2
2D
18
Ya0
1
2
Ib0
18
16
14
12
3
5
7
9
SF00326
17
3
Yb0
Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3
1
OEa
19
VCC = Pin 20
GND = Pin 10
OEb
Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3
18 16 14 12 3 5 7 9
SF00325
FUNCTION TABLE FOR 74F241/74F241A
INPUTS OUTPUTS
OEa Ia OEb Ib Ya Yb
L L H L L L
L H H H H H
H X L X Z Z
Notes to function table for 74F241/74F241A
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance ”off” state
4
Ia1
6
Ia2
8
Ia3
1
OE
a
VCC = Pin 20
GND = Pin 10
16
Ya1
14
Ya2
12
Ya3
Ib1
Ib2
Ib3
OEb
15
13
11
10
5
7
9
SF00327
Yb1
Yb2
Yb3
January 2, 1991
4
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