Philips N74F2240D, N74F2241D, N74F2241N, N74F2240N Datasheet
INTEGRATED CIRCUITS
74F2240
Octal inverter buffer with 30Ω equivalent
output termination (3-State)
74F2241
Octal buffer with 30Ω equivalent output
termination (3-State)
Product specification
IC15 Data Handbook
1990 Dec 13
Philips Semiconductors Product specification
74F2240, 74F2241Octal buffers
FEA TURES
•Octal bus interface
•30Ω output termination ideal for driving DRAM
•15mA source current
DESCRIPTION
The 74F2240 and 74F2241 are octal buffers that are ideal for
driving dynamic DRAM with impedance matching. The outputs are
all capable of sinking 5mA and sourcing up to 15mA. The device
features two output enables, each controlling four of the 3-state
outputs.
TYPICAL
PROPAGATION
TYPE
DELA Y
74F2240 4.3ns 37mA
74F2241 4.5ns 30mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
= 5V ±10%,
V
CC
T
= 0°C to +70°C
amb
20-pin plastic DIP N74F2240N, N74F2241N SOT146-1
20-pin plastic SOL N74F2240D, N74F2241D SOT163-1
TYPICAL
SUPPLY CURRENT
(TOTAL)
PKG DWG #
PIN CONFIGURATION
1
OEa
2
Ia0
3
Y
b0
4
Ia1
5
b1
Y
6
Ia2
7
Y
b2
8
Ia3
9
Yb3
10 11
GND
LOGIC SYMBOL
246817151311
Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3
1
OEa
19
OEb
Ya0 Ya1 Ya2 Ya3Yb0Yb1Yb2Yb3
74F2240
74F2240
20
V
CC
19
OEb
18
Y
a0
17
Ib0
16
Y
a1
15
Ib1
14
Y
a2
13
Ib2
12
a3
Y
Ib3
SF00561
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
Ian, Ibn Data inputs 1.0/0.33 20µA/0.2mA
OEa, OEb
OEb
Output enable inputs
(active Low)
Output enable input
(74F2241)
1.0/0.33
1.0/0.33
Yan, Ybn Data outputs (74F2241) 750/8.33 15mA/5mA
Yan, Ybn Data outputs (74F2240) 750/8.33 15mA/5mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the High
state and 0.6mA in the Low state.
LOAD
VALUE
HIGH/LOW
20µA/0.2mA
20µA/0.2mA
181614123579
V
= Pin 20
CC
GND = Pin 10
IEC/IEEE SYMBOL
1
19
2
4
6
8
17
15
13
11
EN1
EN2
2D
74F2240
SF00562
1
2
18
16
14
12
3
5
7
9
SF00563
December 13, 1990 853-1524 01255
2
Philips Semiconductors Product specification
74F2240, 74F2241Octal buffers
PIN CONFIGURATION
1
OEa
2
Ia0
3
Yb0
4
Ia1
5
Yb1
6
Ia2
7
Yb2
8
Ia3
9
Yb3
10 11
GND
LOGIC SYMBOL
246817151311
Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3
1
OEa
19
OEb
Ya0 Ya1 Ya2 Ya3Yb0Yb1Yb2Yb3
181614123579
= Pin 20
V
CC
GND = Pin 10
IEC/IEEE SYMBOL
1
19
2
4
6
8
17
15
13
11
EN1
EN2
2D
74F2241
74F2241
74F2241
1
2
V
20
CC
19
OEb
18
Ya0
17
Ib0
16
Ya1
15
Ib1
14
Ya2
13
Ib2
12
Ya3
Ib3
SF00565
LOGIC DIAGRAM FOR 74F2240
2
Y
5
Y
7
Y
9
Y
SF00567
b0
b1
b2
b3
SF00564
2
Ia0
4
Ia1
6
Ia2
8
Ia3
1
a
OE
VCC = Pin 20
GND = Pin 10
OE
Ib0
Ib1
Ib2
Ib3
17
15
13
11
10
b
18
Y
a0
15
Y
a1
14
a2
Y
12
Y
a3
LOGIC DIAGRAM FOR 74F2241
Ia0
Ia1
Ia2
Ia3
a
OE
VCC = Pin 20
GND = Pin 10
2
4
6
8
1
18
Ya0
15
Ya1
14
Ya2
12
Ya3
Ib0
Ib1
Ib2
OEb
17
15
13
11
Ib
10
2
Yb0
5
Yb1
7
Yb2
9
Yb3
SF00568
FUNCTION TABLE FOR 74F2240
INPUTS OUTPUTS
OEa Ia OEb Ib Ya Yb
L L L L H H
L H L H L L
H X H X Z Z
18
16
14
12
3
5
7
9
SF00566
Notes to function table for 74F2240
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance ”off” state
FUNCTION TABLE FOR 74F2241
INPUTS OUTPUTS
OEa Ia OEb Ib Ya Yb
L L H L L L
L H H H H H
H X L X Z Z
Notes to function table for 74F2241
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance ”off” state
December 13, 1990
3
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