Philips N74F198N, N74F198D Datasheet

INTEGRATED CIRCUITS

74F198

8-bit bidirectional universal shift register

Product specification

1987 Oct 02

IC15 Data Handbook

m n r

Philips Semiconductors	Product specification
8-bit bidirectional universal shift register	74F198

FEATURES

•Buffered clock and control inputs

•Shift right, shift left, and parallel load capability

•Asynchronous Master Reset

DESCRIPTION

The 74F198 Bidirectional Universal Shift Register is designed to incorporate virtually all of the features a system designer may want in a shift register. This circuit features parallel inputs and outputs, shift right and shift left serial inputs, operating mode select inputs, and direct overriding master reset input. The register has four distinct modes of operation:

±Parallel (broadside) load

±Shift right (in the direction Q0 toward Q7)

±Shift left (in the direction Q7 toward Q0)

±Inhibit clock (do nothing).

Synchronous parallel loading is accomplished by applying the 8 bits of data and taking both mode control inputs, S0 and S1, High. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock inputs. During loading, serial data flow is inhibited.

Shift right is accomplished synchronously, with the rising edge of the clock pulse when S0 is High and S1 is Low. Serial data for this mode is entered at the right data input (DSR). When S0 is Low and

S1 is High, data shifts left synchronously and new data is entered at the shift-left serial input (DSL).

Clocking of the flip-flops is inhibited when both mode control inputs are Low.

PIN CONFIGURATION

S0	1	24	VCC
DSR	2	23	S1
D0	3	22	DSL
Q0	4	21	D7
D1	5	20	Q7
Q1	6	19	D6
D2	7	18	Q6
Q2	8	17	D5
D3	9	16	Q5
Q3	10	15	D4
CP	11	14	Q4
GND	12	13
			MR
		SF00160

TYPE	TYPICAL fMAX	TYPICAL SUPPLY CURRENT
		(TOTAL)
74F198	95MHz	73mA

ORDERING INFORMATION

	COMMERCIAL RANGE
DESCRIPTION	VCC = 5V ±10%,	PKG DWG #
	Tamb = 0°C to +70°C
24-pin Plastic Slim	N74F198N	SOT222-1
DIP (300mil)
24-pin Plastic SOL	N74F198D	SOT137-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS			DESCRIPTION	74F (U.L.) HIGH/LOW	LOAD VALUE HIGH/LOW
D0±D7			Parallel data inputs	1.0/1.0	20μA/0.6mA
DSR			Serial data input (Shift Right)	1.0/1.0	20μA/0.6mA
DSL			Serial data input (Shift Left)	1.0/1.0	20μA/0.6mA
S0±S1			Mode Select inputs	1.0/1.0	20μA/0.6mA
	CP		Clock Pulse input (Active rising edge)	1.0/1.0	20μA/0.6mA
			Master Reset input (Active Low)	1.0/1.0	20μA/0.6mA
	MR
Q0±Q7			Data outputs	50/33	1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20μA in the High state and 0.6mA in the Low state.

October 2, 1987

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853±0089 90746

Philips Semiconductors	Product specification
8-bit bidirectional universal shift register	74F198

LOGIC SYMBOL

IEC/IEEE SYMBOL

13

SRG8

R

2

3

5

7

9

15

17

19

21

22

1

0

0

23

1

M 3

11

C4

1 → /2 ←

DSR D0

D1

D2

D3

D4

D5

D6

D7 DSL

13

MR

2

3

1, 4D

4

1

S0

3, 4D

5

6

23

S1

3, 4D

7

8

11

CP

9

10

Q0

Q1

Q2 Q3

Q4

Q5

Q6 Q7

15

14

17

16

19

18

21

3, 4D

20

22

VCC = Pin 24

4

6

8

10

14

16

18

20

2, 4D

GND = Pin 12

SF00161

SF00162

FUNCTION TABLE

INPUTS

OUTPUTS

MODE

CP

SERIAL

PARALLEL

Q0

Q1

…

Q6

Q7

MR

S0

S1

LEFT

RIGHT

0… 7

L

X

X

X

X

X

X

L

L

L

L

H

X

X

L

X

X

X

Q00

Q10

Q60

Q70

H

H

H

↑

X

X

0… 7

0

1

6

7

H

H

L

↑

X

H

X

H

Q0n

Q5n

Q6n

H

H

L

↑

X

L

X

L

Q0n

Q5n

Q6n

H

L

H

↑

H

X

X

Q1n

Q2n

Q7n

H

H

L

H

↑

L

X

X

Q1n

Q2n

Q7n

L

H

L

L

X

X

X

X

Q00

Q10

Q60

Q70

H

=

High voltage level

L

=

Low voltage level

X

=

Don't care

↑= Low-to-High transition of designated input

0… 7 = The level of steady input at inputs 0 through 7, respectively.

Q00, Q10, Q60, Q70	=	The level of Q0, Q1, Q6,	Q7, respectively, before the indicated steady state input conditions were established.
Q0n, Q1n, Q6n, Q7n	=	The level of Q0, Q1, Q6,	Q7, respectively, before the most recent Low-to-High clock transition.

October 2, 1987

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Philips Semiconductors	Product specification
8-bit bidirectional universal shift register	74F198

LOGIC DIAGRAM

	CP	11
	DSR	2
	S1	23
	S0	1	R	CP	S
		3
	D0
				Q
					4
	D1	5	R	CP	S
				Q
					6
	D2	7	R	CP	S
				Q
					8
	D3	9	R	CP	S
				Q
					10
	D4	15	R	CP	S
				Q
					14
	D5	17	R	CP	S
				Q
					16
	D6	19	R	CP	S
				Q
					18
	D7	21	R	CP	S
				Q
	DSL	22			20
	MR	13

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

SF00163

October 2, 1987

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