INTEGRATED CIRCUITS
74F195A
4-bit parallel-access shift register
Product specification |
1996 Mar 12 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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4-bit parallel-access shift register |
74F195A |
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FEATURES
•Shift right and parallel load capability
•J ± K (D) inputs to first stage
•Complement output from last stage
•Asynchronous Master Reset
•Diode inputs
DESCRIPTION
The 74F195A is a 4-Bit Parallel Access Shift Register and its functional characteristics are indicated in the Logic Diagram and Function Table. This device is useful in a variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds.
The 74F195A operates in two primary modes: shift right (Q0→ Q1) and parallel load, which are controlled by the state of the Parallel
Enable (PE) input. Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE input is High, and is shifted one bit in the direction Q0→ Q1→ Q2→ Q3 following each Low-to-High clock transition.
The J and K inputs provide the flexibility of the J-K type input for special applications, and by tying the two together the simple D-type input is made for general applications.
The device appears as four common clocked D flip-flops when the PE input is Low. After the Low-to-High clock transition, data on the parallel inputs (D0±D3) is transferred to the respective Q0±Q3 outputs. Shift left operation (Q3±Q2) can be achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input Low.
All parallel and serial data transfers are synchronous, occurring after each Low-to-High clock transition. The 74F195A utilizes edge-triggering, therefore there is no restriction on the activity of the
J, K, Dn, and PE inputs for logic operation, other than the set-up and hold time requirements.
A Low on the asynchronous Master Reset (MR) input sets all Q outputs Low, independent of any other input condition.
PIN CONFIGURATION
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MR |
1 |
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16 |
VCC |
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J |
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Q0 |
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2 |
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15 |
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Q1 |
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K |
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3 |
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14 |
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D0 |
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Q2 |
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4 |
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13 |
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D1 |
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Q3 |
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5 |
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12 |
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D2 |
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6 |
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11 |
Q3 |
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D3 |
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7 |
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10 |
CP |
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GND |
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8 |
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9 |
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PE |
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SF00757 |
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TYPICAL |
TYPE |
TYPICAL fMAX |
SUPPLY CURRENT |
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(TOTAL) |
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74F195A |
180MHz |
40mA |
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ORDERING INFORMATION
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COMMERCIAL RANGE |
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DESCRIPTION |
VCC = 5V ±10%, |
PKG. DWG. # |
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Tamb = 0°C to +70°C |
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16-pin plastic DIP |
N74F195AN |
SOT 38-4 |
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16-pin plastic SO |
N74F195AD |
SOT 109-1 |
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INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS |
DESCRIPTION |
74F (U.L.) |
LOAD VALUE HIGH/LOW |
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HIGH/LOW |
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D0±D3 |
Data inputs |
74F195 |
1.0/0.033 |
20mA/20mA |
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74F195A |
1.0/1.0 |
20mA/0.6mA |
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J, |
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J-K or D type serial inputs |
74F195 |
1.0/0.033 |
20mA/20mA |
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K |
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74F195A |
1.0/1.0 |
20mA/0.6mA |
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CP |
Clock Pulse input (active rising edge) |
74F195 |
1.0/0.033 |
20mA/20mA |
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74F195A |
1.0/1.0 |
20mA/0.6mA |
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Master Reset input (active Low) |
74F195 |
2.0/0.066 |
40mA/40mA |
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MR |
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74F195A |
1.0/1.0 |
20mA/0.6mA |
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Q0±Q3, |
Data outputs |
50/33 |
1.0mA/20mA |
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Q3 |
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NOTE:
One (1.0) FAST unit load is defined as: 20mA in the High state and 0.6mA in the Low state.
1996 Mar 12 |
2 |
853-0024 16555 |
Philips Semiconductors |
Product specification |
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4-bit parallel-access shift register |
74F195A |
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LOGIC SYMBOL |
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IEC/IEEE SYMBOL |
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4 |
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6 |
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9 |
M1 |
SRG4 |
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1 |
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R |
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D0 |
D1 |
D2 |
D3 |
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10 |
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C2/1 |
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PE |
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2 |
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J |
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Q3 |
11 |
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2 |
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10 |
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CP |
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1, 2J |
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3 |
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1, 2K |
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15 |
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3 |
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K |
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4 |
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1, 2D |
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14 |
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1 |
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MR |
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5 |
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Q0 |
Q1 |
Q2 |
Q3 |
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1, 2D |
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6 |
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13 |
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7 |
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12 |
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VCC = Pin 16 |
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11 |
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15 |
14 |
13 |
12 |
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GND = Pin 8 |
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SF00758 |
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SF00759 |
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LOGIC DIAGRAM
CP |
10 |
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PE |
9 |
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J |
2 |
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K |
3 |
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MR |
1 |
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D0 |
4 |
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5
D1
6
D2
7
D3
VCC = Pin 16
GND = Pin 8
R |
S |
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15 |
Q0 |
CP |
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Q |
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RD |
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Q |
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R |
S |
Q |
14 |
Q1 |
CP |
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RD
R |
S |
Q |
13 |
Q2 |
CP |
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RD
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12 |
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R |
S |
Q3 |
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CP |
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Q |
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11 |
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Q3 |
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RD |
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Q |
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SF00760 |
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1996 Mar 12 |
3 |
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