INTEGRATED CIRCUITS
74F805, 74F1805
Hex 2-input NOR drivers
Product specification |
1990 Sep 14 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Hex 2-input NOR drivers |
74F805/74F1805 |
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FEATURES
•High capacitive drive capability
•Choice of configuration
Corner VCC and GND ± 74F805 Center VCC and GND ± 74F1805
•Typical propagation delay of 2.3ns
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TYPICAL |
TYPICAL SUPPLY |
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PROPAGATION |
CURRENT |
TYPE |
DELAY |
( TOTAL) |
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74F805 |
2.3ns |
10mA |
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74F1805 |
2.3ns |
10mA |
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ORDERING INFORMATION
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ORDER CODE |
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DESCRIPTION |
COMMERCIAL RANGE |
PKG DWG # |
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VCC = 5V ±10%, |
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Tamb = 0°C to +70°C |
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20±pin plastic DIP |
N74F805N, N74F1805N |
SOT146-1 |
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20±pin plastic SOL |
N74F805D, N74F1805D |
SOT163-1 |
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INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
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PINS |
DESCRIPTION |
74F |
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(U.L.) |
LOAD VALUE |
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HIGH/ |
HIGH/LOW |
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LOW |
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Dna ± Dnb |
Data inputs |
1.0/0.033 |
20μA/20μA |
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Data outputs |
2400/80 |
48mA/48mA |
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Q0 ± Q5 |
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NOTE: One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.
PIN CONFIGURATION
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74F805 |
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D0a |
1 |
20 |
VCC |
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D0b |
2 |
19 |
D5b |
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3 |
18 |
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Q0 |
D5a |
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D1a |
4 |
17 |
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Q5 |
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D1b |
5 |
16 |
D4b |
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Q1 |
6 |
15 |
D4a |
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D2a |
7 |
14 |
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Q4 |
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D2b |
8 |
13 |
D3b |
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Q2 |
9 |
12 |
D3a |
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GND 10 |
11 |
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Q3 |
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SF00456 |
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LOGIC SYMBOL
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74F805 |
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1 |
2 |
4 |
5 |
7 |
8 |
12 |
13 |
15 |
16 |
18 |
19 |
D0a D0bD1a D1bD2a D2b D3aD3bD4aD4bD5a D5b
Q0 Q1 Q2 Q3 Q4 Q5
3 6 9 11 14 17
VCC = Pin 20 |
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GND = Pin 10 |
SF00457 |
IEC/IEEE SYMBOL
74F805
1
1 |
3 |
2
4
6
5
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9
8
12
11
13
15
14
16
18
17
19
SF00458
September 14, 1990 |
2 |
853-0037 00417 |
Philips Semiconductors |
Product specification |
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Hex 2-input NOR drivers |
74F805/74F1805 |
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PIN CONFIGURATION
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74F1805 |
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D4b |
1 |
20 |
D4a |
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2 |
19 |
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Q4 |
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Q5 |
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D5a |
3 |
18 |
D3b |
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D5b |
4 |
17 |
D3a |
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VCC 5 |
16 |
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Q3 |
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D0a |
6 |
15 |
GND |
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D0b |
7 |
14 |
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Q2 |
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8 |
13 |
D2b |
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Q0 |
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D1a |
9 |
12 |
D2a |
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D1b 10 |
11 |
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Q1 |
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SF00459 |
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LOGIC SYMBOL
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74F1805 |
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6 |
7 |
9 |
10 |
12 |
13 |
17 |
18 |
20 |
1 |
3 |
4 |
D0a D0bD1a D1bD2a D2b D3a D3bD4a D4bD5a D5b
Q0 |
Q1 |
Q2 Q3 Q4 Q5 |
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8 |
11 |
14 |
16 |
19 |
2 |
VCC = Pin 5 |
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SF00460 |
GND = Pin 15 |
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LOGIC DIAGRAM
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74F805 |
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74F1805 |
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D0a |
1 |
3 |
D0a |
6 |
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8 |
2 |
7 |
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D0b |
QO |
D0b |
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QO |
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D1a |
4 |
6 |
D1a |
9 |
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11 |
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D1b 5 |
Q1 |
D1b 10 |
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Q1 |
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D2a |
7 |
9 |
D2a |
12 |
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14 |
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8 |
Q2 |
13 |
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Q2 |
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D2b |
D2b |
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D3a |
12 |
11 |
D3a |
17 |
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16 |
13 |
Q3 |
18 |
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Q3 |
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D3b |
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D3b |
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D4a |
15 |
14 |
D4a |
20 |
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19 |
16 |
1 |
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D4b |
Q4 |
D4b |
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Q4 |
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D5a |
18 |
17 |
D5a |
3 |
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2 |
19 |
Q5 |
4 |
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Q5 |
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D5b |
D5b |
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VCC = Pin 20 |
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VCC = Pin 5 |
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GND = Pin 10 |
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GND |
= Pin 15 |
SF00462 |
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FUNCTION TABLE
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INPUTS |
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OUTPUT |
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Dna |
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Dnb |
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Qn |
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H |
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X |
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L |
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X |
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H |
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L |
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L |
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L |
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H |
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Notes to function table |
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H |
= |
High voltage level |
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L |
= |
Low voltage level |
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X |
= |
Don't care |
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IEC/IEEE SYMBOL
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74F1805 |
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6 |
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1 |
8 |
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7 |
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9 |
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11 |
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10 |
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12 |
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14 |
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13 |
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17 |
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16 |
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18 |
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20 |
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19 |
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1 |
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3 |
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2 |
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4 |
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SF00461 |
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September 14, 1990 |
3 |
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