INTEGRATED CIRCUITS
74F175*, 74F175A
Quad D flip-flop
* Discontinued part. Please see the Discontinued Product List in Section 1, page 21.
Product specification |
1996 Mar 12 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Quad D flip-flop |
74F175A |
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FEATURES
•Four edge-triggered D-type flip-flops
•Buffered common clock
•Buffered asynchronous Master Reset
•True and complementary outputs
•Industrial temperature range available (±40°C to +85°C)
•PNP light loading inputs
DESCRIPTION
The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
PIN CONFIGURATION
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MR |
1 |
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16 |
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VCC |
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Q0 |
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Q3 |
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2 |
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15 |
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Q0 |
3 |
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14 |
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Q3 |
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D0 |
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D3 |
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4 |
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13 |
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D1 |
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D2 |
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5 |
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12 |
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Q1 |
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11 |
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Q2 |
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Q1 |
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Q2 |
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7 |
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10 |
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GND |
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CP |
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8 |
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9 |
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SF00718 |
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The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output.
All Q outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for applications where both true and complementary outputs are required, and the CP and MR are common to all storage elements.
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
TYPE |
TYPICAL fmax |
TYPICAL SUPPLY |
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CURRENT (TOTAL) |
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74F175A |
160MHz |
22mA |
ORDERING INFORMATION
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ORDER CODE |
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DESCRIPTION |
COMMERCIAL RANGE |
PKG. DWG. # |
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VCC = 5V ±10%, |
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Tamb = 0°C to +70°C |
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16-pin plastic DIP |
74F175AN |
SOT38-4 |
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16-pin plastic SO |
74F175AD |
SOT109-1 |
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PINS |
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DESCRIPTION |
74F (U.L.) |
LOAD VALUE |
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HIGH/LOW |
HIGH/LOW |
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D0 ± D3 |
Data inputs |
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74F175A |
1.0/0.033 |
20μA/20μA |
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Master reset input (active±Low) |
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74F175A |
1.0/0.033 |
20μA/20μA |
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MR |
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CP |
Clock input (active rising edge) |
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74F175A |
1.0/0.033 |
20μA/20μA |
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Q0±Q3 |
True outputs |
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50/33 |
1.0mA/20mA |
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Complementary outputs |
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50/33 |
1.0mA/20mA |
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Q0±Q3 |
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NOTE:
One (1.0) FAST unit load is defined as: 20μA in the High state and 0.6mA in the Low state.
1996 Mar 12 |
2 |
853±0047 16555 |
Philips Semiconductors |
Product specification |
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Quad D flip-flop |
74F175A |
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LOGIC SYMBOL |
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IEC/IEEE SYMBOL |
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1 |
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R |
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4 |
5 |
12 |
13 |
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9 |
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C1 |
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4 |
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2 |
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D0 |
D1 |
D2 |
D3 |
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3 |
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1D |
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9 |
CP |
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5 |
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7 |
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1 |
MR |
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6 |
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Q0 |
Q0 Q1 Q1 Q2 |
Q2 |
Q3 Q3 |
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12 |
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10 |
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11 |
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13 |
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15 |
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2 |
3 |
7 |
6 |
10 |
11 |
15 |
14 |
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14 |
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VCC = Pin 16 |
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GND = Pin 8 |
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SF00719 |
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SF00720 |
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LOGIC DIAGRAM |
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D0 |
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D1 |
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D2 |
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D3 |
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4 |
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5 |
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12 |
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13 |
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CP |
9 |
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D Q |
D Q |
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D Q |
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D Q |
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CP |
CP |
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CP |
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CP Q |
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RD |
RD |
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RD |
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RD |
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MR |
1 |
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VCC = Pin 16 |
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3 |
2 |
6 |
7 |
11 |
10 |
14 |
15 |
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Q0 |
Q0 |
Q1 |
Q1 |
Q2 |
Q2 |
Q3 |
Q3 |
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GND = Pin 8 |
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SF00721 |
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FUNCTION TABLE
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INPUTS |
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OUTPUTS |
OPERATING |
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MR |
CP |
Dn |
Qn |
Qn |
MODE |
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L |
X |
X |
L |
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H |
Reset (clear) |
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H |
↑ |
h |
H |
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L |
Load ª1º |
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H |
↑ |
I |
L |
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H |
Load ª0º |
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H = High voltage level
h= High state must be present one setup time before the Low-to-High clock transition
L = Low voltage level
l= Low state must be present one setup time before the Low-to-High clock transition
X |
= |
Don't care |
↑ |
= |
Low-to-High clock transition |
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL |
PARAMETER |
RATING |
UNIT |
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VCC |
Supply voltage |
±0.5 to +7.0 |
V |
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VIN |
Input voltage |
±0.5 to +7.0 |
V |
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IIN |
Input current |
±30 to +5 |
mA |
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VOUT |
Voltage applied to output in High output state |
±0.5 to V |
V |
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CC |
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IOUT |
Current applied to output in Low output state |
40 |
mA |
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Tamb |
Operating free air temperature range |
Commercial range |
0 to +70 |
°C |
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Industrial range |
±40 to +85 |
°C |
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T |
Storage temperature range |
±65 to +150 |
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stg |
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C |
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1996 Mar 12 |
3 |
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