Philips N74F173D, N74F173N Datasheet

INTEGRATED CIRCUITS

74F173

Quad D-type flip-flop (3-State)

Product specification

1990 Aug 31

IC15 Data Handbook

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Philips Semiconductors	Product specification
Quad D-type flip±flop (3-State)	74F173

FEATURES

•Edge±triggered D±type register

•Gated clock enable for hold ºdo nothingº mode

•3±state output buffers

•Gated output enable control

•Speed upgrade of N8T10 and current sink upgrade

•Controlled output edges to minimize ground bounces

•48mA sinking capability

DESCRIPTION

The 74F173 is a high speed 4±bit parallel load register with clock enable control, 3±state buffered outputs, and master reset (MR). When the two clock enable (E0 and E1) inputs are low, the data on the D inputs is loaded into the register simultaneously with low±to±high clock (CP) transition. When one or both enable inputs are high one setup time before the low±to±high clock transition, the register retains the previous data.

Data inputs and clock enable inputs are fully edge±triggered and must be stable only one setup time before the low±to±high clock transition.

The master reset (MR) is an active±high asynchronous input. When the MR is high, all four flip±flops are reset (cleared) independently of any other input condition.

The 3±state output buffers are controlled by a 2±input NOR gate. When both output enable (OE0 and OE1) inputs are low, the data in the register is presented at the Q output.

When one or both OE inputs are high, the outputs are forced to a high impedance ºoffº state.

The 3±state output buffers are completely independent of the register operation; the OE transition does not affect the clock and reset operations.

TYPE	TYPICAL fmax	TYPICAL SUPPLY CURRENT (TOTAL)
74F173	125MHz	23mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

VCC = 5V ±10%, Tamb = 0°C to +70°C

16±pin plastic DIP

N74F173N

SOT38-4

16±pin plastic SO

N74F173D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/

LOAD VALUE

LOW

HIGH/LOW

D0 ± D3

Data inputs

1.0/1.0

20μA/0.6mA

CP

Clock input

1.0/1.0

20μA/0.6mA

Clock enable inputs

1.0/1.0

20μA/0.6mA

E0, E1

MR

Master reset input

1.0/1.0

20μA/0.6mA

Output enable inputs

1.0/1.0

20μA/0.6mA

OE0, OE1

Q0 ± Q3

Data outputs

750/80

15mA/48mA

Note to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.

August 31, 1990

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853±1160 00286

Philips Semiconductors	Product specification
Quad D-type flip±flop (3-State)	74F173

PIN CONFIGURATION

IEC/IEEE SYMBOL

9

&

OE0

1

16

VCC

10

C1

OE1

2

15

MR

7

1

Q0

3

14

D0

&

2

EN

Q1

4

13

D3

15

R

Q2

5

12

D2

Q3

14

3

6

11

Q2

13

1D

4

CP

7

10

E1

12

5

GND

8

9

E0

11

6

SF00290

SF00292

LOGIC SYMBOL

14

13

12

11

9

E0

D0

D1

D2

D3

10

E1

7

CP

15

MR

1

OE0

2

OE1 Q0 Q1 Q2 Q3

VCC = Pin 16

3

4

5

6

GND = Pin 8

SF00291

FUNCTION TABLE

INPUTS

OUTPUTS

OUTPUTS

MR

CP

E0

E1

Dn

Qn (register)

H

X

X

X

X

L

Reset (clear)

L

↑

l

l

l

L

Parallel load

L

↑

l

l

h

H

L

X

h

X

X

qn

Hold (do nothing)

L

X

X

h

X

qn

Notes to function table

H

=

High±voltage level

h

=

High state one setup time before the low±to±high clock transition

L

=

Low±voltage level

l

=

Low state one setup time before the low±to±high clock transition

qn =		Lower case letters indicate the state of the referenced input (or output) on setup time prior to the low±to±high clock transition
X	=	Don't care
↑	=	Low±to±high clock transition

August 31, 1990

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