Philips N74F138N, N74F138D Datasheet
INTEGRATED CIRCUITS
74F138
1-of-8 decoder/demultiplexer
Product specification
IC15 Data Handbook
1991 Feb 14
Philips Semiconductors Product specification
74F1381-of-8 decoder/demultiplexer
FEA TURE
PIN CONFIGURATION
• Demultiplexing capability
1
•Multiple input enable for easy expansion
•Ideal for memory chip select decoding
•Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F138 decoder accepts three binary weighted inputs (A0, A1,
A2) and when enabled, provides eight mutually exclusive, active low
outputs (Q
active low (E
high unless E
0 – Q7). The device features three enable inputs; two
0, E1) and one active high (E2). Every output will be
0 and E1 are low and E2 is high. This multiple enable
A0
2
A1
3
A2
4
0
E
1
5
E
6
E2
Q
7
function allows easy parallel expansion of the device to 1-of-32
(5 lines to 32 lines) decoder with just four 74F138s and one inverter
(see Figure 1). The device can be used as an eight output
demultiplexer by using one of the active low enable inputs as the
data input and the remaining enable inputs as strobes. Enable
inputs not used must be permanently tied to their appropriate active
high or active low state.
TYPE
74F138 5.8ns 13mA
TYPICAL
PROPAGATION
DELAY
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
16-pin plastic DIP N74F138N I74F138N SOT38-4
16-pin plastic SO N74F138D I74F138D SOT109-1
COMMERCIAL RANGE
VCC = 5V ±10%, T
= 0°C to +70°C
amb
VCC = 5V ±10%, T
INDUSTRIAL RANGE
= –40°C to +85°C
amb
16
V
CC
15
Q
0
14
1
Q
13
Q2
Q3
12
Q4
11
107
Q5
98GND Q6
SF00174
TYPICAL
SUPPLY CURRENT
(TOTAL)
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW
A0 – A2 Address inputs 1.0/1.0 20µA/0.6mA
E0, E1 Enable inputs (active Low) 1.0/1.0 20µA/0.6mA
E2 Enable input (active High) 1.0/1.0 20µA/0.6mA
Q0 – Q7 Data outputs 50/33 1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
4
5
6
VCC = Pin 16
GND = Pin 8
123
E0
E1
E2
Q114Q0
15
A1 A2A0
Q2 Q3 Q4 Q5
13 12 11 10
Q69Q7
7
SF00175
IEC/IEEE SYMBOL
1
2
3
4
5
6
0
2
DMUX
G
&
0
0
1
3
2
3
4
5
6
7
15
14
13
12
11
10
9
7
SF00176
February 14, 1991 853–0343 01719
2
Philips Semiconductors Product specification
74F1381-of-8 decoder/demultiplexer
LOGIC DIAGRAM
3
A2
2
A1
1
A0
4
0
E
5
1
E
6
E2
15 14 13 12 11 10 9 7
0Q1Q2Q3Q4Q5Q6Q7
Q
V
= Pin 16
CC
GND = Pin 8
FUNCTION TABLE
INPUTS OUTPUTS
E0 E1 E2 A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H H L L H L H H H H H H
L L H L H L H H L H H H H H
L L H H H L H H H L H H H H
L L H L L H H H H H L H H H
L L H H L H H H H H H L H H
L L H L H H H H H H H H L H
L L H H H H H H H H H H H L
NOTES:
H = High voltage level
L = Low voltage level
X = Don’t care
SF00177
APPLICATION
A0
A1
A2
A3
A4
February 14, 1991
H
A0 A1 A2
E2
E1
74F138
E0
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
A0 A1 A2
E2
E1
74F138
E0
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
E2
E1
E0
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Figure 1. Expansion of 1-of-8 Decoding
3
A0 A1 A2
74F138
74F04
A0 A1 A2
E2
E1
74F138
E0
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q31Q0
SF00178
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