Philips MINI X5 SERVICE MANUAL

K9K2G08U0A

K9K2G08R0A

K9K2G08X0A

FLASH MEMORY

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.

NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,

TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1

K9K2G08U0A

K9K2G08R0A

Document Title

256M x 8 Bit NAND Flash Memory

Revision History

FLASH MEMORY

Revision No

0.0

0.1

0.2

0.3

0.4

1.0

History

1. Initial issue

1. Technical note is changed

2. Notes of AC timing characteristics are added

3. The description of Copy-back program is changed

4. TSOP package is deleted

access time : 23ns->35ns (p.9)

1. CE

1. The value of tREA is changed. (18ns->20ns)

2. EDO mode is added.

1. The flow chart to creat the initial invalid block table is changed.

1. 1.8V FBGA spec is merged

2. 3.3V FBGA package is added

3. FBGA package size is changed to 9.5 x 12

4. Leaded part is deleted

Draft Date

May. 31. 2004

Oct. 25. 2004

Feb. 14. 2005

May 4 2005

May 6 2005

Feb. 1 2006

Remark

Advance

Preliminary

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right

to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.

2

K9K2G08U0A

K9K2G08R0A

FLASH MEMORY

256M x 8 Bit NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9K2G08U0A-F 2.7 ~ 3.6V X8 WSOP1

K9K2G08X0A-J 1.65 ~ 1.95V X8 FBGA

FEATURES

• Voltage Supply

- 2.7 V ~3.6 V

- 1.65V ~ 1.95V

• Organization

- Memory Cell Array

- (256M + 8,192K)bit x 8bit

- Data Register

- (2K + 64)bit x8bit

• Automatic Program and Erase

- Page Program

- (2K + 64)Byte

- Block Erase

- (128K + 4K)Byte

• Page Read Operation

- Page Size

- 2K-Byte

- Random Read : 25µs(Max.)

- Serial Access : 50ns(Min.)

• Fast Write Cycle Time

- Program time : 300µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles

- Data Retention : 10 Years

• Command Register Operation

• Unique ID for Copyright Protection

• Package :

- K9K2G08U0A-FIB0
48 - Pin WSOP I (12x17x0.7mm)- Pb-free Package

- K9K2G08X0A-JCB0/JIB0
63- Ball FBGA (9.5x12) - Pb-free Package

GENERAL DESCRIPTION

Offered in 256Mx8bit the K9K2G08X0A is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-effective solution
for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112byte page and an erase
operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 50ns cycle time per byte.
The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all
program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the
write-intensive systems can take advantage of the K9K2G08X0A′s extended reliability of 100K program/erase cycles by providing
ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K2G08X0A is an optimum solution for large nonvolatile
storage applications such as solid state file storage and other portable applications requiring non-volatility.

3

K9K2G08U0A

K9K2G08R0A

PIN CONFIGURATION (WSOP1)

K9K2G08U0A-FIB0

N.C

1

N.C

N.C
N.C
N.C
R/B
RE

CE

N.C
Vcc
Vss
N.C

CLE
ALE

WE
WP
N.C
N.C

N.C
N.C

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

DNU

DNU

DNU

DNU

PACKAGE DIMENSIONS

48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

FLASH MEMORY

N.C
N.C
DNU
N.C
I/O7
I/O6
I/O5
I/O4
N.C
DNU
N.C
Vcc
Vss
N.C
DNU
N.C
I/O3
I/O2
I/O1
I/O0
N.C
DNU
N.C
N.C

48 - WSOP1 - 1217F

#1

+0.07

-0.03

0.16

+0.07

-0.03

0.20

0.50TYP
(0.50±0.06)

#24

15.40±0.10

#48

#25

0.70 MAX

0.58±0.04

(0.01Min)

Unit :mm

12.00±0.10

12.40MAX

17.00±0.20

+0.075

-0.035

0.10

0

°

~

8

°

0.45~0.75

4

K9K2G08U0A

PIN CONFIGURATION (FBGA)

K9K2G08R0A

K9F1G08X0A-JCB0/JIB0

3456 1 2

FLASH MEMORY

N.C N.C

N.C

A

B

C

D

E

F

G

H

N.C N.C

N.C

/RE CLE

NC

NC

NC

NC NC

NC NC NC

NC NC

NC

NC

NCNCNC

NC NC

NCNC I/O0

I/O1NC NC Vcc I/O5 I/O7

N.C N.C

N.C

N.C

R/B/WE/CEVssALE/WP

NC

NC

NC

NC

NCNC

NC

Vcc

VssI/O6I/O4I/O3I/O2Vss

N.C N.C

N.C

N.CN.C

Top View

5

K9K2G08U0A

PACKAGE DEMENSIONS(FBGA)

K9K2G08R0A

FLASH MEMORY

#A1

Top V iew

9.50±0.10

Bottom View

#A1 INDEX MARK(OPTIONAL)

9.50±0.10

0.80 x 9= 7.20

0.80 x 5= 4.00

0.80

65

(Datum A)

A

B

(Datum B)

12.00±0.10

2.80

C

D

E

F

G

H

4321

A

B

0.80

12.00±0.10

0.80 x 7= 5.60

0.80 x 11= 8.80

0.10MAX

63-∅0.45±0.05

∅

0.20

M

A B

Side View

12.00±0.10

2.00

0.45±0.05

1.20(Max)

0.25(Min.)

6

K9K2G08U0A

K9K2G08R0A

PIN DESCRIPTION

Pin Name Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

CLE

The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE

FLASH MEMORY

signal.

ALE

CE

RE

WE

WP

R/B

Vcc

Vss GROUND

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE

CHIP ENABLE

The CE
the device does not return to standby mode in program or erase opertion. Regarding CE
operation, refer to ’Page read’ section of Device operation .

READ ENABLE

The RE
tREA after the falling edge of RE

WRITE ENABLE

The WE
the WE

WRITE PROTECT

The WP
generator is reset when the WP

READY/BUSY OUTPUT

The R/B
random read operation is in process and returns to high state upon completion. It is an open drain output
and does not float to high-z condition when the chip is deselected or when outputs are disabled.

POWER

VCC is the power supply for device.

with ALE high.

input is the device selection control. When the device is in the Busy state, CE high is ignored, and

control during read

input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

which also increments the internal column address counter by one.

input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

pulse.

pin provides inadvertent write/erase protection during power transitions. The internal high voltage

pin is active low.

output indicates the status of the device operation. When low, it indicates that a program, erase or

N.C

NOTE:

1. Connect all VCC and VSS pins of each device to common power supply outputs.

2. Do not leave VCC or VSS disconnected.

NO CONNECTION

Lead is not internally connected.

7

K9K2G08U0A

K9K2G08R0A

Figure 1. Functional Block Diagram

VCC

SS

V

FLASH MEMORY

A12 - A28

A0 - A11

Command

CE
RE
WE

X-Buffers
Latches
& Decoders

Y-B uff ers
Latches
& Decoders

Command

Control Logic

& High Voltage

Generator

CLE

Figure 2 Array Organization

Register

ALE

WP

2048M + 64M Bit

NAND Flash

ARRAY

(2048 + 64)Byte x 131072

Data Register & S/A

Y-G ati ng

I/O Buffers & Latches

Global Buffers

1 Block = 64 Pages
(128K + 4k) Byte

Output

Driver

VCC
VSS

I/0 0

I/0 7

128K Pages
(=2,048 Blocks)

2K Bytes 64 Bytes

Page Register

2K Bytes

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

1st Cycle A

2nd Cycle A8 A9 A10 A11 *L *L *L *L

3rd Cycle A

4th Cycle A20 A21 A22 A23 A24 A25 A26 A27

5th Cycle A28 *L *L *L *L *L *L *L

NOTE : Column Address : Starting Address of the Register.

* L must be set to "Low".

* The device ignores any additional input of address cycles than required.

0 A1 A2 A3 A4 A5 A6 A7

12 A13 A14 A15 A16 A17 A18 A19

1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 64 Pages
= (128K + 4K) Bytes
1 Device = (2K+64)B x 64Pages x 2048 Blocks
= 2112 Mbits

8 bit

I/O 0 ~ I/O 7

64 Bytes

Column Address

Column Address

Row Address

Row Address

Row Address

8

K9K2G08U0A

K9K2G08R0A

Product Introduction

The K9K2G08X0A is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8 columns. Spare 64 col­umns are located from column address of 2048~2111. A 2112-byte data register is connected to memory cell arrays for accommodat­ing data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is
made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block
consists of two NAND structures. A NAND structure consists of 32 cells. Total 135,168 NAND cells reside in a block. The program and
read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of
2048 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K2G08X0A.

The K9K2G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command and etc require just one cycle bus. Some other commands, like Page Read, Block
Erase and Page Program, require two cycles: one cycle for setup and the other cycle for execution. The 264M byte physical space
requires 29 addresses, thereby requiring five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order.
Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation,
however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command
register. Table 1 defines the specific commands of the K9K2G08X0A.

to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

FLASH MEMORY

Table 1. Command Sets

Function 1st. Cycle 2nd. Cycle Acceptable Command during Busy

Read 00h 30h

Read for Copy Back 00h 35h

Read ID 90h -

Reset FFh - O

Page Program 80h 10h

Cache Program 80h 15h

Copy-Back Program 85h 10h

Block Erase 60h D0h

Random Data Input

Random Data Output

Read Status 70h O

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Cache program and Copy-Back program are supported only with 3.3V device.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

*1

*1

85h -

05h E0h

9

K9K2G08U0A

K9K2G08R0A

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Voltage on any pin relative to V

Temperature Under
Bias

Storage Temperature

K9K2G08X0A-XCB0

K9K2G08X0A-XIB0 -40 to +125

K9K2G08X0A-XCB0

K9K2G08X0A-XJIB0

SS

VIN/OUT -0.6 to + 2.45 -0.6 to + 4.6

V

CC -0.6 to + 2.45 -0.6 to + 4.6

T

BIAS

T

STG -65 to +150 °C

Short Circuit Current Ios 5 mA

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is V

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

CC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

1.8V DEVICE 3.3V DEVICE

-10 to +125

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, :TA=0 to 70°C, K9K2G08X0A-XIB0:TA=-40 to 85°C)

Parameter Symbol

Supply Voltage V

Supply Voltage V

CC 1.65 1.8 1.95 2.7 3.3 3.6 V

SS 000000V

K9K2G08R0A(1.8V) K9K2G08U0A(3.3V)

Min Typ . Max Min Ty p. Max

FLASH MEMORY

Rating

Unit

V

°C

Unit

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

Parameter Symbol Test Conditions

Operat-

Current

Page Read with
Serial Access

ing

Program I

Erase I

Stand-by Current(TTL) I

Stand-by Current(CMOS) I

Input Leakage Current I

Output Leakage Current I

Input High Voltage V

Input Low Voltage, All
inputs

Output High Voltage

Level

Output Low Voltage Level V

Output Low Current(R/B

)IOL(R/B)

tRC=50ns, (30ns with 3.3V device)

I

CC1

CE=VIL
IOUT=0mA

CC2 - - 10 20 - 10 30

CC3 - - 10 20 - 10 30

SB1CE=VIH, WP=0V/VCC -- 1 --1

CE

SB2

LI VIN=0 to Vcc(max) - - ±20 - - ±10

LO VOUT=0 to Vcc(max) - - ±20 - - ±10

IH - 0.8xVcc - Vcc+0.3 0.8xVcc - Vcc+0.3

V

IL - -0.3 - 0.2xVcc -0.3 - 0.2xVcc

OH

V

OL

=VCC-0.2,

=0V/VCC

WP

K9K2G08R0A: IOH=-100µA

K9K2G08U0A: I

K9K2G08R0A: IOL=100mA

K9K2G08U0A: I

K9K2G08R0A: V

K9K2G08U0A: V

OH=-400µA

OL=2.1mA

OL=0.1V

OL=0.4V

K9K2G08R0A(1.8V) K9K2G08U0A(3.3V)

Min Typ Max Min Typ Max

- 10 20 - 10 30

- 20 100 - 20 100

Vcc-0.1 - - 2.4 - -

--0.1 --0.4

34 - 810-mA

Unit

mA

µA

V

10

K9K2G08U0A

K9K2G08R0A

VALID BLOCK

Parameter Symbol Min Ty p. Max Unit

Valid Block Number N

NOTE :

1. The

K9K2G08X0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid

blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits

or program factory-marked bad blocks.

2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction up to 1K Program/
Earase cycles..

VB 2008 - 2048 Blocks

Refer to the attached technical notes for appropriate management of invalid blocks.

AC TEST CONDITION

(K9K2G08X0A-XCB0 :TA=0 to 70°C, K9K2G08X0A-XIB0:TA=-40 to 85°C
K9K2G08R0A : Vcc=1.65V~1.95V, K9K2G08U0A : Vcc=2.7V~3.6Vunless otherwise noted)

Parameter K9K2G08R0A K9K2G08U0A

Input Pulse Levels 0V to Vcc 0V to Vcc

Input Rise and Fall Times 5ns 5ns

Input and Output Timing Levels Vcc/2 Vcc/2

Output Load 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF

CAPACITANCE(TA=25C, VCC=1.8V/3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance C

Input Capacitance C

NOTE : Capacitance is periodically sampled and not 100% tested.

I/O VIL=0V - 20 pF

IN VIN=0V - 20 pF

FLASH MEMORY

. Do not erase

MODE SELECTION

CLE ALE CE WE RE WP Mode

HLL HX

Read Mode

Command Input

L H L H X Address Input(5clock)

HLL HH

Write Mode

Command Input

L H L H H Address Input(5clock)

L L L H H Data Input

LLLH X Data Output

X X X X H X During Read(Busy)

XXXXXH During Program(Busy)

XXXXXH During Erase(Busy)

X

XXHXX

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

(1)

X

X X X L Write Protect

(2)

CC

Stand-by

0V/V

Program / Erase Characteristics

Parameter Symbol Min Typ Max Unit

Program Time

Dummy Busy Time for Cache Program

Number of Partial Program Cycles
in the Same Page

Main Array

Spare Array - - 4 cycles

Block Erase Time t

NOTE : 1.Typical program time is defined as the time within which more than 50% of whole pages are programmed at Vcc of 3.3V and 25°C

2. Max. time of tCBSY depends on timing between internal program completion and data in

*1

PROG

t

*2

t

CBSY

Nop

BERS -23ms

- 200 700 µs

3700

--4cycles

µs

11

K9K2G08U0A

K9K2G08R0A

AC Timing Characteristics for Command / Address / Data Input

Parameter Symbol

CLE setup Time

CLE Hold Time t

setup Time

CE

CE

Hold Time tCH 10 5 - - ns

WE

Pulse Width tWP 25 15 - - ns

ALE setup Time

ALE Hold Time t

Data setup Time

Data Hold Time t

Write Cycle Time t

WE

High Hold Time tWH 15 10 - - ns

Address to Data Loading Time

CLS

t

CLH 10 5 - - ns

CS

t

t

ALS

ALH 10 5 - - ns

DS

t

DH 10 5 - - ns

WC 45 30 - - ns

ADL

t

K9K2G08R0A K9K2G08U0A K9K2G08R0A K9K2G08U0A

*1

*1

*1

*1

*2

25 15 - - ns

35 20 - - ns

25 15 - - ns

20 15 - - ns

100

Min Max

*2

100

*2

FLASH MEMORY

--ns

Unit

NOTE : 1. The transition of the corresponding control pins must occur only once while WE is held low.

2. tADL is the time from the WE

3. For cache program operation, the whole AC Charcateristics must be same as that of K9K2G08R0A.

rising edge of final address cycle to the WE rising edge of first data cycle.

AC Characteristics for Operation

Parameter Symbol

K9K2G08R0A K9K2G08U0A K9K2G08R0A K9K2G08U0A

Data Transfer from Cell to Register tR - - 25 25 µs

ALE to RE

CLE to RE

Ready to RE

RE Pulse Width t

WE High to Busy t

Read Cycle Time t

RE

CE

RE

CE

RE

RE

Output Hi-Z to RE

WE

Device Resetting Time (Read/Program/Erase) t

Delay tAR 10 10 - - ns

Delay tCLR 10 10 - - ns

Low tRR 20 20 - - ns

RP 25 15 - - ns

WB - - 100 100 ns

RC 50 30 - - ns

Access Time tREA - - 30 20 ns

Access Time tCEA - - 45 35 ns

High to Output Hi-Z tRHZ - - 30 30 ns

High to Output Hi-Z tCHZ - - 20 20 ns

or CE High to Output hold tOH 15 15 - - ns

High Hold Time tREH 15 10 - - ns

Low tIR 00 - -ns

High to RE Low tWHR 60 60 - - ns

RST --

Min Max

5/10/500

*1

5/10/500

*1

Unit

µs

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

2. For cache program operation, the whole AC Charcateristics must be same as that of K9K2G08R0A.

12

K9K2G08U0A

K9K2G08R0A

NAND Flash Technical Notes

Initial Invalid Block(s)

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid
block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid
block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a
select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is
placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase
cycles.

Identifying Initial Invalid Block(s)

All device locations are erased except locations where the initial invalid block(s) information is written prior to shipping. The initial
invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial
invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most
cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial
invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.

Start

FLASH MEMORY

Increment Block Address

Create (or update)

Initial Invalid Block(s) Table

Figure 3. Flow chart to create initial invalid block table.

Set Block Address = 0

No

No

Check "FFh ?

Yes

Last Block ?

Yes

End

Check "FFh" at the column address

2048 of the 1st and 2nd page in the block

*

13

K9K2G08U0A

K9K2G08R0A

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block fail­ure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read
failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be
employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be
reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those reclaimed
blocks.

Failure Mode Detection and Countermeasure sequence

Write

Read Single Bit Failure Verify ECC -> ECC Correction

Erase Failure Status Read after Erase --> Block Replacement

Program Failure Status Read after Program --> Block Replacement

FLASH MEMORY

ECC

Program Flow Chart

: Error Correcting Code --> Hamming Code etc.
Example) 1bit correction & 2bit detection

Start

Write 80h

Write Address

Write Data

Write 10h

Read Status Register

I/O 6 = 1 ?

or R/B = 1 ?

No

*

Program Error

No

I/O 0 = 0 ?

P

rogram Completed

Yes

Yes

: If program operation results in an error, map out

*

the block including the page in error and copy the
target data to another block.

14

K9K2G08U0A

K9K2G08R0A

NAND Flash Technical Notes (Continued)

FLASH MEMORY

Erase Flow Chart

*

Erase Error

No

Start

Write 60h

Write Block Address

Write D0h

Read Status Register

I/O 6 = 1 ?

or R/B = 1 ?

Yes

I/O 0 = 0 ?

Yes

No

Read Flow Chart

Reclaim the Error

Start

Write 00h

Write Address

Write 30h

Read Data

ECC Generation

No

Verify ECC

Yes

Page Read Completed

Erase Completed

: If erase operation results in an error, map out

*

the failing block and replace it with another block.

Block Replacement

Block A

1st

∼

{

(n-1)th

nth

(page)

1st

∼

(n-1)th

nth

(page)

* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

an error occurs.

Block B

{

1

Buffer memory of the controller.

2

15

K9K2G08U0A

K9K2G08R0A

NAND Flash Technical Notes (Continued)

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most sig­nificant bit) pages of the block. Random page address programming is prohibited.

FLASH MEMORY

Page 63

Page 31

Page 2
Page 1
Page 0

From the LSB page to MSB page

DATA IN: Data (1)

(64)

:

(32)

:

(3)
(2)
(1)

Data register

Data (64)

Page 63

Page 31

Page 2
Page 1
Page 0

Ex.) Random page program (Prohibition)

DATA IN: Data (1)

(64)

:

(1)

:

(3)

(32)

(2)

Data register

Data (64)

16

K9K2G08U0A

K9K2G08R0A

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of µ-seconds, de-activating CE
would provide significant savings in power consumption.

Figure 4. Program Operation with CE don’t-care.

CLE

CE don’t-care

CE

FLASH MEMORY

during the data-loading and serial access

WE

ALE

I/Ox

CE

WE

80h Data Input

Address(5Cycles)

tCS

tWP

tCH

Figure 5. Read Operation with CE don’t-care.

CLE

CE

≈

CE

RE

I/O0~7

tCEA

tREA

CE

don’t-care

≈

Data Input

out

10h

RE

ALE

R/B

WE

I/Ox

≈

tR

Address(5Cycle)00h

30h

17

Data Output(serial access)

K9K2G08U0A

K9K2G08R0A

NOTE

Device

K9K2G08X0A I/O 0 ~ I/O 7 ~2112byte A0~A7 A8~A11 A12~A19 A20~A27 A28

I/O DATA ADDRESS

I/Ox Data In/Out Col. Add1 Col. Add2 Row Add1 Row Add2 Row Add3

Command Latch Cycle

FLASH MEMORY

CLE

CE

WE

ALE

I/Ox

Address Latch Cycle

CLE

tCLS

tCLS

tCS

tALS

tWP

tDS

Command

tCLH

tCH

tALH

tDH

CE

WE

ALE

I/Ox

tCS

tALS

tWP

tDS

Col. Add1

tWC

tALH

tDH

tWH

tWP

tALS

18

tWC

tALH

tDH

tDS

Col. Add2

tWH

tWP

tALS

Row Add1

tDS

tWC

tALH

tDH

tWH

tWP

tALS

tDS

Row Add2

tALH

tDH

K9K2G08U0A

Input Data Latch Cycle

CLE

CE

K9K2G08R0A

FLASH MEMORY

tCLH

≈

tCH

≈

ALE

WE

I/Ox

tALS

tWP

tWC

tWH

tDH

tDS

DIN 0

NOTES : DIN final means 2112

tWP

tDS

DIN 1

tDH

Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

CE

RE

tCEA

tREA

tREH

tREA

≈

≈

tWP

≈

≈

tDH

tDS

DIN final*

≈≈≈≈

tREA

tCHZ*

tOH

I/Ox

R/B

tRHZ*

Dout

tRR

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

tRC

Dout

19

tRHZ*
tOH

Dout

K9K2G08U0A

Status Read Cycle

CLE

CE

WE

RE

I/Ox

K9K2G08R0A

tCLS

tCS

tWP

tDS

70h

tCLH

tCH

tDH

tWHR

tCLR

tIR*

tCEA

FLASH MEMORY

tCHZ*

tOH

tREA

Status Output

tRHZ*

tOH

20

K9K2G08U0A

Read Operation

CLE

CE

tWC

WE

ALE

K9K2G08R0A

FLASH MEMORY

tCLR

tWB

tAR

tR

tRC

tRHZ

RE

I/Ox

00h

Col. Add1

Col. Add2

Column Address

Row Add1

R/B

Read Operation(Intercepted by CE)

CLE

CE

WE

ALE

Row Add2

Row Address

Row Add3

30h

tRR

Busy

tWB

tAR

Dout N

Dout N+1

≈

tCHZ
tOH

≈≈

Dout M

RE

I/Ox

R/B

00h

Col. Add1

Column Address

Col. Add2 Row Add1

Row Address

Row Add2

Row Add3

21

30h

tR

tRR

Busy

Dout N

tRC

Dout N+1

Dout N+2

K9K2G08U0A

K9K2G08R0A

Dout M+1

FLASH MEMORY

tCLR

B
W

t

tWHR

tAR

tREA

C
R

t

tR

tRR

Dout M

E0h

Col Add2

Col Add1

Column Address

Dout N Dout N+1

30h 05h

Busy

Random Data Output In a Page

CLE

CE

WE

ALE

22

RE

Row Add3

Row Add2

Row Address

Row Add1

Col. Add2

Col. Add1

Column Address

00h

I/Ox

R/B

K9K2G08U0A

Page Program Operation

CLE

CE

tWC

WE

ALE

RE

I/Ox

R/B

80h

SerialData

Input Command

Co.l Add1 Col. Add2 Row Add1 Row Add 2 Row Add3

Column Address Row Address

tWC

K9K2G08R0A

FLASH MEMORY

tWC

≈

tPROG

tADL

1 up to m Byte

≈

Din

N

≈

Serial Input

m = 2112byte

Din

M

tWB

10h

Program
Command

70h I/O

Read Status
Command

≈

I/O

0

=0 Successful Program

I/O

0

=1 Error in Program

0

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

23

K9K2G08U0A

K9K2G08R0A

0

Read Status

Command

FLASH MEMORY

≈

tPROG

tWB

10h

Program

Command

K

Din

≈

≈

tADL

≈

Din

Serial Input

J

tWC

tWC

Col. Add2

Column Address

Col. Add1

85h

Random Data

Input Command

M

Din

≈

≈≈

N

Din

Serial Input

tADL

Row Add3

rising edge of final address cycle to the WE rising edge of first data cycle.

Row Add2

Row Add1

Col. Add2

Column Address Row Address

Col. Add1

Page Program Operation with Random Data Input

CLE

CE

tWC

WE

ALE

RE

24

80h 70h I/O

I/Ox

Serial Data

Input Command

NOTES : tADL is the time from the WE

R/B

K9K2G08U0A

K9K2G08R0A

0

Read Status

Command

tPROG

≈

Busy

=0 Successful Program

=1 Error in Program

0

0

I/O

I/O

FLASH MEMORY

tWB

10h

Data N

≈ ≈

Data 1

tADL

Row Add3

Row Add2

Row Address

Row Add1

tWC

tWB

Col Add2

Col Add1

Column Address

85h

≈

Copy-Back Data

Input Command

tR

35h

Row Add3

Row Add2

Row Address

Row Add1

Col Add2

Col Add1

Column Address

00h 70h I/O

Busy

rising edge of final address cycle to the WE rising edge of first data cycle.

NOTES : tADL is the time from the WE

Copy-Back Program Operation With Random Data Input

CLE

CE

WE

ALE

RE

I/Ox

R/B

25

K9K2G08U0A

K9K2G08R0A

FLASH MEMORY

≈

tCPROG

tWB

I/O

70h

tPROG

70h

10h

≈

Address &

Data Input

10h

(True)

Command

Program Confirm

M

Din

80h

≈≈

N

Din

tADL

Row Add3

Row Add2

Row Add1

Col Add2

Col Add1

80h

Last Page Input & Program

tCBSY

tCBSY

15h

Address &

Data Input

80h

15h

Cache Program Operation(available only within a block)

CLE

CE

Address &

≈

tCBSY

tWB

15h

Program

Command

(Dummy)

M

Din

tADL

RE

≈≈

N

Din

Row Add3

Row Add2

Row Add1

Col Add2

Col Add1

80h

I/Ox

Serial Input

Row Address

Column Address

Serial Data

Input Command

Max. 63 times repeatable

R/B

≈

tWC

WE

ALE

CBSY :

max. 700us

t

tCBSY

Ex.) Cache Program

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

R/B

Data Input

80h

15h

Address &

Data Input

Col Add1,2 & Row Add1,2

80h

I/Ox

Data

26

K9K2G08U0A

Block Erase Operation

CLE

CE

tWC

WE

ALE

RE

K9K2G08R0A

tWB

tBERS

FLASH MEMORY

I/Ox

R/B

Row Add1

60h

Auto Block Erase
Setup Command

Row Add2 Row Add3

Row Address

D0h 70h I/O 0

Busy

Erase Command

≈

Read Status
Command

I/O0=0 Successful Erase
I/O

0

=1 Error in Erase

27

K9K2G08U0A

Read ID Operation

CLE

CE

WE

K9K2G08R0A

FLASH MEMORY

ALE

RE

I/Ox

Read ID Command Maker Code

90h

Address. 1cycle

Device Device Code*(2nd Cycle) 4th Cycle*

K9K2G08R0A AAh 15h

K9K2G08U0A DAh 15h

ID Defintition Table

90 ID : Access command = 90H

tAR

tREA

00h ECh

Device
Code*

Device Code

XXh

4th cyc.*

st

1

nd

2

rd

3

th

4

Byte

Byte

Byte

Byte

Description

Maker Code
Device Code
Don’t care
Page Size, Block Size, Spare Size, Organization

28

K9K2G08U0A

4th ID Data

Page Size
(w/o redundant area )

Blcok Size
(w/o redundant area )

Redundant Area Size
( byte/512byte)

Organization

Serial AccessMinimum

K9K2G08R0A

Description I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

1KB
2KB
Reserved
Reserved

64KB
128KB
256KB
Reserved

8
16

x8
x16

50ns
Reserved
Reserved
Reserved

0
1
0
1

0 0
0 1
1 0
1 1

0
1

FLASH MEMORY

0 0
0 1
1 0
1 1

0
1

0
0
1
1

29

K9K2G08U0A

K9K2G08R0A

Device Operation

PAG E R EA D

Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 25µs(t
this data transfer(tR) by analyzing the output of R/B
out in 50ns cycle time by sequentially pulsing RE
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com­mand. Random data output can be operated multiple times regardless of how many times it is done in a page.

pin. Once the data in a page is loaded into the data registers, they may be read

. The repetitive high to low transitions of the RE clock make the device output the

R). The system controller can detect the completion of

Figure 6. Read Operation

CLE

CE

FLASH MEMORY

WE

ALE

R/B

RE

I/Ox

Address(5Cycle)00h

Col Add1,2 & Row Add1,2,3

tR

30h

Data Field Spare Field

Data Output(Serial Access)

30