Philips MINI X5 SERVICE MANUAL

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A

K9K2G08X0A

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ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1.For updates or additional information about Samsung products, contact your nearest Samsung office.

2.Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1

K9K2G08U0A				FLASH MEMORY
K9K2G08R0A
Document Title
256M x 8 Bit NAND Flash Memory
Revision History
Revision No	History			Draft Date			Remark
0.0	1.	Initial issue		May. 31. 2004			Advance
0.1	1.	Technical note is changed		Oct. 25. 2004			Preliminary
	2.	Notes of AC timing characteristics are added
	3.	The description of Copy-back program is changed
	4.	TSOP package is deleted
0.2	1.		access time : 23ns->35ns (p.9)	Feb. 14. 2005
		CE
0.3	1.	The value of tREA is changed. (18ns->20ns)		May	4	2005
	2.	EDO mode is added.
0.4	1.	The flow chart to creat the initial invalid block table is changed.		May	6	2005
1.0	1.	1.8V FBGA spec is merged		Feb. 1 2006
	2.	3.3V FBGA package is added
	3.	FBGA package size is changed to 9.5 x 12
	4.	Leaded part is deleted

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.

2

K9K2G08U0A			FLASH MEMORY
K9K2G08R0A
256M x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number	Vcc Range	Organization	PKG Type
K9K2G08U0A-F	2.7 ~ 3.6V	X8	WSOP1
K9K2G08X0A-J	1.65 ~ 1.95V	X8	FBGA

FEATURES
• Voltage Supply	• Fast Write Cycle Time
- 2.7 V ~3.6 V	- Program time : 300µs(Typ.)
- 1.65V ~ 1.95V	- Block Erase Time : 2ms(Typ.)
• Organization	• Command/Address/Data Multiplexed I/O Port
- Memory Cell Array	• Hardware Data Protection
- (256M + 8,192K)bit x 8bit	- Program/Erase Lockout During Power Transitions
- Data Register	• Reliable CMOS Floating-Gate Technology
- (2K + 64)bit x8bit	- Endurance : 100K Program/Erase Cycles
• Automatic Program and Erase	- Data Retention : 10 Years
- Page Program	• Command Register Operation
- (2K + 64)Byte	• Unique ID for Copyright Protection
- Block Erase	• Package :
- (128K + 4K)Byte	- K9K2G08U0A-FIB0
• Page Read Operation	48 - Pin WSOP I (12x17x0.7mm)- Pb-free Package
- Page Size	- K9K2G08X0A-JCB0/JIB0
- 2K-Byte	63Ball FBGA (9.5x12) - Pb-free Package
- Random Read : 25µs(Max.)
- Serial Access : 50ns(Min.)

GENERAL DESCRIPTION

Offered in 256Mx8bit the K9K2G08X0A is 2G bit with spare 64M bit capacity. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 300µs on the 2112byte page and an erase operation can be performed in typical 2ms on a 128K-byte block. Data in the data page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9K2G08X0A′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9K2G08X0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

3

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A

PIN CONFIGURATION (WSOP1)
	K9K2G08U0A-FIB0
N.C	1	48	N.C
N.C	2	47	N.C
DNU	3	46	DNU
N.C	4	45	N.C
N.C	5	44	I/O7
N.C	6	43	I/O6
R/B	7	42	I/O5
RE	8	41	I/O4
CE	9	40	N.C
DNU	10	39	DNU
N.C	11	38	N.C
Vcc	12	37	Vcc
Vss	13	36	Vss
N.C	14	35	N.C
DNU	15	34	DNU
CLE	16	33	N.C
ALE	17	32	I/O3
WE	18	31	I/O2
WP	19	30	I/O1
N.C	20	29	I/O0
N.C	21	28	N.C
DNU	22	27	DNU
N.C	23	26	N.C
N.C	24	25	N.C
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I)
48 - WSOP1 - 1217F			Unit :mm
			0.70 MAX
	15.40±0.10		0.58±0.04
#1		#48
+0.07 -0.03
0.16
+0.07 -0.03			10.0±00.12	40MAX.12
0.20
0.50TYP (0.50±0.06)
#24		#25
			(0.01Min)
		+0.075 -0.035		8
		0.10
				0
				°
				~
				°
			0.45~0.75
	17.00±0.20

4

K9K2G08U0A								FLASH MEMORY
K9K2G08R0A
PIN CONFIGURATION (FBGA)
		K9F1G08X0A-JCB0/JIB0
		1	2	3	4	5	6
	N.C	N.C					N.C N.C
A	N.C						N.C N.C
		/WP	ALE	Vss	/CE	/WE	R/B
B
		NC	/RE	CLE	NC	NC	NC
C
		NC	NC	NC	NC	NC	NC
D
		NC	NC	NC	NC	NC	NC
E
		NC	NC	NC	NC	NC	NC
F
		NC	I/O0	NC	NC	NC	Vcc
G
		NC	I/O1	NC	Vcc	I/O5	I/O7
H
		Vss	I/O2	I/O3	I/O4	I/O6	Vss
	N.C	N.C					N.C N.C
	N.C	N.C					N.C N.C

Top View

5

K9K2G08U0A					FLASH MEMORY
K9K2G08R0A
PACKAGE DEMENSIONS(FBGA)
Top View			Bottom View
						#A1 INDEX MARK(OPTIONAL)
				9.50±0.10				A
			0.80 x 9= 7.20
			0.80 x 5= 4.00
9.50±0.10		6	5	0.80	3	2	1			B
				4
	(Datum A)
#A1								0.80
		A
		B
12.00±0.10	(Datum B)	C						0.80 x 7= 5.60	0.80 x 11= 8.80	12.00±0.10
		D
		E
	2.80	F
		G
		H
	63- 0.45±0.05
	0.20 M A B
			2.00
	Side View						(Min.)	(Max)
	12.00±0.10						0.25	1.20
0.10MAX			0.45±0.05
	6

K9K2G08U0A

FLASH MEMORY

K9K2G08R0A

PIN DESCRIPTION

Pin Name

Pin Function

DATA INPUTS/OUTPUTS

I/O0 ~ I/O7

The I/O pins are used to input command, address and data, and to output data during read operations. The

I/O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

CLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

ALE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CHIP ENABLE

The CE input is the device selection control. When the device is in the Busy state,

CE

high is ignored, and

CE

the device does not return to standby mode in program or erase opertion. Regarding CE control during read

operation, refer to ’Page read’ section of Device operation .

READ ENABLE

RE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

WE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the

WE

pulse.

WRITE PROTECT

WP

The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage

generator is reset when the WP pin is active low.

READY/BUSY OUTPUT

The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or

R/B

random read operation is in process and returns to high state upon completion. It is an open drain output

and does not float to high-z condition when the chip is deselected or when outputs are disabled.

Vcc

POWER

VCC is the power supply for device.

Vss

GROUND

N.C

NO CONNECTION

Lead is not internally connected.

NOTE:

1.Connect all VCC and VSS pins of each device to common power supply outputs.

2.Do not leave VCC or VSS disconnected.

7

K9K2G08U0A		FLASH MEMORY
K9K2G08R0A
Figure 1. Functional Block Diagram
VCC
VSS
A12 - A28	X-Buffers	2048M + 64M Bit
		NAND Flash
	Latches	ARRAY
	& Decoders
A0 - A11	Y-Buffers	(2048 + 64)Byte x 131072
	Latches
	& Decoders	Data Register & S/A
		Y-Gating
Command	Command
	Register	I/O Buffers & Latches		VCC
				VSS
CE	Control Logic
RE	& High Voltage		Output	I/0 0
WE	Generator	Global Buffers
			Driver
				I/0 7
	CLE ALE WP
Figure 2 Array Organization
		1 Block = 64 Pages
		(128K + 4k) Byte
		1 Page = (2K + 64)Bytes
128K Pages		1 Block = (2K + 64)B x 64 Pages
		= (128K + 4K) Bytes
(=2,048 Blocks)		1 Device = (2K+64)B x 64Pages x 2048 Blocks
		= 2112 Mbits
		8 bit

2K Bytes

64 Bytes

									I/O 0 ~ I/O 7
		Page Register
		2K Bytes				64 Bytes

	I/O 0	I/O 1	I/O 2	I/O 3	I/O 4	I/O 5	I/O 6	I/O 7
1st Cycle	A0	A1	A2	A3	A4	A5	A6	A7
2nd Cycle	A8	A9	A10	A11	*L	*L	*L	*L
3rd Cycle	A12	A13	A14	A15	A16	A17	A18	A19
4th Cycle	A20	A21	A22	A23	A24	A25	A26	A27
5th Cycle	A28	*L	*L	*L	*L	*L	*L	*L

NOTE : Column Address : Starting Address of the Register.

*L must be set to "Low".

*The device ignores any additional input of address cycles than required.

Column Address

Column Address

Row Address

Row Address

Row Address

8

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A

Product Introduction

The K9K2G08X0A is a 2112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2112x8 columns. Spare 64 columns are located from column address of 2048~2111. A 2112-byte data register is connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block consists of two NAND structures. A NAND structure consists of 32 cells. Total 135,168 NAND cells reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9K2G08X0A.

The K9K2G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command and etc require just one cycle bus. Some other commands, like Page Read, Block Erase and Page Program, require two cycles: one cycle for setup and the other cycle for execution. The 264M byte physical space requires 29 addresses, thereby requiring five cycles for addressing: 2 cycles of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9K2G08X0A.

Table 1. Command Sets

Function	1st. Cycle	2nd. Cycle	Acceptable Command during Busy
Read	00h	30h
Read for Copy Back	00h	35h
Read ID	90h	-
Reset	FFh	-	O
Page Program	80h	10h
Cache Program	80h	15h
Copy-Back Program	85h	10h
Block Erase	60h	D0h
Random Data Input*1	85h	-
Random Data Output*1	05h	E0h
Read Status	70h		O

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Cache program and Copy-Back program are supported only with 3.3V device.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

9

K9K2G08U0A					FLASH MEMORY
K9K2G08R0A
ABSOLUTE MAXIMUM RATINGS
Parameter		Symbol		Rating			Unit
			1.8V DEVICE			3.3V DEVICE
Voltage on any pin relative to VSS		VIN/OUT	-0.6 to + 2.45			-0.6 to + 4.6	V
		VCC	-0.6 to + 2.45			-0.6 to + 4.6
Temperature Under	K9K2G08X0A-XCB0	TBIAS		-10 to +125			°C
Bias	K9K2G08X0A-XIB0			-40 to +125
Storage Temperature	K9K2G08X0A-XCB0	TSTG		-65 to +150			°C
	K9K2G08X0A-XJIB0
Short Circuit Current		Ios		5			mA

NOTE :

1.Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC,+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

2.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND, :TA=0 to 70°C, K9K2G08X0A-XIB0:TA=-40 to 85°C)

Parameter	Symbol		K9K2G08R0A(1.8V)					K9K2G08U0A(3.3V)				Unit
		Min		Typ.		Max	Min		Typ.		Max
Supply Voltage	VCC	1.65		1.8		1.95	2.7		3.3		3.6	V
Supply Voltage	VSS	0		0		0	0		0		0	V

DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)

	Parameter				Symbol					Test Conditions			K9K2G08R0A(1.8V)			K9K2G08U0A(3.3V)			Unit
													Min	Typ	Max	Min	Typ	Max
	Operat-	Page Read with			ICC1				tRC=50ns, (30ns with 3.3V device)
									CE=VIL				-	10	20	-	10	30
	ing	Serial Access							IOUT=0mA
	Current																		mA
		Program			ICC2				-				-	10	20	-	10	30
		Erase			ICC3				-				-	10	20	-	10	30
	Stand-by Current(TTL)				ISB1								-	-	1	-	-	1
									CE=VIH, WP=0V/VCC
	Stand-by Current(CMOS)				ISB2				CE=VCC-0.2,				-	20	100	-	20	100
									WP=0V/VCC										µA
	Input Leakage Current				ILI				VIN=0 to Vcc(max)				-	-	±20	-	-	±10
	Output Leakage Current				ILO				VOUT=0 to Vcc(max)				-	-	±20	-	-	±10
	Input High Voltage				VIH				-				0.8xVcc	-	Vcc+0.3	0.8xVcc	-	Vcc+0.3
	Input Low Voltage, All				VIL				-				-0.3	-	0.2xVcc	-0.3	-	0.2xVcc
	inputs
																			V
	Output High Voltage				VOH				K9K2G08R0A: IOH=-100µA				Vcc-0.1	-	-	2.4	-	-
	Level								K9K2G08U0A: IOH=-400µA
	Output Low Voltage Level				VOL				K9K2G08R0A: IOL=100mA				-	-	0.1	-	-	0.4
									K9K2G08U0A: IOL=2.1mA
	Output Low Current(R/B)								K9K2G08R0A: VOL=0.1V				3	4	-	8	10	-	mA
					IOL(R/B)
									K9K2G08U0A: VOL=0.4V

10

K9K2G08U0A				FLASH MEMORY
K9K2G08R0A
VALID BLOCK
Parameter	Symbol	Min	Typ.	Max	Unit
Valid Block Number	NVB	2008	-	2048	Blocks

NOTE :

1.The K9K2G08X0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks.

2.The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block and does not require Error Correction up to 1K Program/ Earase cycles..

AC TEST CONDITION

(K9K2G08X0A-XCB0 :TA=0 to 70°C, K9K2G08X0A-XIB0:TA=-40 to 85°C

K9K2G08R0A : Vcc=1.65V~1.95V, K9K2G08U0A : Vcc=2.7V~3.6Vunless otherwise noted)

Parameter	K9K2G08R0A	K9K2G08U0A
Input Pulse Levels	0V to Vcc	0V to Vcc
Input Rise and Fall Times	5ns	5ns
Input and Output Timing Levels	Vcc/2	Vcc/2
Output Load	1 TTL GATE and CL=30pF	1 TTL GATE and CL=50pF

CAPACITANCE(TA=25C, VCC=1.8V/3.3V, f=1.0MHz)

Item	Symbol	Test Condition	Min	Max	Unit
Input/Output Capacitance	CI/O	VIL=0V	-	20	pF
Input Capacitance	CIN	VIN=0V	-	20	pF

NOTE : Capacitance is periodically sampled and not 100% tested.

MODE SELECTION

CLE	ALE	CE	WE	RE	WP		Mode
H	L	L		H	X	Read Mode	Command Input
L	H	L		H	X		Address Input(5clock)
H	L	L		H	H	Write Mode	Command Input
L	H	L		H	H		Address Input(5clock)
L	L	L		H	H	Data Input
L	L	L	H		X	Data Output
X	X	X	X	H	X	During Read(Busy)
X	X	X	X	X	H	During Program(Busy)
X	X	X	X	X	H	During Erase(Busy)
X	X(1)	X	X	X	L	Write Protect
X	X	H	X	X	0V/VCC(2)	Stand-by

NOTE : 1. X can be VIL or VIH.

2. WP should be biased to CMOS high or CMOS low for standby.

Program / Erase Characteristics

	Parameter		Symbol	Min	Typ	Max	Unit
	Program Time		tPROG*1	-	200	700	µs
	Dummy Busy Time for Cache Program		tCBSY*2		3	700	µs
	Number of Partial Program Cycles	Main Array	Nop	-	-	4	cycles
	in the Same Page	Spare Array		-	-	4	cycles
	Block Erase Time		tBERS	-	2	3	ms

NOTE : 1.Typical program time is defined as the time within which more than 50% of whole pages are programmed at Vcc of 3.3V and 25°C 2. Max. time of tCBSY depends on timing between internal program completion and data in

11

K9K2G08U0A							FLASH MEMORY
K9K2G08R0A
AC Timing Characteristics for Command / Address / Data Input
		Parameter	Symbol		Min			Max		Unit
				K9K2G08R0A		K9K2G08U0A	K9K2G08R0A		K9K2G08U0A
CLE setup Time			tCLS*1	25		15	-		-	ns
CLE Hold Time			tCLH	10		5	-		-	ns
		setup Time	tCS*1	35		20	-		-	ns
CE
		Hold Time	tCH	10		5	-		-	ns
CE
		Pulse Width	tWP	25		15	-		-	ns
WE
ALE setup Time			tALS*1	25		15	-		-	ns
ALE Hold Time			tALH	10		5	-		-	ns
Data setup Time			tDS*1	20		15	-		-	ns
Data Hold Time			tDH	10		5	-		-	ns
Write Cycle Time			tWC	45		30	-		-	ns
		High Hold Time	tWH	15		10	-		-	ns
WE
Address to Data Loading Time			tADL*2	100*2		100*2	-		-	ns

NOTE : 1. The transition of the corresponding control pins must occur only once while WE is held low.

2.tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

3.For cache program operation, the whole AC Charcateristics must be same as that of K9K2G08R0A.

AC Characteristics for Operation

															Parameter	Symbol	Min		Max		Unit
																	K9K2G08R0A	K9K2G08U0A	K9K2G08R0A	K9K2G08U0A
	Data Transfer from Cell to Register															tR	-	-	25	25	µs
	ALE to									Delay						tAR	10	10	-	-	ns
					RE
	CLE to									Delay						tCLR	10	10	-	-	ns
						RE
	Ready to											Low				tRR	20	20	-	-	ns
								RE
	RE Pulse Width															tRP	25	15	-	-	ns
	WE High to Busy															tWB	-	-	100	100	ns
	Read Cycle Time															tRC	50	30	-	-	ns
			Access Time													tREA	-	-	30	20	ns
	RE
			Access Time													tCEA	-	-	45	35	ns
	CE
			High to Output Hi-Z													tRHZ	-	-	30	30	ns
	RE
			High to Output Hi-Z													tCHZ	-	-	20	20	ns
	CE
			or				High to Output hold									tOH	15	15	-	-	ns
	RE			CE
			High Hold Time													tREH	15	10	-	-	ns
	RE
	Output Hi-Z to														Low	tIR	0	0	-	-	ns
													RE
			High to											Low		tWHR	60	60	-	-	ns
	WE										RE
	Device Resetting Time (Read/Program/Erase)															tRST	-	-	5/10/500*1	5/10/500*1	µs

NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.

2. For cache program operation, the whole AC Charcateristics must be same as that of K9K2G08R0A.

12

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A

NAND Flash Technical Notes

Initial Invalid Block(s)

Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase cycles.

Identifying Initial Invalid Block(s)

All device locations are erased except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 2048. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.

Start

Set Block Address = 0

Increment Block Address

*

Check "FFh" at the column address

No

2048 of the 1st and 2nd page in the block

Create (or update)

Check "FFh ?

Initial Invalid Block(s) Table

Yes

No

Last Block ?

Yes

End

Figure 3. Flow chart to create initial invalid block table.

13

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A

NAND Flash Technical Notes (Continued)

Error in write or read operation

Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read failure due to single bit error should be reclaimed by ECC without any block replacement. The block failure rate in the qualification report does not include those reclaimed blocks.

		Failure Mode	Detection and Countermeasure sequence
	Write	Erase Failure	Status Read after Erase --> Block Replacement
		Program Failure	Status Read after Program --> Block Replacement
	Read	Single Bit Failure	Verify ECC -> ECC Correction
	ECC	: Error Correcting Code --> Hamming Code etc.
		Example) 1bit correction & 2bit detection

Program Flow Chart

		Start
		Write 80h
		Write Address
		Write Data
		Write 10h
		Read Status Register
										No
		I/O 6 = 1 ?
					= 1 ?
		or R/B
*						Yes
	No
Program Error		I/O 0 = 0 ?

Yes

Program Completed

* : If program operation results in an error, map out the block including the page in error and copy the

target data to another block.

14

K9K2G08U0A

FLASH MEMORY

K9K2G08R0A

NAND Flash Technical Notes (Continued)

Erase Flow Chart

Read Flow Chart

Start

Start

Write 60h

Write 00h

Write Block Address

Write Address

Write D0h

Write 30h

Read Status Register

Read Data

I/O 6 = 1 ?

No

ECC Generation

= 1 ?

or R/B

*

No

Yes

Reclaim the Error

No

Verify ECC

Yes

Erase Error

I/O 0 = 0 ?

Yes

Page Read Completed

Erase Completed

*

: If erase operation results in an error, map out

the failing block and replace it with another block.

Block Replacement

{

Block A

1st

(n-1)th

1

nth

an error occurs.

(page)

Buffer memory of the controller.

1st

{

Block B

2

(n-1)th

nth

(page)

* Step1

When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2

Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’) * Step3

Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’. * Step4

Do not erase or program to Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme.

15

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A

NAND Flash Technical Notes (Continued)

Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) pages of the block. Random page address programming is prohibited.

Page 63

(64)

Page 63

(64)

:

:

Page 31

(32)

Page 31

(1)

:

:

Page 2

Page 2

(3)

(3)

Page 1

(2)

Page 1

(32)

Page 0

(1)

Page 0

(2)

Data register

Data register

From the LSB page to MSB page

Ex.) Random page program (Prohibition)

DATA IN: Data (1)

Data (64)

DATA IN: Data (1)

Data (64)

16

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A

System Interface Using CE don’t-care.

For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption.

Figure 4. Program Operation with CE don’t-care.

CLE

CE don’t-care

CE

≈

≈

WE

ALE

I/Ox

80h

Address(5Cycles)

Data Input

Data Input

10h

tCS	tCH	CE	tCEA
CE
			tREA
WE	tWP	RE
		I/O0~7	out

Figure 5. Read Operation with CE don’t-care.

CLE

CE don’t-care

CE

RE

ALE

R/B

≈

tR

WE

I/Ox	00h	Address(5Cycle)	30h	Data Output(serial access)

17

K9K2G08U0A

FLASH MEMORY

K9K2G08R0A

NOTE

Device

I/O

DATA

ADDRESS

I/Ox

Data In/Out

Col. Add1

Col. Add2

Row Add1

Row Add2

Row Add3

K9K2G08X0A

I/O 0 ~ I/O 7

~2112byte

A0~A7

A8~A11

A12~A19

A20~A27

A28

Command Latch Cycle

CLE

tCLS

tCLH

tCS

tCH

CE

tWP

WE

tALStALH

ALE

tDStDH

I/Ox				Command

Address Latch Cycle

CLE

tCLS

tCS

CE

t

WC

tWC

tWC

tWP

tWP

tWP

tWP

WE

tWH

tWH

tWH

tALH	tALS	tALH	tALS	tALH	tALS	tALH
tALS

ALE

tDH

tDH

tDH

tDH

tDS

tDS

tDS

I/Ox

tDS

Col. Add2

Col. Add1

Row Add1

Row Add2

18

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A
Input Data Latch Cycle

CLE						tCLH
				≈
CE						tCH
				≈
ALE	tALS
	tWC			≈
	tWP		tWP	≈	tWP
WE		tWH
				tDH
	tDS	tDH	DS		tDS	tDH
			t
I/Ox				≈	DIN final*
	DIN 0		DIN 1
				≈
		NOTES : DIN final means 2112

Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)

CE	tCEA
				≈
						tCHZ*
	tREA		tREH
			tREA	≈	tREA	tOH
RE
				tRHZ*		tRHZ*
						tOH
I/Ox		Dout	Dout	≈		Dout
	tRR	tRC
				≈

R/B

NOTES : Transition is measured ±200mV from steady state voltage with load.

This parameter is sampled and not 100% tested.

19

K9K2G08U0A				FLASH MEMORY
K9K2G08R0A
Status Read Cycle
			tCLR
CLE	tCLS
		tCLH
	tCS
CE
	tWP	tCH
WE
			tCEA
				tCHZ*
			tWHR
				tOH
RE
	tDS	tDH	tREA	tRHZ*
			tIR*	tOH
I/Ox	70h			Status Output
			20

K9K2G08U0A

FLASH MEMORY

K9K2G08R0A

Read Operation

tCLR

CLE

CE

tWC

WE

tWB

tAR

ALE

tRHZ

tR

tRC

RE

≈

I/Ox

tRR

≈

00h Col. Add1 Col. Add2

Row

Add1 Row Add2 Row Add3

30h

Dout N Dout N+1

Dout M

Column Address

Row Address

≈

Busy

R/B

Read Operation(Intercepted by CE)

CLE

CE
WE						tWB
									tCHZ
							tAR
									tOH
ALE
						tR		tRC
RE
						tRR
I/Ox	00h	Col. Add1	Col. Add2	Row Add1 Row Add2	Row Add3	30h	Dout N	Dout N+1	Dout N+2
		Column Address		Row Address
R/B						Busy
					21

Random Data Output In a Page

K9K2G08R0A

K9K2G08U0A

CLE

tCLR

CE

WE

tWB

tWHR

tAR

ALE

tR

tRC

tREA

22

RE

tRR

I/Ox

00h

Col. Add1 Col. Add2

Row Add1 Row Add2 Row Add3

30h

Dout N

Dout N+1

05h

Col Add1 Col Add2

E0h

Dout M

Dout M+1

Column Address

Row Address

Column Address

R/B

Busy

MEMORY FLASH

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A

Page Program Operation

CLE

CE

tWC

tWC

≈

tWC

WE

ALE

tADL

RE

I/Ox

80h

Co.l Add1 Col. Add2

Row Add1 Row Add2 Row

Add3

Din

≈

Din

N

≈

M

SerialData

Column Address

Row Address

1 up to m Byte

Input Command

Serial Input

R/B

m = 2112byte

tWB tPROG

10h

Program Command

≈

70h I/O0

Read Status

Command

I/O0=0 Successful Program

I/O0=1 Error in Program

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

23

24

Page Program Operation with Random Data Input						K9K2G08U0A K9K2G08R0A
CLE

CE

tWC

tWC

tWC

WE

≈

≈

tADL

tADL

tWB

tPROG

ALE

RE

I/Ox

80h

Col. Add1

Col. Add2

Row Add1

Row Add2

Row Add3

Din

≈

Din

85h

Col. Add1

Col. Add2

Din

≈

Din

10h

70h

I/O0

N

≈

M

J

≈

K

Serial Data

Random Data

Program

Read Status

Column Address

Row Address

Serial Input

Column Address

Serial Input

Input Command

Input Command

Command

Command

R/B

≈

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

MEMORY FLASH

Copy-Back Program Operation With Random Data Input

CLE

CE

tWC

WE

tWB

tPROG

ALE

tWB

tR

RE

tADL

I/Ox

00h

Col Add1 Col Add2

Row Add1 Row Add2 Row Add3

35h

85h

Col Add1

Col Add2

Row Add1

Row Add2

Row Add3

Data 1

≈

Data N

10h

70h

I/O0

≈

25

Column Address

Row Address

Column Address

Row Address

Read Status

Command

R/B

≈

≈

Busy

Busy

Copy-Back Data

I/O0=0 Successful Program

I/O0=1 Error in Program

Input Command

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

K9K2G08U0A K9K2G08R0A

MEMORY FLASH

26

Cache Program Operation(available only within a block)

CLE
CE
tWC
≈	≈
WE		tCPROG
tCBSY	tWB
tWB

ALE

RE

tADL

Din

≈

tADL

≈

I/Ox

80h

Col Add1 Col Add2

Row Add1 Row Add2 Row Add3

Din

15h

80h

Col Add1 Col Add2 Row Add1 Row Add2 Row Add3

Din

Din

10h

70h

I/O

N

≈

M

N

≈

M

Program

Program Confirm

Serial Data

Column Address

Row Address

Serial Input

Command

Command

Input Command

(Dummy)

(True)

R/B

Max. 63 times repeatable

≈

Last Page Input & Program

≈

tCBSY : max. 700us

NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.

Ex.) Cache Program

tCBSY

tCBSY

tCBSY

tPROG

R/B

Address &

Address &

Address &

Address &

I/Ox

80h

10h

70h

80h

15h

80h

15h

80h

15h

Data Input

Data Input

Data Input

Data Input

Col Add1,2 & Row Add1,2

Data

K9K2G08U0A K9K2G08R0A

MEMORY FLASH

K9K2G08U0A						FLASH MEMORY
K9K2G08R0A
Block Erase Operation
CLE
CE
	tWC
WE
					tWB	tBERS
ALE
RE
I/Ox	60h	Row Add1	Row Add2	Row Add3	D0h	70h	I/O 0
		Row Address
R/B						Busy
	Auto Block Erase			Erase Command		≈	I/O0=0 Successful Erase
	Setup Command					Read Status	I/O0=1 Error in Erase
						Command
						27

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A
Read ID Operation

CLE

CE

WE

ALE

tAR

RE

tREA

I/Ox

Device

4th cyc.*

90h

00h

ECh

XXh

Code*

Read ID Command

Address. 1cycle

Maker Code Device Code

Device

Device Code*(2nd Cycle)

4th Cycle*

K9K2G08R0A

AAh

15h

K9K2G08U0A

DAh

15h

ID Defintition Table

90 ID : Access command = 90H

	Description
1st Byte	Maker Code
2nd Byte	Device Code
3rd Byte	Don’t care
4th Byte	Page Size, Block Size, Spare Size, Organization

28

K9K2G08U0A						FLASH MEMORY
K9K2G08R0A
4th ID Data
	Description	I/O7	I/O6	I/O5	I/O4	I/O3	I/O2	I/O1	I/O0
	1KB							0	0
Page Size	2KB							0	1
(w/o redundant area )	Reserved							1	0
	Reserved							1	1
	64KB			0	0
Blcok Size	128KB			0	1
(w/o redundant area )	256KB			1	0
	Reserved			1	1
Redundant Area Size	8						0
( byte/512byte)	16						1
Organization	x8		0
	x16		1
	50ns	0				0
Serial AccessMinimum	Reserved	1				0
	Reserved	0				1
	Reserved	1				1

29

K9K2G08U0A	FLASH MEMORY
K9K2G08R0A

Device Operation

PAGE READ

Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 25µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 50ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address.

The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.

Figure 6. Read Operation

CLE

CE

WE

ALE
R/B	tR

RE

I/Ox

00h

Address(5Cycle)

30h

Data Output(Serial Access)

Col Add1,2 & Row Add1,2,3

					Data Field
						Spare Field

30