ARM, ARM7, embedded, 32-bit, microcontroller, USB 2.0, USB device
AbstractAn initial LPC214x User Manual revision
Philips Semiconductors
Volume 1LPC2141/2/4/6/8 UM
Revision history
RevDateDescription
0120050815Initial version
UM10139
Contact information
For additional information, please visit: http://www.semiconductors.philips.com
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The LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI-S CPU with
real-time emulation and embedded trace support, that combines the microcontroller with
embedded high speed flash memory ranging from 32
memory interface and a unique accelerator architecture enable 32-bit code execution at
the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb
mode reduces code by more than 30
Due to their tiny size and low power consumption, LPC2141/2/4/6/8 are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. A blend of serial communications interfaces ranging from a USB 2.0 Full
Speed device, multiple UARTS, SPI, SSP to I
make these de vices very well suited f or comm unication gate wa ys and protocol conv erters,
soft modems, voice recognition and low end imaging, providing both large buffer size and
high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC,
PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external
interrupt pins make these microcontrollers particularly suitable for industrial control and
medical systems.
% with minimal performance penalty.
2
Cs and on-chip SRAM of 8 kB up to 40 kB,
kB to 512 kB. A 128-bit wide
1.2 Features
• 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
• 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory.
128 bit wide interface/accelerator enables high speed 60 MHz operation.
• In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.
Single flash sector or full chip erase in 4 00 ms and pr og ra mming o f 256
• EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software and high speed tracing of instruction execution.
• USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.
In addition, the LPC2146/8 provide 8 kB of on-chip RAM accessible to USB by DMA.
• One or two (LPC2141/2 vs. LPC2144/ 6/8) 10-bit A/D con verters provide a total of 6/ 14
analog inputs, with conversion times as low as 2.44
µs per channel.
• Single 10-bit D/A converter provides variable analog output.
• Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog.
• Low power real-time clock with independent power and dedicated 32 kHz clock input.
• Multiple serial interfaces including two UARTs (16C550), two Fast I
(400
kbit/s), SPI and SSP with buffering and variable data length capabilities.
• Vectored interrupt controller with configurable priorities and vector addresses.
• Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
• Up to nine edge or level sensitive external interrupt pins available.
• 60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100
• On-chip integrated oscillator operates with an external crystal in range from 1 MHz to
30
• Power saving modes include Idle and Power-down.
• Individual enable/disab le of peripheral functions as w ell as peripheral cloc k scaling for
additional power optimization.
• Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out
Detect (BOD) or Real-Time Clock (RTC).
• Single power supply chip with Power-On Reset (POR) and BOD circuits:
– CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O
1.3 Applications
• Industrial control
• Medical systems
• Access control
• Point-of-sale
• Communication gateway
• Embedded soft modem
• General purpose applications
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µs.
MHz and with an external oscillator up to 50 MHz.
pads.
1.4 Device information
Table 1:LPC2141/2/4/6/8 device information
DeviceNumber
of pins
LPC2141648 kB2 kB32 kB6-LPC21426416 kB2 kB64 kB61LPC21446416 kB2 kB128 kB141UAR T1 with f ull modem
LPC21466432 kB + 8 kB
LPC21486432 kB + 8 kB
On-chip
SRAM
[1] While the USB DMA is the primary user of the additional 8 kB RAM, this RAM is also accessible at any time
by the CPU as a general purpose RAM for data and code storage.
Endpoint
USB RAM
[1]
2 kB256 kB141UAR T1 with f ull modem
[1]
2 kB512 kB141UAR T1 with f ull modem
On-chip
FLASH
Number of
10-bit ADC
channels
Number of
10-bit DAC
channels
Note
interface
interface
interface
1.5 Architectural overview
The LPC2141/2/4/6/8 consists of an ARM7TDMI-S CPU with emulation support, the
ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced
High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI
Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus)
for connection to on-chip peripheral functions. The LPC2141/24/6/8 configures the
ARM7TDMI-S processor in little-endian byte order.
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the
4
gigabyte ARM memory space. Each AHB peripheral is a llocated a 16 kB address space
within the AHB address space. LPC2141/2/4/6/8 peripheral functions (other than the
interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the
VPB bus to the AHB bus. VPB peripherals are also allocated a 2
addresses, beginning at the 3.5
a 16
kB address space within the VPB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connect Block
(see chapter "Pin Connect Block" on
specific application requirements for the use of peripheral functions and pins.
1.6 ARM7TDMI-S processor
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architectu re is base d on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers. This simplicity results in a high instruction throughput and
impressive real-time interrupt response from a small and cost-effective processor core.
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megabyte range of
gigabyte address point. Each VPB peripheral is allocated
page 75). This must be configured by software to fit
Pipeline techniques are employ ed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
THUMB, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
• The standard 32-bit ARM instruction set.
• A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because THUMB code
operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the
performance of an equivalent ARM processor connecte d to a 16 -b it me m ory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that
can be found on official ARM website.
The LPC2141/2/4/6/8 incorporate a 32 kB, 64 kB, 128 kB, 256 kB, and 512 kB Flash
memory system respectively. This memory may be used for both code and data storage.
Programming of the Flash memory may be accomplished in several ways: over the serial
built-in JTAG interface, using In System Progr amming (ISP) and UA RT0, or b y means of In
Application Programming (IAP) capabilities. The application program, using the IAP
functions, may also erase and/or program the Flash while the application is running,
allowing a great degree of flexibility for data storage field firmware upgrades, etc. When
the LPC2141/2/4/6/8 on-chip bo o tlo ad er is used , 32
500
kB of Flash memor y is available for user code.
The LPC2141/2/4/6/8 Flash memory provides minim um of 100,000 erase/write cycles and
20 years of data-retention.
1.8 On-chip Static RAM (SRAM)
On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip
SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2141/2/4/6/8 provide
8/16/32 kB of static RAM respectively.
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kB, 64 kB, 128 kB, 256 kB, and
The LPC2141/2/4/6/8 SRAM is designed to be accessed as a byte-addressed memory.
Word and halfword accesses to the memory ignore the alignment of the address and
access the naturally-aligned value that is addressed (so a memory access ignores
address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses).
Therefore valid reads and writes require data accessed as halfwords to originate from
addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in
hexadecimal notation) and data accessed as words to originate from addresses with
address lines 0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal
notation). This rule applies to both off and on-chip memory usage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during
back-to-bac k writes. The write-back buffer always holds the last data sent by software to
the SRAM. This data is only written to the SRAM when another write is requested by
software (the data is only written to the SRAM when sof tware does anot her write). If a chip
reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after
a "warm" chip reset, the SRAM does not reflect the last write oper ation). An y softwar e that
checks SRAM contents after reset must take this into account. Two identical writes to a
location guarantee that the data will be present after a Reset. Alternatively, a dummy write
operation before entering idle or power-down mode will similarly guarantee that the last
data written will be present in SRAM after a subsequent Reset.
(1) Pins shared with GPIO.
(2) LPCC2144/6/8 only.
(3) USB DMA controller with 8 kB of RAM accessible as general purpose RAM and/or DMA is available in LPC2146/8 only.
(4) LPC2142/4/6/8 only.
The LPC2141/2/4/6/8 incorporates several distinct memory regions, shown in the
following figures.
user program viewpoint following reset. The interrupt vector area supports address
remapping, which is described later in this section.
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Chapter 2: LPC2141/2/4/6/8 Memory Addressing
Rev. 01 — 15 August 2005User manual
Figure 2 shows the overall map of the entire address space from the
- AHB section is
128 x 16 kB blocks
(totaling 2 MB).
- VPB section is
128 x 16 kB blocks
(totaling 2 MB).
3.75 GB
0xFFFF FFFF
AHB PERIPHERALS
0xFFE0 0000
0xFFDF FFFF
RESERVED
0xF000 0000
0xEFFF FFFF
RESERVED
3.5 GB + 2 MB
VPB PERIPHERALS
3.5 GB
Fig 3. Peripheral memory map
Figures 3 through 4 and Table 2 show different views of the peripheral address space.
Both the AHB and VPB peripheral areas are 2 megabyte spaces which are divided up into
128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying the
address decoding for each peripheral. All peripheral register addresses are word aligned
(to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane
mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit)
accesses to occur at smaller boundaries. An implication of this is that word and half-word
registers must be accessed all at once. For example, it is not possible to read or write the
upper byte of a word r egister separately.
2.2 LPC2141/2142/2144/2146/2148 memory re-mapping and boot block
2.2.1 Memory map concepts and operating modes
The basic concept on the LPC2141/2/4/6/8 is that each memory area has a "natural"
location in the memory map. This is the address ran ge f or which code re siding in that area
is written. The bulk of each memory space remains permanently fixed in the same
location, eliminating the need to have portions of the code designed to run in different
address ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses
0x0000
Boot Block and SRAM spaces need to be re-mapped in order to allow alternative uses of
interrupts in the different operating modes described in
interrupts is accomplished via the Memory Mapping Control feature ( Section 3. 7 “Memory
Note: Identified as reserved in ARM documentation, this location is used
by the Boot Loader as the Valid User Program key. This is described in
detail in "Flash Memory System and Programming" chapter on
The Boot Loader always executes after any reset. The Boot Block
interrupt vectors are mapped to the bottom of memory to allow
handling exceptions and using interrupts during the Boot Loading
process.
Activated by Boot Loader when a valid User Program Signature is
recognized in memory and Boot Loader operation is not forced.
Interrupt vectors are not re-mapped and are found in the bottom of the
Flash memory.
Activated by a User Program as desired. Interrupt vectors are
re-mapped to the bottom of the Static RAM.
page 291.
2.2.2 Memory re-mapping
In order to allow for compatibility with future derivatives, the entire Boot Block is mapped
to the top of the on-chip memory space. In this manner, the use of larger or smaller flash
modules will not require changing the location of the Boot Block (which would require
changing the Boot Loader code itself) or changin g the mapping of t he Boot Bloc k interrupt
vectors. Memory spaces other than the interrupt vectors remain in fixed locations.
Figure 5 shows the on-chip memory mapping in the modes defined above.
The portion of memory that is re-mapped to allow interrupt processing in different modes
includes the interrupt vector area (32
64
bytes. The re-mapped code locations overlay addresses 0x0000 0000 through
0x0000
handler at address 0x0000
vector contained in the SRAM, e xternal memory, and Boot Block must contain br anches to
the actual interrupt handlers, or to other instructions that accomplish the branch to the
interrupt handlers.
There are three reasons this configuration was chosen:
003F. A typical user program in the Flash memory can place the entire FIQ
001C without any need to consider memory boundaries. The
1. To give the FIQ handler in the Flash memory the advantage of not ha ving to take a
memory boundary caused by the remapping into account.
bytes) and an additional 32 bytes, for a total of
Philips Semiconductors
Volume 1Chapter 2: Memory map
2. Minimize the need to for the SRAM and Boot Block vectors to deal with arbitrary
boundaries in the middle of code space.
3. To provide space to store constants for jumping beyond the range of single word
branch instructions.
Re-mapped memory areas, including the Boot Block and interrupt vectors, continue to
appear in their original location in addition to the re-mapped address.
Details on re-mapping and examples can be found in Section 3.7 “ Memory mapping
ACTIVE INTERRUPT VECTORS (FROM FLASH, SRAM, OR BOOT BLOCK)
0x0000 0000
Philips Semiconductors
Volume 1Chapter 2: Memory map
2.3 Prefetch abort and data abort exceptions
The LPC2141/2/4/6/8 generates the appropriate bus cycle abort exception if an access is
attempted for an a ddress t hat is in a re serve d or u nassign ed addre ss r eg ion. T he regi ons
are:
• Areas of the memory map that are not implemented for a specific ARM derivative. F or
the LPC2141/2/4/6/8, this is:
– Address space between On-Chip Non-Volatile Memory and On-Chip SRAM,
labelled "Reserved Address Space" in
memory address range from 0x0000 8000 to 0x3FFF FFFF, for 64 kB Flash de vice
this is memory address range from 0x0001
device this is memory address range from 0x0002
256
kB Flash device this is memory address range from 0x0004 0000 to
0x3FFF
0x3FFF
– Address space between On-Chip Static RAM and the Boot Block. Labelled
"Reserved Address Space" in
address range from 0x4000 2000 to 0x7FFF CFFF, for 16 kB SRAM device this is
memory address range from 0x4000
device this range is from 0x4000
RAM starts, and from 0x7FD0
– Address space between 0x8000 0000 and 0xDFFF FFFF, labelled "Reserved
Adress Space".
– Reserved regions of the AHB and VPB spaces. See Figure 3.
• Unassigned AHB peripheral spaces. See Figure 4.
• Unassigned VPB peripheral spaces. See Table 2.
FFFF while for 512 kB Flash device this range is from 0x0008 0000 to
FFFF.
Figure 2. For 8 kB SRAM device this is memory
8000 to 0x7FCF FFFF where the 8 kB USB DMA
2000 to 0x7FFF CFFF.
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Figure 2. For 32 kB Flash device this is
0000 to 0x3FFF FFFF, for 128 kB Flash
0000 to 0x3FFF FFFF, for
4000 to 0x7FFF CFFF. For 32 kB SRAM
For these areas , both at tempt ed data access and inst ruction fetch generate an exception.
In addition, a Prefetch Abort exception is generated for any instruction fetch that maps to
an AHB or VPB peripheral address.
Within the address space of an existing VPB peripheral , a data abort exception is not
generated in response to an access to an undefined address. Address decoding within
each peripheral is limited to that needed to distinguish defined registers within the
peripheral itself. For example, an access to address 0 xE000
within the UART0 space) may result in an access to the register defined at address
0xE000
in the LPC2141/2/4/6/8 documentation and are not a supported feature.
Note that the ARM core stores the Prefetch Abort flag along with the associated
instruction (which will be meaningless) in the pipeline and processes the abort only if an
attempt is made to execute the instruction fetched from the illegal address. This prevents
accidental aborts that could be caused by prefetches that occur when code is executed
very near a memory boundary.
C000. Details of such address aliasing within a peripheral space are not defined
D000 (an undefined address
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Chapter 3: System Control Block
Rev. 01 — 15 August 2005User manual
3.1 Summary of system control block functions
The System Control Block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
• Crystal Oscillator
• External Interrupt Inputs
• Miscellaneous System Controls and Status
• Memory Mapping Control
• PLL
• Power Contro l
• Reset
• VPB Divider
• Wakeup Timer
Each type of function has its own register(s) if any are required and unneeded bits are
defined as reserved in order to allow future expansion. Unrelated functions never share
the same register addresses
3.2 Pin description
Table 5 shows pins that are associated with System Control block functions.
Table 5:Pin summary
Pin namePin
X1InputCrystal Oscillator Input - Input to the oscillator and internal clock
X2OutputCrystal Oscillator Output - Output from the oscillator amplifier
EINT0InputExternal Interrupt Input 0 - An active low/high level or
EINT1InputExternal Interrupt Input 1 - See the EINT0 description above.
Pin description
direction
generator circuits
falling/rising edge general purpose interrupt input. This pin may be
used to wake up the processor from Idle or Power-down modes.
Pins P0.1 and P0.16 can be selected to perform EINT0 function.
Pins P0.3 and P0.14 can be selected to perform EINT1 function.
Important: LOW level on pin P0.14 immediately after reset is
considered as an external hardware request to start the ISP
command handler. More details on ISP and Serial Boot Loader can
be found in "Flash Memory System and Programming" chapter on
page 291.
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
3.4 Crystal oscillator
While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz
can be used by the LPC2141/2/4/6/8 if supplied to its input XT AL1 pin, this
microcontroller’s onboard oscillator circuit supports external crystals in the range of 1
to 30
MHz only. If the on-chip PLL system or the boot-loader is used, the inp ut clock
frequency is limited to an exclusive range of 10
MHz to 25 MHz.
value
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Address
[1]
MHz
The oscillator output frequency is called F
referred to as CCLK f or purposes of rate equations , etc. else where in this d ocument. F
and CCLK are the same value unless the PLL is running and connected. Refer to the
Section 3.8 “Phase Locked Loop (PLL)” on page 27 for details and frequency limitations.
The onboard oscillator in the LPC2141/2/4/6/8 can operate in one of two modes: slave
mode and oscillation mode.
In slave mode th e input clock signal should be coupled by means of a capacitor of 100 pF
(C
in Figure 6, drawing a), with an amplitude of at least 200 mVrms. The X2 pin in this
C
configuration can be left not connected. If sla ve mode is se lected, the F
duty cycle can range from 1
External components and models used in oscillation mode are shown in Figure 6,
drawings b and c, and in Table 7. Since the feedbac k resistance is int egr ated on chip, only
a crystal and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (the fundamental frequency is represented by L, C
R
). Capacitance CP in Figure 6, drawing c, represents the parallel package capacitance
S
and should not be larger than 7 pF. Par ameters FC, CL, RS and CP are supplied by the
crystal manufacturer.
Choosing an oscillation mode as an on-board oscillator mode of operation limits F
clock selection to 1
(Figure 7, mode a and/or b)(Figure 7, mode a)(Figure 7, mode b)
Fig 7. F
OSC
= 25 MHz
OSC
selection algorithm
3.5 External interrupt inputs
The LPC2141/2/4/6/8 includes four External Interrupt Inputs as selectable pin functions.
The External Interrupt Inputs can optionally be used to wake up the processor from
Power-down mode.
True
True
On-chip PLL used
in application?
False
ISP used for initial
code download?
False
External crystal
oscillator used?
False
MIN f
= 1 MHz
OSC
MAX f
= 50 MHz
OSC
True
MIN f
MAX f
= 1 MHz
OSC
= 30 MHz
OSC
3.5.1 Register description
The external interrupt function has four registers associated with it. The EXTINT register
contains the interrupt flags, and the EXTWAKEUP register contains bits that enable
individual external interrupts to wake up the microcontroller from Power-down mode. The
EXTMODE and EXTPOLAR registers specify the level and edge sensitivity parameters.
Table 8:External interrupt registers
NameDescriptionAccess Reset
value
EXTINTThe External Interrupt Fla g Register contains
interrupt flags for EINT0, EINT1, EINT2 and
EINT3. See
EXTPOLAR The External Interrupt Polarity Register controls
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
3.5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)
When a pin is selected for its external interrupt function, the level or edge on that pin
(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in
this register. This asserts the corresponding interrupt request to the VIC, which will cause
an interrupt if interrupts from the pin are enabled.
enable bits that control whether each external
interrupt will cause the processor to wake up
from Power-down mode. See
whether each pin is edge- or level sensitive.
which level or edge on each pin will cause an
interrupt.
Table 10.
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Address
[1]
value
R/W00xE01F C144
R/W00xE01F C148
R/W00xE01F C14C
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding
bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to e xecut e (handling
wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
the event that was just triggered by activity on the EINT pin will not be recognized in the
future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt), the
corresponding bit in the EXTINT register must be cleared! For details see
For example, if a system wakes up from power-down using a low level on external
interrupt 0 pin, its post-wakeup code m ust reset the EINT0 bit in order to allow futur e entry
into the power-down mode. If the EINT0 bit is left set to 1, subsequent attempt(s) to invoke
power-down mode will fail. The same goes for external interrupt handling.
More details on power-down mode will be discussed in the following chapters.
Table 9:External Interrupt Flag register (EXTINT - address 0xE01F C140) bit description
BitSymbolDescriptionReset
0EINT0In level-sensitiv e mode , this bit is set if the EINT0 function is selected for its pin, and the pin is in
its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin,
and the selected edge occurs on the pin.
Up to two pins can be selected to perform the EINT0 function (see P0.1 and P0.16 description in
"Pin Configuration" chapter page 66.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active
state (e.g. if EINT0 is selected to be low level sensitive and a low level is present on the
corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the
pin becomes high).
1EINT1In level-sensitiv e mode , this bit is set if the EINT1 function is selected for its pin, and the pin is in
its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin,
and the selected edge occurs on the pin.
Up to two pins can be selected to perform the EINT1 function (see P0.3 and P0.14 description in
"Pin Configuration" chapter on page 66.)
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active
state (e.g. if EINT1 is selected to be low level sensitive and a low level is present on the
corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the
pin becomes high).
2EINT2In level-sensitiv e mode , this bit is set if the EINT2 function is selected for its pin, and the pin is in
its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin,
and the selected edge occurs on the pin.
Up to two pins can be selected to perform the EINT2 function (see P0.7 and P0.15 description in
"Pin Configuration" chapter on
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active
state (e.g. if EINT2 is selected to be low level sensitive and a low level is present on the
corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the
pin becomes high).
3EINT3In level-sensitiv e mode , this bit is set if the EINT3 function is selected for its pin, and the pin is in
its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin,
and the selected edge occurs on the pin.
Up to three pins can be selected to perform the EINT3 function (see P0.9, P0.20 and P0.30
description in "Pin Configuration" chapter on
This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active
state (e.g. if EINT3 is selected to be low level sensitive and a low level is present on the
corresponding pin, this bit can not be cleared; this bit can be cleared only when the signal on the
pin becomes high).
7:4-Reserved, user software should not write ones to reserved bits. The value read from a reserved
Enable bits in the INTWAKE register allow the external interrupts and other sources to
wake up the processor if it is in Power-down mode. The related EINTn function must be
mapped to the pin in order f or the w ak eup process to tak e plac e. It is not necessary for the
interrupt to be enabled in the Vectored Interrupt Controller for a wak eup to tak e place . This
arrangement allows additional capabilities, such as having an external interrupt input
wake up the processor from Power-down mode without causing an interrupt (simply
resuming operation), or allowing an interrupt to be enabled during Power-down without
waking the processor up if it is asserted (eliminating the need to disab le th e interrupt if the
wakeup feature is not desirable in the application).
For an external interrupt pin to be a source that would wake up the microcontroller from
Po wer-down mode, it is also necessary to clear the corresponding bit in the External
Interrupt Flag register (
0EXTWAKE0 When one, assertion of EINT0 will wake up the processor from
1EXTWAKE1 When one, assertion of EINT1 will wake up the processor from
2EXTWAKE2 When one, assertion of EINT2 will wake up the processor from
3EXTWAKE3 When one, assertion of EINT3 will wake up the processor from
4-Reserved, user software should not write ones to reserved bits.
5USBW AKEWhen one, activity of the USB bus (USB_need_clock = 1) will
13:4-Reserved, user software should not write ones to reserved bits.
14BODWAKEWhen one, a BOD interrupt will wake up the processor from
15RTCWAKEWhen one, assertion of an RTC interrupt will wake up the
UM10139
Section 3.5.2 on page 21).
Power-down mode.
Power-down mode.
Power-down mode.
Power-down mode.
The value read from a reserved bit is not defined.
wake up the processor from Po w er-do wn mode. An y change of
state on the USB data pins will cause a wakeup when this bit is
set. For details on the relationship of USB to Power-do wn mode
and wakeup, see
(USBIntSt - 0xE01F C1C0)” on page 200 and Section 3.8.8
“PLL and Power-down mode” on page 32.
The value read from a reserved bit is not defined.
The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins
that are selected for the EINT function (see chapter Pin Connect Block on
enabled via the VICIntEnable register (Section 5.4.4 “Interrupt Enable register
(VICIntEnable - 0xFFFF F010)” on page 54) can cause interrupts from the External
Interrupt function (though of course pins selected for other functions may cause interrupts
from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the VICIntEnable register, and should write the corresponding 1 to the
EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear
the EXTINT bit that could be set by changing the mode.
In level-sensitive mode, the bits in this register select whether the corresponding pin is
high- or low-active. In edge-sensitive mode, they select whether the pin is rising- or
falling-edge sensitive . Only pins that are selected for the EINT function (see "Pin Connect
Block" chapter on
“Interrupt Enable register (VICIntEnable - 0xFFFF F010)” on page 54) can cause
interrupts from the External Interrupt function (though of course pins selected for other
functions may cause interrupts from those functio ns ).
UM10139
description
value
1EINT1 is edge sensitive.
1EINT2 is edge sensitive.
1EINT3 is edge sensitive.
NA
bits. The value read from a reserved bit is not defined.
page 75) and enabled in the VICIntEnable register (Section 5.4.4
Note: Software should only change a bit in this register when its interrupt is
disabled in the VICIntEnable register, and should write the corresponding 1 to the
EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear
the EXTINT bit that could be set by changing the polarity.
Software can select multiple pins f or each of EINT3:0 in t he Pin Select registers , which are
described in chapter Pin Connect Block on
of EINT3:0 receives the state of all of its associated pins from the pins’ receivers, along
with signals that indicate whether each pin is selected for the EINT function. The external
interrupt logic handles the case when more than one pin is so selected, diff erently
according to the state of its Mode and Polarity bits:
• In Low-Active Le v el Sensitiv e mode , the states o f all pins selected f or the same EINTx
functionality are digitally combined using a positive logic AND gate.
• In High-Active Level Sensitive mode, the states of all pins selected for the same
EINTx functionality are digitally combined using a positive logic OR gate.
• In Edge Sensitive mode, regardless of polarity, the pin with the lowest GPIO port
number is used. (Selecting multiple pins for an EINTx in edge-sensitive mode could
be considered a programming error.)
The signal derived by this logic processing multiple external interrupt pins is the EINTi
signal in the following logic schematic
UM10139
page 75. The external interrupt logic for each
Figure 8.
EINTi
EXTPOLARi
For ex ample, if the EINT3 function is selected in the PINSEL0 and PINSEL1 registers for
pins P0.9, P0.20 and P0.30, and EINT3 is configured to be low level sensitive, the inputs
from all three pins will be logically ANDed. When more than one EINT pin is logically
ORed, the interrupt service routine can read the states of the pins from the GPIO port
using the IO0PIN and IO1PIN registers, to determine which pin(s) caused the interrupt.
Some aspects of controlling LPC2141/2/4/6/8 operation that do not fit into peripheral or
other registers are grouped here.
3.6.1 System Control and Status flags register (SCS - 0xE01F C1A0)
Table 13:System Control and Status flags register (SCS - address 0xE01F C1A0) bit description
BitSymbolValueDescriptionReset
value
0GPIO0MGPIO port 0 mode selection.0
0GPIO port 0 is accessed via VPB addresses in a fashion compatible with previous
LCP2000 devices.
1High speed GPIO is enabled on GPIO port 0, accessed via addresses in the on-chip
memory range. This mode includes the port masking feature described in the GPIO
chapter on page
1GPIO1MGPIO port 1 mode selection.0
0GPIO port 1 is accessed via VPB addresses in a fashion compatible with previous
LCP2000 devices.
1High speed GPIO is enabled on GPIO port 1, accessed via addresses in the on-chip
memory range. This mode includes the port masking feature described in the GPIO
chapter on page
31:2-Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
page 81.
page 81.
NA
3.7 Memory mapping control
The Memory Mapping Control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000
to have control of the interrupts.
3.7.1 Memory Mapping control register (MEMMAP - 0xE01F C040)
Whenever an exception handling is necessary, the microcontroller will f etch an instruction
residing on the exception cor res ponding a ddress a s de scribed in
vector locations” on page 12. The MEMMAP register determines the source of data that
will fill this table.
0000. This allows code running in diffe rent memory spaces
Table 14:Memory Mapping control register (MEMMAP - address 0xE01F C040) bit
BitSymbol ValueDescriptionReset
1:0MAP00Boot Loader Mode. Interrupt vectors are re-mapped to Boot
7:2--Reserved, user software should not write ones to reserved
3.7.2 Memory mapping control usage notes
The Memory Mapping Control simply selects one out of three available sources of data
(sets of 64 bytes each) necessary for handling ARM exceptions (interrupts).
UM10139
description
value
00
Block.
01User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
10User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
11Reserved. Do not use this option.
Warning: Improper setting of this value may result in incorrect
operation of the device.
NA
bits. The value read from a reserved bit is not defined.
For example, whenever a Software Interrupt request is generated, the ARM core will
always fetch 32-bit data "residing" on 0x0000
locations” on page 12. This means that when MEMMAP[1:0]=10 (User RAM Mode), a
read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of
MEMMAP[1:0]=00 (Boot Loader Mode), a read/fetch from 0x0000
available also at 0x7FFF
3.8 Phase Locked Loop (PLL)
There are two PLL modules in the LPC2141/2/4/6/8 microcontroller. The PLL0 is used to
generate the CCLK clock (system clock) while the PLL1 has to supply the clock for the
USB at the fixed rate of 48
of the PLL interrupt capabilities reserved only for the PLL0.
The PLL0 and PLL1 accept an input clock frequency in the range of 10 MHz to 25 MHz
only. The input frequency is multiplied up the range of 10
and 48
multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be
higher than 6 on the LPC2141/2/4/6/8 due to the upper frequency limit of the CPU). The
CCO operates in the range of 156
loop to keep the CCO within its frequency range while the PLL is providing the desired
output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the
output clock. Since the minimum ou tput divider value is 2, it is insured that the PLL output
has a 50% duty cycle. A block diagram of the PLL is shown in
MHz for the USB clock using a Current Controlled Oscillators (CCO). The
0008 see Table 3 “ARM exception vector
0008 will provide data
E008 (Boot Block remapped from on-chip Bootloader).
MHz. Structurally these two PLLs are identical with exception
MHz to 60 MHz for the CCLK
MHz to 320 MHz, so there is an additional divider in the
Figure 9.
PLL activation is controlled via the PLLCON register . The PLL multiplier and divider values
are controlled by the PLLCFG register. These two registers are protected in order to
prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all chip
operations, including t he W atchdog Timer, are dependent on the PLL0 when it is pro viding
the chip clock, accidental changes to the PLL setup could re sult in une xpected beha vior of
the microcontroller. The same concern is present with the PLL1 and the USB. The
protection is accomplished by a feed sequence similar to that of the Watchdog Timer.
Details are provided in the description of the PLLFEED register.
Both PLLs are turned off and bypassed f ollowing a chip Reset and when by entering
Pow er-down mode. The PLL is en abled b y softw are only. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.
3.8.1 Register description
The PLL is controlled by the registers shown in Table 15. More detailed descriptions
follow.
Warning: Improper setting of the PLL0 and PLL1 values may result in incorrect
operation of the device and the USB module!
Table 15:PLL registers
Generic
name
PLLCONPLL Control Register. Holding register for
PLLCFGPLL Configuration Register. Holding register for
PLLSTATPLL Status Register. Read-back register for PLL
PLLFEEDPLL Feed Register. This register enables
DescriptionAccess Reset
updating PLL control bits. Values written to this
register do not take effect until a valid PLL feed
sequence has taken place.
updating PLL configuration values. Values
written to this register do not take effect until a
valid PLL feed sequence has taken place.
control and configuration information. If
PLLCON or PLLCFG have been written to, but a
PLL feed sequence has not yet occurred, they
will not reflect the current PLL state. Reading
this register provides the actual values
controlling the PLL, as well as the status of the
PLL.
loading of the PLL control and configuration
information from the PLLCON and PLLCFG
registers into the shadow registers that actually
affect PLL operation.
System clock
[1]
value
R/W00xE01F C080
R/W00xE01F C084
RO00xE01F C088
WONA0xE01F C08C
(PLL0)
Address & Name
PLL0CON
PLL0CFG
PLL0STAT
PLL0FEED
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USB 48 MHz
clock (PLL1)
Address & Name
0xE01F C0A0
PLL1CON
0xE01F C0A4
PLL1CFG
0xE01F C0A8
PLL1STAT
0xE01F C0AC
PLL1FEED
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
The PLLCON register contains the bits that enable and connect the PLL. Enabling the
PLL allows it to attempt to lock to the current settings of the multiplier and divider values.
Connecting the PLL causes the processor and all chip functions to run from the PLL
output clock. Changes to the PLLCON register do not take effect until a correct PLL feed
sequence has been given (see
0PLLEPLL Enable. When one, and after a valid PLL feed, this bit will
1PLLCPLL Connect. When PLLC and PLLE are both set to one, and after a
7:2-Reserved, user software should not write ones to reserved bits. The
The PLL must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that the PLL is loc ked before it is connected or automatically
disconnect the PLL if lock is lost during operation. In the event of loss of PLL lock, it is
likely that the oscillator clock has become unstable and disconnecting the PLL will not
remedy the situation.
0xE01F
C0A0) bit description
activate the PLL and allow it to lock to the requested frequency. See
PLLSTAT register,
valid PLL feed, connects the PLL as the clock source for the
microcontroller. Otherwise, the oscillator clock is used directly by the
microcontroller. See PLLSTAT register,
The PLLCFG register contains the PLL multiplier and divider values. Changes to the
PLLCFG register do not take effect until a correct PLL feed sequence has been given (see
Section 3.8.7 “PLL Feed register (PLL0FEED - 0xE01F C08C, PLL1FEED 0xE01F C0AC)” on page 32). Calculations for the PLL frequency, and multiplier and
divider values are found in the PLL Frequency Calculation section on page 33.
3.8.4 PLL Status register (PLL0STAT - 0xE01F C088, PLL1STAT 0xE01F
The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until a
proper PLL feed has occurred (see
4:0MSELRead-back for the PLL Multiplier value. This is the value currently
6:5PSELRead-back f or the PLL Divider value. This is the value currently
7-Reserved, user software should not write ones to reserved bits.
8PLLERead-back for the PLL Enable bit. When on e, the PLL is currently
9PLLCRead-back for the PLL Connect bit. When PLLC and PLLE are both
10PLOCKReflects the PLL Lock status. When zero, the PLL is not locked.
15:11-Reserved, user software should not write ones to reserved bits.
C0A8)
0xE01F C0A8) bit description
used by the PLL.
used by the PLL.
The value read from a reserved bit is not defined.
activated. When zero, the PLL is turned off. This bit is automatically
cleared when Power-down mode is activated.
one, the PLL is connected as the clock source for the
microcontroller. When either PLLC or PLLE is zero, the PLL is
bypassed and the oscillator clock is used directly by the
microcontroller. This bit is automatically cleared when Power-down
mode is activated.
When one, the PLL is locked onto the requested frequency.
The value read from a reserved bit is not defined.
UM10139
Section 3.8.7 “PLL Feed register (PLL0FEED -
value
0
0
NA
0
0
0
NA
3.8.5 PLL Interrupt
The PLOCK bit in the PLLSTA T register is connecte d to the interrupt controller . This allows
for software to turn on the PLL and continue wit h other function s without ha ving t o wait f or
the PLL to achieve lock. When the interrupt occurs (PLOCK
connected, and the interrupt disabled. For details on how to enable and disable the PLL
interrupt, see
page 54 and Section 5.4.5 “Interrupt Enable Clear register (VICIntEnClear 0xFFFF F014)” on page 55.
PLL interrupt is available only in PLL0, i.e. the PLL that generates the CCLK. USB
dedicated PLL1 does not have this capability.
Section 5.4.4 “Interrupt Enable register (VICIntEnable - 0xFFFF F010)” on
= 1), the PLL may be
3.8.6 PLL Modes
The combinations of PLLE and PLLC are shown in Table 19.
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
UM10139
input. This combination can not be used in case of the PLL1 since there will be
MHz clock and the USB can not operate.
no 48
PLOCK is asserted.
connected without also being enabled.
from the PLL0 and the USB clock is sourced from the PLL1.
C0AC)
The two writes must be in the correct sequence, and must be consecutive VPB bus
cycles. The latter requirement implies that interr u p ts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PL LCON or PLLCFG regist er will not
become effective.
7:0PLLFEED The PLL feed sequence must be written to this register in order for
PLL configuration and control register changes to take effect.
3.8.8 PLL and Power-down mode
Pow er-down mode au tomatically turns off and disconnects activated PLL(s) . W akeup from
Power-down mode does not automatically restore the PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
If activity on the USB data lines is not selected to wake up t he microcontroller from
Power-down mode (see
0xE01F C144)” on page 22), both the system and the USB PLL will be automatically be
turned off and disconnected when P ower-down mode is invoked, as described above.
However, in case USBWAKE
Power-down mode and any attempt to set the PD bit will fail, leaving the PLLs in the
current state.
CCLKthe PLL output frequency (also the processor clock frequency)
MPLL Multiplier value from the MSEL bits in the PLLCFG register
PPLL Divider value from the PSEL bits in the PLLCFG register
The PLL output frequency (when the PLL is both active and connected) is given by:
UM10139
the frequency from the crystal oscillator/external oscillator
the frequency of the PLL current controlled oscillator
CCLK = M × F
The CCO frequency can be computed as:
F
= CCLK × 2 × P or F
CCO
The PLL inputs and settings must meet the following:
• F
is in the range of 10 MHz to 25 MHz.
OSC
• CCLK is in the range of 10 MHz to F
microcontroller - determined by the system microcontroller is embedded in).
• F
is in the range of 156 MHz to 320 MHz.
CCO
or CCLK = F
OSC
CCO
CCO
= F
/ (2 × P)
× M × 2 × P
OSC
max
(the maximum allowed frequency for the
3.8.10 Procedure for determining PLL settings
If a particular application uses the PLL0, its configuration ma y be determined as follows:
1. Choose the desired processor operating frequency (CCLK). This may be based on
processor throughput requirements, need to support a specific set of UART baud
rates, etc. Bear in mind that peripheral devices may be running from a lower clock
than the processor (see
2. Choose an oscillator frequency (F
multiple of F
3. Calculate the value of M to configure the MSEL bits. M = CCLK / F
the range of 1 to 32. The value written to the MSEL bits in PLLCFG is M − 1 (see
Table 23.
4. Find a value for P to configure the PSEL bits, such that F
frequency limits. F
of the values 1, 2, 4, or 8. The value written to the PSEL bits in PLLCFG is 00 for
P
= 1; 01 for P = 2; 10 for P = 4; 11 for P = 8 (see Table 22).
OSC
.
Section 3.11 “VPB divider” on page 40).
). CCLK must be the whole (non-fractional)
OSC
is calculated using the equation given above. P must h ave one
CCO
. M must be in
OSC
is within its defined
CCO
Important: if a particular application is using the USB peripheral, the PLL1 must be
configured since this is the only available source of the 48
the USB. This limits the selection of F
Example 1: an application not using the USB - configuring the PLL0
System design asks for F
Based on these specifications, M = CCLK / Fosc = 60 MHz / 10 MHz = 6. Consequently,
M
- 1 = 5 will be written as PLLCFG[4:0].
V alue f or P can be deriv ed from P = F
in range of 156
F
= 156 MHz, P = 156 MHz / (2 x 60 MHz) = 1.3. The highest F
CCO
produces P
listed in
Example 2: an application using the USB - configuring the PLL1
System design asks for F
Based on these specifications, M = 48 MHz / Fosc = 48 MHz / 12 MHz = 4. Consequently ,
M
Value for P can be derived from P = F
be in range of 156
F
CCO
criteria produces P
listed in
program PLLCFG[6:5] in the PLL1.
Table 22 is P = 2. Therefore, PLLCFG[6:5] = 1 will be used.
- 1 = 3 will be written as PLLCFG[4:0].
= 156 MHz, P = 156 MHz / (2 x 48 MHz) = 1.625. The highest F
Table 22 are P = 2 and P = 3. Therefore, either of these two v alues can be used to
MHz to 320 MHz. Assuming the lowest allowed frequency for
= 2.67. The only solution for P that satisf ies both of th ese requir ements and is
MHz to 320 MHz. Assuming the lowest allowed frequency for
= 3.33. Solution for P that satisfy both of these requirements and are
= 10 MHz and requires CCLK = 60 MHz.
OSC
/ (CCLK x 2), using condition that F
CCO
= 12 MHz and requires the USB clock of 48 MHz.
OSC
/ (48 MHz x 2), using condition that F
CCO
CCO
frequency criteria
CCO
CCO
frequency
CCO
must be
must
Example 2 has illustrated the way PLL1 should be configured. Since PLL0 and PLL1 are
independent, the PLL0 can be configured using th e approach described in Example 1.
The LPC2141/2/4/6/8 supports two reduced power modes: Idle mode and Power-down
mode. In Idle mode, e x ecution of inst ructions is suspended until either a Reset or inter rupt
occurs. Peripheral functions continue operation during Idle mode and may generate
interrupts to cause the processor to resume execution. Idle mode eliminates power used
by the processor itself, memory systems and related controllers, and inte rnal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip pins remain static.
The Power-down mode can be terminated and normal operation resumed by either a
Reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
Entry to Power-down and Idle modes must be coordinated with program execution.
Wakeup from Power-down or Idle modes via an interrupt resumes program execution in
such a way that no instructions are lost, incomplete, or repeated. Wake up from
Po wer-down mode is discussed further in
UM10139
Section 3.12 “Wakeup timer” on page 41.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings.
3.9.1 Register description
The Power Control function contains two registers, as shown in Table 24. More detailed
descriptions follow.
Table 24:Power control registers
NameDescriptionAccess Reset
PCONPower Control Register. This register contains
control bits that enable the two reduced power
operating modes of the microcontroller. See
Table 25.
PCONP Power Control for Peripherals Register. This
register contains control bits that enable and
disable individual peripheral functions,
Allowing elimination of power consumption by
peripherals that are not needed.
[1]Reset value reflects the data stored in used bits only. It does not include reserved bits content.
3.9.2 Power Control register (PCON - 0xE01F COCO)
The PCON register contains two bits. Writing a one to the corresponding bit causes entry
to either the Power-down or Idle mode. If both bits are set, Power-down mode is entered.
Table 25:Power Control register (PCON - address 0xE01F COCO) bit description
BitSymbolDescriptionReset
0IDLIdle mode - when 1, this bit causes the processor clock to be stopped,
1PDPower-down mode - when 1, this bit causes the oscillator and all
2PDBODWhen PD is 1 and this bit is 0, Brown Out Detection (BOD) remains
3BODPDM When this bit is 1, the BOD circuitry will go into power down mode when
4BOGDBrown Out Global Disable. When this bit is 1, the BOD circuitry is fully
5BORDBrown Out Reset Disable. When this bit is 1, the second stage of low
7:6-Reserved, user software should not write ones to reserved bits. The
UM10139
while on-chip peripherals remain active. Any enabled interrupt from a
peripheral or an external interrupt source will cause the processor to
resume execution.
on-chip clocks to be stopped. A wakeup condition from an external
interrupt can cause the oscillator to restart, the PD bit to be cleared,
and the processor to resume execution.
IMPORTANT: PD bit can be set to 1 at any time if USBWAKE = 0. In
case of USBWAKE
USB_need_clock
USB_need_clock equal 1 prevents the microcontroller from
entering Power-down mode. (For additional details see
“Interrupt Wakeup register (INTW AKE - 0xE01F C144)” on page 22 and
Section 14.7.1 “USB Interrupt Status register (USBIntSt 0xE01F C1C0)” on page 200)
operative during Power-down mode, such that its Reset can release the
microcontroller from Power-down mode
both 1, the BOD circuit is disabled during Power-down mode to
conserve power. When PD is 0, the state of this bit has no effect.
chip power down is asserted, resulting in a further reduction in power.
However, the possibility of using BOD as a wakeup source from Power
Down mode will be lost. When this bit is 0, BOD stays active during
Power Down mode.
disabled at all times, and will not consume power. When 0, the BOD
circuitry is enabled.
voltage detection (2.6
the reset is enabled. The first stage of low voltage detection (2.9 V)
Brown Out interrupt is not affected.
value read from a reserved bit is not defined.
= 1, it is possible to set PD to 1 only if
= 0. Having both USBWAKE and
[1]
. When PD and this bit are
V) will not cause a chip reset. When BORD is 0,
Section 3.5.3
value
0
0
0
0
0
0
NA
[1] Since execution is delayed until after the Wakeup Timer has allowed the main oscillator to resume stable
operation, there is no guarantee that execution will resume before V
threshold, which prevents execution. If execution does resume, there is no guarantee of how long the
microcontroller will continue execution before the lower BOD threshold terminates execution. These issues
depend on the slope of the decline of V
vicinity of the microcontroller will improve the likelihood that software will be able to do what needs to be
done when power is being lost.
. High decoupling capacitance (between VDD and ground) in the
DD
has fallen below the lower BOD
DD
3.9.3 Power Control for Peripherals register (PCONP - 0xE01F COC4)
The PCONP register allows turning off selected peripheral functions for the purpose of
saving power. This is accomplished by gating off the clock source to the specified
peripheral blocks . A f ew p eripheral functions cannot b e turned off (i.e. the W at chdog timer,
GPIO, the Pin Conn ect block, and the System Control block). Some peripherals,
particularly those that include analog functions, may consume power that is not clock
dependent. These peripherals may contain a separate disable control that turns off
additional circuitry to reduce power. Each bit in PCONP controls one of the peripherals.
The bit numbers correspond to the related peripheral number as shown in the VPB
peripheral map
Memory Addressing " cha p ter.
UM10139
Table 2 “VPB peripheries and base addresses” in the "LPC2141/2/4/6/8
If a peripheral control bit is 1, that peripheral is enabled. If a peripheral bit is 0, that
peripheral is disabled to conserve power. For example if bit 19 is 1, the I
enabled. If bit 19 is 0, the I
Important: valid read from a peripheral register and valid write to a peripheral
register is possible only if that peripheral is enabled in the PCONP register!
Table 26:Power Control for Peripherals register (PCONP - address 0xE01F C0C4) bit
description
BitSymbolDescriptionReset
0-Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
1PCTIM0Timer/Counter 0 power/clock control bit.1
2PCTIM1Timer/Counter 1 power/clock control bit.1
3PCUART0 UART0 power/clock control bit.1
4PCUART1 UART1 power/clock control bit.1
5PCPWM0PWM0 power/clock control bit.1
6-Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
7PCI2C0The I2C0 interface power/clock control bit.1
8PCSPI0The SPI0 interface power/clock control bit.1
9PCRTCThe RTC power/clock control bit.1
10PCSPI1The SSP interface power/clock control bit.1
11-Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
12PCAD0A/D converter 0 (ADC0) power/clock control bit.
Note: Clear the PDN bit in the AD0CR before clearing this bit, and set
this bit before setting PDN.
18:13 -Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
19PCI2C1The I2C1 interface power/clock control bit.1
20PCAD1A/D converter 1 (ADC1) power/clock control bit.
Note: Clear the PDN bit in the AD1CR before clearing this bit, and set
this bit before setting PDN.
30:21 -Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
31PUSBUSB power/cloc k co nt ro l bi t.0
After every reset, the PCONP register contains the value that enables all interfaces and
peripherals controlled by the PCONP to be enabled. Therefore, apart from proper
configuring via peripheral dedicated registers, the user’s application has no need to
access the PCONP in order to start using any of the on-board peripherals.
Power saving oriented systems should have 1s in the PCONP register only in positi ons
that match peripherals really used in the application. All other bits, declared to be
"Reserved" or dedicated to the peripherals not used in the curr ent application, must be
cleared to 0.
3.10 Reset
Reset has two sources on the LPC2141/2/4/6/8: the RESET pin and Watchdog Reset.
The
RESET pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of
chip Reset by any source starts the Wakeup Timer (see description in
“Wakeup timer” in this chapter), causing reset to remain asserted until the external Reset
is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the
on-chip circuitry has completed its initialization. The relationship between Reset, the
oscillator, and the Wakeup Timer are shown in
UM10139
Section 3.12
Figure 10.
The Reset glitch filter allows the processor to ignore external reset pulses that are very
short, and also determines the minimum duration of
order to guarantee a chip reset. Once asserted,
crystal oscillator is fully running and an adequate signal is present on the X1 pin of the
microcontroller. Assuming that an external crystal is used in the crystal oscillator
subsystem, after power on, the
subsequent resets when crystal oscillator is already running and stable signal is on the X1
pin, the
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the Boot Block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
External and internal Resets have some small differences. An external Reset causes the
value of certain pins to be latched to configure the part. External circuitry cannot
determine when an internal Reset occurs in order to allow setting up those special pins,
so those latches are not reloaded during an internal Reset. Pins that are e x amined during
an external Reset for various purposes are: P1.20/TRACESYNC , P1.26/RTCK (see
chapters "Pin Configuration" on
(see "Flash Memory System and Programming" chapter on page 291) is examined by
on-chip bootloader when this code is executed after ev ery Reset.
It is possible for a chip Reset to occur during a Flash programming or erase operation.
The Flash memory will interrupt the ongoing operation and hold off the completion of
Reset to the CPU until internal Flash high voltages have settled.
RESET pin needs to be asserted for 300 ns only.
RESET pin should be asserted for 10 ms. For all
page 66 and "Pin Connect Block" on page 75). Pin P0.14
This register contains one bit for each source of Reset. Writing a 1 to any of these bits
clears the corresponding read-side bit to 0. The interactions among the four sources are
described below.
T able 27: Reset Source identification Register (RSIR - address 0xE01F C180) bit description
BitSymbol DescriptionReset
0PORPow er-On Reset (POR) e vent sets this bit, and clears all of the other bits
in this register. But if another Reset signal (e.g., External Reset) remains
asserted after the POR signal is negated, then its bit is set. This bit is not
affected by any of the other sources of Reset.
1EXTRAssertion of the RESET signal sets this bit. This bit is cleared by POR,
T able 27: Reset Source identification Register (RSIR - address 0xE01F C180) bit description
BitSymbol DescriptionReset
2WDTRThis bit is set when the Watchdog Timer times out and the WDTRESET
3BODRThis bit is set when the 3.3 V power reaches a level below 2.6 V. If the
7:4-Reserved, user software should not write ones to reserved bits. The
3.11 VPB divider
The VPB Divider determines the relationship between the processor cloc k (CCLK) and the
clock used by peripheral devices (PCLK). The VPB Divider serves two purposes.
UM10139
bit in the Watchdog Mode Register is 1. It is cleared by any of the other
sources of Reset.
voltage dips fr om 3.3 V to 2.5 V and backs up, the BODR bit will be
V
DD
set to 1. Also, if the V
level above 2.6 V, the BODR will be set to 1, too. This bit is not affected
by External Reset nor Watchdog Reset.
Note: only in case a reset occurs and the bit POR = 0, the BODR bit
indicates if the VDD voltage was below 2.6 V or not.
value read from a reserved bit is not defined.
voltage rises continuously from below 1 V to a
DD
value
see text
see text
NA
The first is to provides peripherals with desired PCLK via VPB bus so that they can
operate at the speed chosen for the ARM processor. In order to achieve this, the VPB b us
may be slowed down to one half or one fourth of the processor clock rate. Because the
VPB bus must work properly at power up (and its timing cannot be altered if it does not
work since the VPB divider control registers reside on the VPB bus), the default condition
at reset is for the VPB bus to run at one quarter speed.
The second purpose of the VPB Divider is to allow power savings when an application
does not require any peripherals to run at the full processor rate.
The connection of the VPB Divider relative to the oscillator and the processor clock is
shown in
remains active (if it was running) during Idle mode.
Figure 11. Because the VPB Divider is connected to the PLL output, the PLL
3.11.1 Register description
Only one register is used to control the VPB Divider.
Table 28:VPB divider register map
NameDescriptionAccess Reset
VPBDIVControls the rate of the VPB clock in relation to
the processor clock.
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Address
[1]
value
R/W0x000xE01F C100
3.11.2 VPBDIV register (VPBDIV - 0xE01F C100)
The VPB Divider register contains two bits, allowing three divider values, as shown in
1:0VPBDIV 00VPB bus clock is one fourth of the processor clock.00
7:2--Reserved, user software should not write ones to reserved
external clock source
01VPB bus clock is the same as the processor clock.
10VPB bus clock is one half of the processor clock.
11Reserved. If this value is written to the VPBDIV register, it
Crystal oscillator
or
)
(F
OSC
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has no effect (the previous setting is retained).
bits. The value read from a reserved bit is not defined.
PLL0
Processor clock
(CCLK)
value
NA
Fig 11. VPB divider connections
3.12 Wakeup timer
The purpose of the wakeup timer is to ensure that the oscillator and other analog
functions required for chip operation are fully functional before the processor is allowed to
execute instructions. This is important at power on, all types of Reset, and wh en ever any
of the aforementioned functions are turned off for any reason. Since the oscillator and
other functions are turn e d off during Power-down mode, any wakeup of the processor
from Power-down mode makes use of the Wakeup Timer.
The Wakeup Timer monitors the crystal oscillator as the means of checking whether it is
safe to begin code execution. When power is applied to the chip, or some event caused
the chip to exit Power-down mode, some time is required for the oscillator to produce a
signal of sufficient amplitude to drive the clock logic. The amount of time depends on
many factors, including the rate of V
and its electrical characteristics (if a quartz crystal is used), as well as any other external
circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing
ambient conditions.
VPB
DIVIDER
ramp (in the case of power on), the type of crystal
DD
VPB Clock
(PCLK)
Once a clock is detected, the Wakeup Timer counts 4096 clocks, then enables the on-chip
circuitry to initialize. When the onboard m odules initialization is complete, the processor is
released to execute instructions if the external Reset has been deasserted. In the case
where an external clock source is used in the system (as opposed to a crystal connected
to the oscillator pins), the possibility that there could be little or no delay for oscillator
start-up must be considered. The Wakeup Timer design then ensures that any other
required chip functions will be operational prior to the beginning of program execution.
Any of the various Resets can bring the microcontroller out of power-down mode, as can
the external interrupts EINT3:0, plus the R TC interrupt if the R TC is operati ng from its o wn
oscillator on the RTCX1-2 pins. When one of these interrupts is enabled for wakeup and
its selected event occurs, an oscillator w akeup cycle is started. The actual interrupt (if any)
occurs after the wakeup timer expires, and is handled by the Vecto re d Int er rupt Contro ller.
However, the pin multiplexing on the LPC2141/2/4/6/8 (see chapters "Pin Configuration"
on
page 66 and "Pin Connect Block" on page 75) was designed to allow other peripherals
to, in effect, bring the device out of P ower-down mode. The following pin-function pairings
allow interrupts from events relating to UART0 or 1, SPI 0 or 1, or the I
SDA / EINT1, SSEL0 / EINT2, RxD1 / EINT3, DCD1 / EINT1, RI1 / EINT2, SSEL1 /
EINT3.
To put the device in Powe r-down mode and a llow activity on one or more of these b uses or
lines to power it back up, software should reprog r am the pin funct ion to Exte rnal Interrupt,
select the appropriate mode and polarity for the Interrupt, and then select Power-down
mode. Upon wakeup software should restore the pin multiplexing to the peripheral
function.
All of the bus- or line-activity indications in the list above happen to be low-active. If
software wants the device to come out of power -down mode in response to activity on
more than one pin that share the same EINTi channel, it should program low-level
sensitivity for that channel, because only in level mode will the channel logically OR the
signals to wake the device.
UM10139
2
C: RxD0 / EINT0,
The only flaw in this scheme is that the time to restart the oscillator prevents the
LPC2141/2/4/6/8 from capturing the bus or line activity that w ak es it up . Idle mode is more
appropriate than power-do wn mode for devices that must capture and resp ond to e xt ernal
activity in a timely manner.
To summarize: on the LPC2141/2/4/6/8, the Wakeup Timer enforces a minimum reset
duration based on the crystal oscillator, and is activated whenever there is a wakeup from
Power-down mode or any type of Reset.
3.13 Brown-out detection
The LPC2141/2/4/6/8 includes 2-stage monitoring of the voltage on the VDD pins. If this
voltage fa lls be low 2.9
Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt
Enable register (see
0xFFFF F010)” on page 54); if not, software can monitor the signal by reading the Raw
Interrupt Status register (see Section 5.4.3 “Raw Interrupt status register (VICRawIntr -
0xFFFF F008)” on page 54).
The second stage of low-voltage detection asserts Reset to inactivate the
LPC2141/2/4/6/8 when the voltage on the V
alteration of the Flash as operation of the various elements of the chip would otherwise
become unreliable due to low voltage. The BOD circuit maintains this reset down below
1
V, at which point the Power-On Reset circuitry maintains the overall Reset.
V, the Brown-Out Detector (BOD) asserts an interrupt signal to the
V detection to reliably interrupt, or a regularly-executed event
Philips Semiconductors
Volume 1Chapter 3: System Control Block
But when Brown-Out Detection is enabled to bring the LPC2141/2/4/6/8 out of
Pow er-Do wn mode (which is itself not a guar antee d operat ion -- see
Control register (PCON - 0xE01F COCO)”), the supply voltage may recover from a
transient before the Wakeup Timer has completed its delay. In this case, the net result of
the transient BOD is that the part wakes up a nd continues operation after the instructions
that set Power-Down Mode, without any interrupt occurring and with the BOD bit in the
RISR being 0. Since all other wakeu p conditions have latching flags (see
“External Interrupt Flag register (EXTINT - 0xE01F C140)” and Section 19.4.3 “Interrupt
Location Register (ILR - 0xE002 4000)” on page 277), a wakeup of this type, without any
apparent cause, can be assumed to be a Brown-Out that has gone away.
3.14 Code security vs. debugging
Applications in development typically need the deb ugging and tracing facilities in the
LPC2141/2/4/6/8. Later in the life cycle of an application, it may be more important to
protect the application code from observation b y hostile or competitiv e e y es. Th e f ollowing
feature of the LPC2141/2/4/6/8 allows an application to control whether it can be
debugged or protected from observation.
UM10139
Section 3.9.2 “Power
Section 3.5.2
Details on the way Code Read Protection works can be found in the "Flash Memory
System and Programming" chapter on
The MAM block in the LPC2141/2/4/6/8 maximizes the performance of the ARM
processor when it is running code in Flash memory, but does so using a single Flash
bank.
Simply put, the Memory Accelerator Module (MAM) attempts to have the next ARM
instruction that will be needed in its latches in time to prevent CPU fetch stalls. The
LPC2141/2/4/6/8 uses one bank of Flash memory, compared to the two banks used on
predecessor devices. It includes three 128-bit buffers called the Prefetch Buffer, the
Branch Trail Buffer and the Data Buffer. When an Instruction Fetch is not satisfied by
either the Pref etch o r Br anch Trail buffe r, nor has a prefetch been initiate d for that line, the
ARM is stalled while a fetch is initiated for the 128-bit line. If a prefetch has been initiated
but not yet completed, the ARM is stalled for a shorter time. Unless aborted by a data
access, a prefetch is initiated as soon as the Flash has completed the previous access.
The prefetched line is latched b y th e Flash module , b ut th e MAM does not capt ure the li ne
in its prefetch bu ffer until the ARM core presents the address from which the prefe tch has
been made. If the core presents a different address from the one from which the prefetch
has been made, the prefetched line is discarded.
The Prefetch and Branch Trail Buffers each include four 32-bit ARM instructions or eight
16-bit Thumb instructions. During sequential code execution, typically the prefetch buffer
contains the current instruction and the entire Flash line that contains it.
The MAM uses the LPROT[0] line to differentiate between instruction and data accesses.
Code and data accesses use separat e 128-bit buffers. 3 of e very 4 sequential 32-bit code
or data accesses "hit" in the buffer without requiring a Flash access (7 of 8 sequential
16-bit accesses, 15 of every 16 sequential byte accesses). The fourth (eighth, 16th)
sequential data access must access Flash, aborting any prefetch in progress. When a
Flash data access is concluded, any prefetch that had been in progress is re-initiated.
Timing of Flash read operations is programmable and is described later in this section.
In this manner , there is no code f etch penalty f or sequenti al instruction ex ecution when the
CPU clock period is greater than or equal to one fourth of the Flash access time. The
average amount of time spent doing program branches is relatively small (less than 25%)
and may be minimized in ARM (rather than Thumb) code through the use of the
conditional execution feature present in all ARM instructions. This conditional execution
may often be used to a void small forward branches that wo uld otherwise be necessary.
Branches and other program flow changes cause a break in the sequential flow of
instruction fetches described above. The Branch Trail Buffer captures the line to which
such a non-sequential break occurs. If the same branch is taken again, the next
instruction is taken from the Branch Trail Buffer. When a branch outside the contents of
the Prefetch and Bra nch Trail Buffer is tak en, a stall of se v er al cloc ks is needed to load the
Branch Trail Buffer. Subsequently, there will typically be no further instructionfetch delays
until a new and different branch occurs.
4.3 MAM blocks
The Memory Accelerator Module is divided into several functional blocks:
• A Flash Address Latch and an incrementor function to form prefetch addresses
• A 128-bit Prefetch Bu ffer and an associated Address latch and comparator
• A 128-bit Branch Trail Buffer and an associated Address latch and comparator
• A 128-bit Data Buffer and an associated Address latch and comparator
• Control logic
• Wait logic
Figure 12 shows a simplified bloc k diag ram of the Memory Accelerator Module da ta paths .
In the following descriptions , the term “f etch” applies to an e xplicit Fla sh read request from
the ARM. “Pre-fetch” is used to denote a Flash read of instructions beyond the current
processor fetch address.
UM10139
4.3.1 Flash memory bank
There is one bank of Flash memory with the LPC2141/2/4/6/8 MAM.
Flash programming operations are not controlled by the MAM, but are handled as a
separate function. A “boot block” sector contains Flash programming algorithms that may
be called as part of the application program, and a loader that may be run to allow serial
programming of the Flash memory.
ARM Local Bus
Memory Address
Flash Memory
Bank
BUS
INTERFACE
BUFFERS
Memory Data
Fig 12. Simplified block diagram of the Memory Accelerator Module (MAM)
Code and Data accesses are treated separately by the Memory Accelerator Module.
There is a 128-bit Latch, a 15-bit Address
Latch, and a 15-bit comparator associated with each buffer (prefetch, branch trail, and
data). Each 128-bit latch holds 4 words (4 ARM instructions, or 8 Thumb instructions).
Also associated with each buffer are 32 4:1 Multiplexers that select the requested word
from the 128-bit line.
Each Data access that is not in the Data latch causes a Flash fetch of 4 words of data,
which are captured in the Data latch. This speeds up sequential Data operations, but has
little or no effect on random accesses.
4.3.3 Flash programming Issues
Since the Flash memory does not allow accesses during programming and erase
operations, it is necessary for the MAM to force the CPU to wait if a memory access to a
Flash address is requested while the Flash module is busy. (This is accomplished by
asserting the ARM7TDMI-S local bus signal CLKEN.) Under some conditions, this delay
could result in a Watchdog time-out. The user will need to be aware of this possibility and
take steps to insure that an unwanted Watchdog reset does not cause a system failure
while programming or erasing the Flash memory.
UM10139
In order to preclude the possibility of stale data being read from the Flash memory, the
LPC2141/2/4/6/8 MAM holding latches are automatically invalidated at the beginning of
any Flash programming or erase operation. Any subsequent read from a Flash address
will cause a new fetch to be initiated after the Flash operation has completed.
4.4 MAM operating modes
Three modes of operation are defined for the MAM, trading off perf ormance for ease of
predictability:
Mode 0: MAM off. All memory requests result in a Flash read operat ion (see note 2
below). There are no instruction prefetches.
Mode 1: MAM partially enabled. Sequential instruction accesses are fulfilled from the
holding latches if the data is present. Instruction prefetch is enabled. Non-sequential
instruction accesses initiate Flash read operations (see note 2 below). This means that
all branches cause memory fetches. All data oper ations cause a Flash read because
buffer ed data access timing is hard to predict and is very situation dependent.
Mode 2: MAM fully enabled. An y memory request (code or data) for a value that is
contained in one of the corresponding holding latches is fulfilled from the latch.
Instruction prefetch is enabled. Flash read operations are initiated for instruction
prefetch and code or data values not available in the corresponding holding latches.
Table 30:MAM Responses to program accesses of various types
Program Memory Request TypeMAM Mode
Sequential access, data in latchesInitiate Fetch
Sequential access, data not in latchesInitiate FetchInitiate Fetch
Non-sequential access, data in latchesInitiate Fetch
Non-sequential access, data not in latches Initiate FetchInitiate Fetch
[1] Instruction prefetch is enabled in modes 1 and 2.
[2] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
Table 31:MAM responses to data and DMA accesses of various types
Data Memory Request TypeMAM Mode
Sequential access, data in latchesInitiate Fetch
Sequential access, data not in latchesInitiate FetchInitiate FetchInitiate Fetch
Non-sequential access, data in latchesInitiate Fetch
Non-sequential access, data not in latches Initiate FetchInitiate FetchInitiate Fetch
UM10139
012
[2]
Use Latched
[1]
Data
[1]
[2]
Initiate Fetch
012
[1]
Initiate Fetch
[1]
Initiate Fetch
[1][2]
[1]
[1]
[1]
Use Latched
[1]
Data
Initiate Fetch
Use Latched
[1]
Data
Initiate Fetch
Use Latched
Data
Use Latched
Data
[1]
[1]
[1] The MAM actually uses latched data if it is available, but mimics the timing of a Flash read operation. This
saves power while resulting in the same execution timing. The MAM can truly be turned off by setting the
fetch timing value in MAMTIM to one clock.
4.5 MAM configuration
After reset the MAM defaults to the disabled state. Software can turn memory access
acceleration on or off at any time. This allows most of an application to be run at the
highest possible performance, while certain functions can be run at a somewhat slower
but more predictable rate if more precise timing is required.
4.6 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
Determines the MAM functional mode, that is, to
what extent the MAM performance enhancements
are enabled. See
MAMTIM Memory Accelerator Module Timing control.
Determines the number of clocks used for Flash
memory fetches (1 to 7 processor clocks).
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 33.
4.7 MAM Control Register (MAMCR - 0xE01F C000)
Two configuration bits select the three MAM operating modes, as shown in Table 33.
Following Rese t, MAM functions ar e disable d. Changing the MAM op erating mode causes
the MAM to invalidate all of the holding latche s, resulti ng in new r eads of Flash inf ormation
as required.
UM10139
Address
[1]
value
R/W0x00xE01F C000
R/W0x070xE01F C004
Table 33:MAM Control Register (MAMCR - address 0xE01F C000) bit description
BitSymbolValueDescriptionReset
1:0MAM_mode
_control
7:2--Reserved, user software should not write ones to reserved
00MAM functions disabled0
01MAM functions partially enabled
10MAM functions fully enabled
11Reserved. Not to be used in the application.
bits. The value read from a reserved bit is not defined.
4.8 MAM Timing register (MAMTIM - 0xE01F C004)
The MAM Timing register determines how many CCLK cycles are used to access the
Flash memory. This allows tuning MAM timing to match the processor operating
frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash
accesses would essentially remov e the MAM from timing calculations. In this case the
MAM mode may be selected to optimize power usage.
0011 - MAM fetch cycles are 1 processor clock (CCLK) in
duration
0102 - MAM fetch cycles are 2 CCLKs in duration
0113 - MAM fetch cycles are 3 CCLKs in duration
1004 - MAM fetch cycles are 4 CCLKs in duration
1015 - MAM fetch cycles are 5 CCLKs in duration
7:3--Reserved, user software should not write ones to reserved
4.9 MAM usage notes
When changing MAM timing, the MAM must first be turned off by writing a zero to
MAMCR. A new value may then be written to MAMTIM. Finally, the MAM may be turned
on again by writing a value (1 or 2) corresponding to the desired operating mode to
MAMCR.
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value
1106 - MAM fetch cycles are 6 CCLKs in duration
1117 - MAM fetch cycles are 7 CCLKs in duration
Warning: These bits set the duration of MAM Flash fetch operations
as listed here. Improper setting of this value may result in incorrect
operation of the device.
NA
bits. The value read from a reserved bit is not defined.
For system clock slower than 20 MHz, MAMTIM can be 001. For system clock between
20
MHz and 40 MHz, Flash access time is suggested to be 2 CCLKs, while in systems
• 16 priority levels dynamically assigned to interrupt requests
• Software interrupt generation
The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and
programmably assigns the m into 3 cat egories , FIQ, vectored IRQ, and non-vectored IRQ.
The programmable assignment scheme means that priorities of interrupts from the
various peripherals can be dynamically assigned and adjusted.
Fast Inter rupt reQuest (FIQ) requests hav e the hig hest priority. If more than one request is
assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM
processor. The fastest possible FIQ latency is achieved when only one request is
classified as FIQ, because then the FIQ service routine can simply start dealing with that
device. But if more than one request is assigned to the FIQ class, the FIQ service routine
can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an
interrupt.
Vectored IRQs have the middle priority, but only 16 of the 32 requests can be assigned to
this category. Any of the 32 requests can be assigned to an y of the 16 v ectored I RQ slots ,
among which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the
IRQ signal to the ARM processor. The IRQ service routine can start by reading a register
from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC
provides the address of the highest-priority requesting IRQs service routine, otherwise it
provides the address of a default routine that is shared by all the non-vectored IRQs. The
default routine can read another VIC register to see what IRQs are active.
All registers in the VIC are word registers. Byte and halfword reads and write are not
supported.
Additional information on the Vectored Interrupt Controller is available in the ARM
PrimeCell™ Vectored Interrupt Controller (PL190) documentation.
5.3 Register description
The VIC implements the registers shown in Table 35. More detailed descriptions follo w.
VICVectAddr12Vector address 12 register.R/W00xFFFF F130
VICVectAddr13Vector address 13 register.R/W00xFFFF F134
VICVectAddr14Vector address 14 register.R/W00xFFFF F138
VICVectAddr15Vector address 15 register.R/W00xFFFF F13C
VICVectCntl0Vector control 0 register . Vector Control Registers 0-15 each
control one of the 16 vectored IRQ slots. Slot 0 has the
highest priority and slot 15 the lowest.
VICVectCntl1Vector control 1 register.R/W00xFFFF F204
VICVectCntl2Vector control 2 register.R/W00xFFFF F208
VICVectCntl3Vector control 3 register.R/W00xFFFF F20C
VICVectCntl4Vector control 4 register.R/W00xFFFF F210
VICVectCntl5Vector control 5 register.R/W00xFFFF F214
VICVectCntl6Vector control 6 register.R/W00xFFFF F218
VICVectCntl7Vector control 7 register.R/W00xFFFF F21C
VICVectCntl8Vector control 8 register.R/W00xFFFF F220
VICVectCntl9Vector control 9 register.R/W00xFFFF F224
VICVectCntl10Vector control 10 register.R/W00xFFFF F228
VICVectCntl11Vector control 11 register.R/W00xFFFF F22C
VICVectCntl12Vector control 12 register.R/W00xFFFF F230
VICVectCntl13Vector control 13 register.R/W00xFFFF F234
VICVectCntl14Vector control 14 register.R/W00xFFFF F238
VICVectCntl15Vector control 15 register.R/W00xFFFF F23C
R/W00xFFFF F200
UM10139
Address
[1]
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
5.4 VIC registers
The following section de scribes the VIC registers in the order in which the y are used in the
VIC logic, from those closest to the interrupt request inputs to those most abstracted for
use by software. For most people, this is also the best order to read about the registers
when learning the VIC.
5.4.3 Raw Interrupt status register (VICRawIntr - 0xFFFF F008)
This is a read only register. This register reads out the state of the 32 interrupt requests
and software interrupts, regardless of enabling or classification.
Table 40:Raw Interrupt status register (VICRawIntr - address 0xFFFF F008) bit allocation
0The interrupt request with this bit number is assigned to the IRQ
category.
1The interrupt request with this bit number is assigned to the FIQ
category.
UM10139
value
0
5.4.7 IRQ Status register (VICIRQStatus - 0xFFFF F000)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as IRQ. It does not differentiate between v ectored and
non-vectored IRQs.
Table 48:IRQ Status register (VICIRQStatus - address 0xFFFF F000) bit allocation
5.4.8 FIQ Status register (VICFIQStatus - 0xFFFF F004)
This is a read only register. This register reads out the state of those interrupt requests
that are enabled and classified as FIQ. If more than one request is classified as FIQ, the
FIQ service routine can read this register to see which request(s) is (are) active.
Table 50:FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit allocation
Table 51:FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit description
BitSymbolDescriptionReset
31:0See
VICFIQStatus
bit allocation
table.
A bit read as 1 indicates a corresponding interrupt request being enabled,
classified as FIQ, and asserted
value
0
5.4.9 Vector Control registers 0-15 (VICVectCntl0-15 - 0xFFFF F200-23C)
These are a read/write accessible registers. Each of these registers cont rols one of the 16
vectored IRQ slots. Slot 0 has the highest priority and slot 15 the lowest. Note that
disabling a vectored IRQ slot in one of the VICVectCntl registers does not disable the
interrupt itself, the interrupt is simply changed to the non -vectored form.
Table 52:Vector Control registers 0-15 (VICVectCntl0-15 - 0xFFFF F200-23C) bit description
BitSymbolDescriptionReset
value
4:0int_request/
sw_int_assig
5IRQslot_enWhen 1, this vectored IRQ slot is enabled, and can produce a unique ISR
31:6-Reserved, user software should not write ones to reserved bits. The value read
The number of the interrupt request or software interrupt assigned to this
vectored IRQ slot. As a matter of good programming practice, software should
not assign the same interrupt number to more than one enabled vectored IRQ
slot. But if this does occur, the lower numbered slot will be used when th e
interrupt request or software interrupt is enabled, classified as IRQ, and
asserted.
address when its assigned interrupt request or software interrupt is enabled,
classified as IRQ, and asserted.
These are a read/write accessible registers. These registers hold the addresses of the
Interrupt Service routines (ISRs) for the 16 vectored IRQ slots.
31:0IRQ_vectorWhen one or more interrupt request or software interrupt is (are) enabled,
classified as IRQ, asserted, and assigned to an enabled vectored IRQ slot,
the value from this register for the highest-priority such slot will be provided
when the IRQ service routine reads the Vector Address register -VICVectAddr
31:0IRQ_vectorIf any of the interrupt requests or software interrupts that are assigned to a
vectored IRQ slot is (are) enabled, classified as IRQ, and asserted, reading
from this register returns the address in the Vector Address Register for the
highest-priority such slot (lowest-numbered) such slot. Otherwise it returns the
address in the Default Vector Address Register.
Writing to this register does not set the value for future reads from it. Rather,
this register should be written near the end of an ISR, to update the priority
hardware.
Table 57 lists the interrupt sources for each peripheral function. Each peripheral device
has one interrupt line connected to the Vectored Interrupt Controller, but ma y ha v e se v eral
internal interrupt flags. Individual interrupt flags may also re present more than one
interrupt source.
Table 57:Connection of interrupt sources to the Vectored Interrupt Controller (VIC)
BlockFlag(s)VIC Channel # and Hex
Mask
WDTWatchdog Interrupt (WDINT)00x0000 0001
-Reserved for Software Interrupts only10x0000 0002
ARM CoreEmbedded ICE, DbgCommRx20x0000 0004
ARM CoreEmbedded ICE, DbgCommTX30x0000 0008
TIMER0Match 0 - 3 (MR0, MR1, MR2, MR3)
Capture 0 - 3 (CR0, CR1, CR2, CR3)
TIMER1Match 0 - 3 (MR0, MR1, MR2, MR3)
Capture 0 - 3 (CR0, CR1, CR2, CR3)
UART0Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
UART1Rx Line Status (RLS)
Transmit Holding Register Empty (THRE)
Rx Data Available (RDA)
Character Time-out Indicator (CTI)
Spurious interrupts are possible in the ARM7TDMI based microcontrollers such as th e
LPC2141/2/4/6/8 due to asynchronous interrupt h andling. The a synch ronou s char acte r of
the interrupt processing has its roots in the interaction of the core and the VIC. If the VIC
state is changed between the moments when the core detects an interrupt, and the core
actually processes an interrupt, problems may be generated.
Real-life applications may experience the following scenarios:
1. VIC decides there is an IRQ interrupt and sends the IRQ signal to the core.
2. Core latches the IRQ state.
3. Processing continues for a few cycles due to pipelining.
4. Core loads IRQ address from VIC.
Furthermore, It is possible that the VIC state has changed during step 3. F or exam ple, VIC
was modified so that the interrupt that triggered the seq uence starting with step 1) is no
longer pending -interrupt got disabled in the ex ecuted code. In this case, the VIC will not
be able to clearly identify the interrupt that generated the interrupt reque st, and as a result
the VIC will return the default interrupt VicDefVectAddr (0xFFFF
UM10139
F034).
This potentially disastrous chain of events can be prevented in two ways:
1. Application code should be set up in a way to prevent the spurious interrupts from
occurring. Simple guarding of changes to the VIC ma y not be enough since, for
example, glitches on level sensitive interrupts can also cause spurious interrupts.
2. VIC default handler should be set up and tested properly.
5.6.1 Details and case studies on spurious interrupts
This chapter contains details that can be obtained from the official ARM website
(http://www.arm.com), FAQ section under the "Technical Support" link:
http://www.arm.com/support/faqip/3677.html.
What happens if an interrupt occurs as it is being disabled?
Applies to: ARM7TDMI
If an interrupt is received by the core during execution of an instruction that disables
interrupts, the ARM7 family will still take the interrupt. This occurs for both IRQ and FIQ
interrupts.
For ex ample, consider the following instruction sequence:
• The MSR cpsr, r0 executes to completion setting both the I bit and the F bit in the
CPSR.
• The IRQ interrupt is taken because the core was committ ed to tak i ng the inte rrupt
exception before the I bit was set in the CPSR.
• The CPSR (with the I bit and F bit set) is moved to the SPSR_IRQ.
This means that, on entry to the IRQ interrupt service routine, you can see the unusual
effect that an IRQ interrupt has just been taken while the I bit in the SPSR is set. In the
example above, the F bit will also be set in both the CPSR and SPSR. This means that
FIQs are disabled upon entry to the IRQ service routine, and will remain so until explicitly
re-enabled. FIQs will not be reenabled automatically by the IRQ return sequence.
Although the example sho ws bot h IRQ and FI Q interrupts being di sabl ed, similar beha vio r
occurs when only one of the two interrupt types is being di sabled. The fact that the core
processes the IRQ after completion of the MSR instruction which disables IRQs does not
normally cause a problem, since an interrupt arriving just one cycle earlier would be
expected to be taken. When the interrupt routine returns with an instruction like:
SUBS pc, lr, #4
UM10139
the SPSR_IRQ is restored to the CPSR. The CPSR will now have the I bit and F bit set,
and therefore execution will continue with all interrupts disabled. However, this can cause
problems in the following cases:
Problem 1: A particular routine maybe called as an IRQ handler, or as a regular
subroutine. In the latter ca se , the system guar antees that IRQs w ould ha ve been disabled
prior to the routine being called. The routine exploits this restriction to determine how it
was called (by examining the I bit of the SPSR), and returns using the appropriate
instruction. If the routine is entered due to an IRQ being received during execution of the
MSR instruction which disables IRQs, then the I bit in the SPSR will be set. The routine
would therefore assume that it could not have been entered via an IRQ.
Problem 2: FIQs and IRQs are bot h disab led by t he same write to the CPSR. In this case ,
if an IRQ is received during the CPSR write, FIQs will be disabled for the ex ecution time of
the IRQ handler. This may not be acceptable in a system where FIQs must not be
disabled for more than a few cycles.
5.6.2 Workaround
There are 3 suggested workarounds. Which of these is most applicable will depend upon
the requirements of the particular system.
5.6.3 Solution 1: test for an IRQ received during a write to disable IRQs
Add code similar to the following at the start of the interrupt routine.
SUB lr, lr, #4 ; Adjust LR to point to return
STMFD sp!, {..., lr} ; Get some free regs
MRS lr, SPSR ; See if we got an interrupt while
TST lr, #I_Bit ; interrupts were disabled.
LDMNEFD sp!, {..., pc}^ ; If so, just return immediately.
; The interrupt will remain pending since we haven’t
; acknowledged it and will be reissued when interrupts
This code will test for the situation where the IRQ was received during a write to disable
IRQs. If this is the case, the code returns immediately - resulting in the IRQ not being
acknowledged (cleared), and further IRQs being disabled.
Similar code may also be applied to the FIQ handler, in order to resolve the first issue.
This is the recommended workaround, as it overcomes both problems mentioned above.
However, in the case of prob lem t w o, it does add sev eral cycles to the maximum length of
time FIQs will be disabled.
5.6.4 Solution 2: disable IRQs and FIQs using separate writes to the CPSR
This is the best workaround where the maximum time for which FIQs are disabled is
critical (it does not increase this time at all). However, it does not solve problem one, and
requires extra instructions at every point where IRQs and FIQs are disabled together.
5.6.5 Solution 3: re-enable FIQs at the beginning of the IRQ handler
As the required state of all bits in the c field of the CPSR are known, this can be most
efficiently be achieved by writing an immediate value to CPSR_C, for example:
MSR cpsr_c, #I_Bit:OR:irq_MODE ;IRQ should be disabled
;FIQ enabled
;ARM state, IRQ mode
This requires only the IRQ handler to be modified, and FIQs may be re-enabled more
quickly than by using workaround 1. However, this should only be used if the system can
guarantee that FIQs are never disabled while IRQs are enabled. It does not address
problem one.
5.7 VIC usage notes
If user code is running from an on-chip RAM and an application uses interrupts, interrupt
vectors must be re-mapped to on-chip address 0x0. This is necessary because all the
exception vectors are located at addresses 0x0 and above. This is easily achieved by
configuring the MEMMAP register (see
(MEMMAP - 0xE01F C040)” on page 26) to User RAM mode. Application code should be
linked such that at 0x4000 0000 the Interrupt Vector Table (IVT) will reside.
Section 3.7.1 “Memory Mapping control register
Although multiple sources can be selected (VICIntSelect) to generate FIQ request, only
one interrupt service routine should be dedicated to service all available/present FIQ
request(s). Therefore, if more than one interrupt sources are classified as FIQ the FIQ
interrupt service routine must read VICFIQStatus to decide based on this content what to
do and how to process the interrupt request. However, it is recommended that only one
interrupt source should be classified as FIQ. Classifying more than one interrupt sources
as FIQ will increase the interrupt latency.
Following the completion of the desired interrupt service routine, clearing of the interrupt
flag on the peripheral level will propagate to corresponding bits in VIC registers
(VICRawIntr, VICFIQStatus and VICIRQStatus). Also, before the next interrupt can be
serviced, it is necessary that write is performed into the VICVectAddr register before the
return from interrupt is executed. This write will clear the respective interrupt flag in the
internal interrupt priority hardware.
In order to disable the interrupt at the VIC you need to clear corresponding bit in the
VICIntEnClr register, which in turn clears the related bit in the VICIntEnable register . This
also applies to the VICSoftInt and VICSoftIntClear in which VICSoftIntClear will clear the
respective bits in VICSoftInt. For example, if VICSoftInt
cleared, VICSoftIntClear
operation on the same bit in VICSoftInt using writing into VICSoftIntClear is performed in
the future, VICSoftIntClear
bit in Clear register will have one-time-effect in the destination register.
UM10139
= 0x0000 0005 and bit 0 has to be
= 0x0000 0001 will accomplish this. Before the new clear
= 0x0000 0000 must be assigned. Therefore writing 1 to any
If the watchdog is enabled for interrupt on underflow or invalid feed sequence only then
there is no way of clearing the interrupt. The only way you could perform return from
interrupt is by disabling the interrupt at the VIC (using VICIntEnClr).
Example:
Assuming that UART0 and SPI0 are generating interrupt requests that are classified as
vectored IRQs (UART0 being on the higher level than SPI0), while UART1 and I
generating non-vectored IRQs, the following could be one possibility for VIC setup:
VICIntSelect = 0x0000 0000 ; SPI0, I2C, UART1 and UART0 are IRQ =>
; bit10, bit9, bit7 and bit6=0
VICIntEnable = 0x0000 06C0 ; SPI0, I2C, UART1 and UART0 are enabled interrupts =>
; bit10, bit9, bit 7 and bit6=1
VICDefVectAddr = 0x... ; holds address at what routine for servicing
; non-vectored IRQs (i.e. UART1 and I2C) starts
VICVectAddr0 = 0x... ; holds address where UART0 IRQ service routine starts
VICVectAddr1 = 0x... ; holds address where SPI0 IRQ service routine starts
VICVectCntl0 = 0x0000 0026 ; interrupt source with index 6 (UART0) is enabled as
; the one with priority 0 (the highest)
VICVectCntl1 = 0x0000 002A ; interrupt source with index 10 (SPI0) is enabled
; as the one with priority 1
After any of IRQ requests (SPI0, I2C, UART0 or UART1) is made, microcontroller will
redirect code execution to the address specified at location 0x0000
and non-vectored IRQ’s the following instruction could be placed at 0x0000
2
C are
0018. For vectored
0018:
LDR pc, [pc,#-0xFF0]
This instruction loads PC with the address that is present in VICVectAddr register.
In case UART0 request has been made, VICVectAddr will be identical to VICVectAddr0,
while in case SPI0 request has been made value from VICVectAddr1 will be found here. If
neither UART0 nor SPI0 have generated IRQ request but UART1 and/or I
reason, content of VICVectAddr will be identical to VICDefVectAddr.
P0.0 to P0.31I/OPort 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit.
Total of 28 pins of the Port 0 can be used as a general purpose bi-directional
digital I/Os while P0.31 provides digital output functions only. The operation of
port 0 pins depends upon the pin function selected via the pin connect block.
Pins P0.24, P0.26 and P0.27 are not available.
P0.0/TXD0/
PWM1
P0.1/RxD0/
PWM3/EINT0
P0.2/SCL0/
CAP0.0
P0.3/SDA0/
MAT0.0/EINT1
P0.4/SCK0/
CAP0.1/AD0.6
P0.5/MISO0/
MAT0.1/AD0.7
P0.6/MOSI0/
CAP0.2/AD1.0
P0.7/SSEL0/
PWM2/EINT2
19
21
22
26
27
29
30
31
[1]
[2]
[3]
[3]
[4]
[4]
[4]
[2]
I/OP0.0 — General purpose digital input/output pin
OTXD0 — Transmitter output for UART0
OPWM1 — Pulse Width Modulator output 1
I/OP0.1 — General purpose digital input/output pin
IRxD0 — Receiver input for UART0
OPWM3 — Pulse Width Modulator output 3
IEINT0 — External interrupt 0 input
I/OP0.2 — General purpose digital input/output pin
I/OSCL0 — I2C0 clock input/output. Open drain output (for I2C compliance)
ICAP0.0 — Capture input for Timer 0, channel 0
I/OP0.3 — General purpose digital input/output pin
I/OSDA0 — I2C0 data input/output. Open drain output (for I2C compliance)
OMAT0.0 — Match output for Timer 0, channel 0
IEINT1 — External interrupt 1 input
I/OP0.4 — General purpose digital input/output pin
I/OSCK0 — Serial clock for SPI0. SPI clock output from master or input to slave
ICAP0.1 — Capture input for Timer 0, channel 0
IAD0.6 — A/D converter 0, input 6. This analog input is always connected to
its pin
I/OP0.5 — General purpose digital input/output pin
I/OMISO0 — Master In Slave OUT for SPI0. Data input to SPI master or data
output from SPI slave
OMAT0.1 — Match output for Timer 0, channel 1
IAD0.7 — A/D converter 0, input 7. This analog input is always connected to
its pin
I/OP0.6 — General purpose digital input/output pin
I/OMOSI0 — Master Out Slave In for SPI0. Data output from SPI master or data
input to SPI slave
ICAP0.2 — Capture input for Timer 0, channel 2
IAD1.0 — A/D converter 1, input 0. This analog input is always connected to
its pin. Available in LPC2144/6/8 only.
I/OP0.7 — General purpose digital input/output pin
ISSEL0 — Slave Select for SPI0. Selects the SPI interface as a slave
OPWM2 — Pulse Width Modulator output 2
IEINT2 — External interrupt 2 input
I/OP0.8 — General purpose digital input/output pin
OTXD1 — Transmitter output for UART1
OPWM4 — Pulse Width Modulator output 4
IAD1.1 — A/D converter 1, input 1. This analog input is always connected to
its pin. Available in LPC2144/6/8 only
I/OP0.9 — General purpose digital input/output pin
IRxD1 — Receiver input for UART1
OPWM6 — Pulse Width Modulator output 6
IEINT3 — External interrupt 3 input
I/OP0.10 — General purpose digital input/output pin
ORTS1 — Request to Send output for UART1. Available in LPC2144/6/8 only.
ICAP1.0 — Capture input for Timer 1, channel 0
IAD1.2 — A/D converter 1, input 2. This analog input is always connected to
its pin. Available in LPC2144/6/8 only.
I/OP0.11 — General purpose digital input/output pin
ICTS1 — Clear to Send input for UART1. Available in LPC2144/6/8 only.
ICAP1.1 — Capture input for Timer 1, channel 1.
I/OSCL1 — I2C1 clock input/output. Open drain output (for I2C compliance)
I/OP0.12 — General purpose digital input/output pin
IDSR1 — Data Set Ready input for UART1. Available in LPC2144/6/8 only.
OMAT1.0 — Match output for Timer 1, channel 0.
IAD1.3 — A/D converter input 3. This analog input is always connected to its
pin. Available in LPC2144/6/8 only.
I/OP0.13 — General purpose digital input/output pin
ODTR1 — Data Terminal Ready output for UART1. Available in LPC2144/6/8
only.
OMAT1.1 — Match output for Timer 1, channel 1.
IAD1.4 — A/D converter input 4. This analog input is always connected to its
pin. Available in LPC2144/6/8 only.
I/OP0.14 — General purpose digital input/output pin
IDC D1 — Data Carrier Detect input for UAR T1. Available in LPC2144/6/8 only .
IEINT1 — External interrupt 1 input
I/OSDA1 — I2C1 data input/output. Open drain output (for I2C compliance)
Note: LOW on this pin while RESET is LOW forces on-chip boot-loader to
take over control of the part after reset.
I/OP0.15 — General purpose digital input/output pin
IRI1 — Ring Indicator input for UART1. Available in LPC2144/6/8 only.
IEINT2 — Exte rnal interrupt 2 input.
IAD1.5 — A/D converter 1, input 5. This analog input is always connected to
I/OP0.16 — General purpose digital input/output pin
IEINT0 — Exte rnal interrupt 0 input.
OMAT0.2 — Match output for Timer 0, channel 2.
ICAP0.2 — Capture input for Timer 0, channel 2.
I/OP0.17 — General purpose digital input/output pin
ICAP1.2 — Capture input for Timer 1, channel 2.
I/OSCK1 — Serial Clock for SSP. Clock output from master or input to slave.
OMAT1.2 — Match output for Timer 1, channel 2.
I/OP0.18 — General purpose digital input/output pin
ICAP1.3 — Capture input for Timer 1, channel 3.
I/OMISO1 — Master In Slave Out for SSP. Data input to SPI master or data
output from SSP slave.
OMAT1.3 — Match output for Timer 1, channel 3.
I/OP0.19 — General purpose digital input/output pin
OMAT1.2 — Match output for Timer 1, channel 2.
I/OMOSI1 — Master Out Slave In for SSP. Data output from SSP master or data
input to SSP slave.
ICAP1.2 — Capture input for Timer 1, channel 2.
I/OP0.20 — General purpose digital input/output pin
OMAT1.3 — Match output for Timer 1, channel 3.
ISSEL1 — Slave Select for SSP. Selects the SSP interface as a slave.
IEINT3 — Exte rnal interrupt 3 input.
I/OP0.21 — General purpose digital input/output pin
OPWM5 — Pulse Width Modulator output 5.
IAD1.6 — A/D converter 1, input 6. This analog input is always connected to
its pin. Available in LPC2144/6/8 only.
ICAP1.3 — Capture input for Timer 1, channel 3.
I/OP0.22 — General purpose digital input/output pin.
IAD1.7 — A/D converter 1, input 7. This analog input is always connected to
its pin. Available in LPC2144/6/8 only.
ICAP0.0 — Capture input for Timer 0, channel 0.
OMAT0.0 — Match output for Timer 0, channel 0.
I/OP0.23 — General purpose digital input/output pin.
IV
I/OP0.25 — General purpose digital input/output pin
IAD0.4 — A/D converter 0, input 4. This analog input is always connected to
OAout — D/A converter output. Available in LPC2142/4/6/8 only.
P1.0 to P1.31I/OPort 1: Port 1 is a 32-bit bi-directional I/O port with individual direction
P1.16/
TRACEPKT0
P1.17/
TRACEPKT1
P1.18/
TRACEPKT2
P1.19/
TRACEPKT3
P1.20/
TRACESYNC
P1.21/
PIPESTAT0
13
14
15
16
12
8
4
48
44
[4]
[4]
[4]
[6]
[6]
[6]
[6]
[6]
[6]
[6]
I/OP0.28 — General purpose digital input/output pin
IAD0.1 — A/D converter 0, input 1. This analog input is always connected to
its pin.
ICAP0.2 — Capture input for Timer 0, channel 2.
OMAT0.2 — Match output for Timer 0, channel 2.
I/OP0.29 — General purpose digital input/output pin
IAD0.2 — A/D converter 0, input 2. This analog input is always connected to
its pin.
ICAP0.3 — Capture input for Timer 0, Channel 3.
OMAT0.3 — Match output for Timer 0, channel 3.
I/OP0.30 — General purpose digital input/output pin.
IAD0.3 — A/D converter 0, input 3. This analog input is always connected to
its pin.
IEINT3 — Exte rnal interrupt 3 input.
ICAP0.0 — Capture input for Timer 0, channel 0.
OP0.31 — General purpose output only digital pin (GPO).
OUP_LED — USB Good Link LED indicator. It is LOW when device is
configured (non-control endpoints enabled). It is HIGH when the device is not
configured or during global suspend.
OCONNECT — Signal used to switch an external 1.5 kΩ resistor under the
software control (active state for this signal is LOW). Used with the Soft
Connect USB feature.
Note: This pin MUST NOT be externally pulled LOW when RESET pin is
LOW or the JTAG port will be disabled.
controls for each bit. The operation of port 1 pins depends upon the pin
function selected via the pin connect block. Pins 0 through 15 of port
available.
I/OP1.16 — General purpose digital input/output pin
OTRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.
I/OP1.17 — General purpose digital input/output pin
OTRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.
I/OP1.18 — General purpose digital input/output pin
OTRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.
I/OP1.19 — General purpose digital input/output pin
OTRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.
I/OP1.20 — General purpose digital input/output pin
OTRACESYNC — Trace Synchronization. Standard I/O port with internal
pull-up.
Note: LOW on this pin while RESET is LOW enables pins P1.25:16 to
operate as Trace port after reset
I/OP1.21 — General purpose digital input/output pin
OPIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.
I/OP1.22 — General purpose digital input/output pin
OPIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.
I/OP1.23 — General purpose digital input/output pin
OPIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.
I/OP1.24 — General purpose digital input/output pin
OTRACECLK — Trace Clock. Standard I/O port with internal pull-up.
I/OP1.25 — General purpose digital input/output pin
IEXTIN0 — External Trigger Input. Standard I/O with internal pull-up.
I/OP1.26 — General purpose digital input/output pin
I/ORTCK — Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bi-directional pin with internal pull-up.
Note: LOW on this pin while RESET is LOW enables pins P1.31:26 to
operate as Debug port after reset
I/OP1.27 — General purpose digital input/output pin
OTDO — Test Data out for JTAG interface.
I/OP1.28 — General purpose digital input/output pin
ITDI — Test Data in for JTAG interface.
I/OP1.29 — General purpose digital input/output pin
ITCK — Test Clock for JTAG interface.
I/OP1.30 — General purpose digital input/output pin
ITMS — Test Mode Select for JTAG interface.
I/OP1.31 — General purpose digital input/output pin
ITRST — Test Reset for JTAG interface.
I/OUSB bidirectional D+ line.
I/OUSB bidirectional D- line.
IExternal reset input: A LOW on this pin resets the device, causing I/O ports
and peripherals to take on their default states, and processor execution to
begin at address 0. TTL with hysteresis, 5
IInp ut to the oscillator circuit and internal clock generator circuits.
OOutput from the oscillator amplifier.
IInp ut to the RTC oscillator circuit.
OOutput from the RTC oscillator circuit.
59IAnalog Ground: 0 V reference. This should nominally be the same voltage
as VSS, but should be isolated to minimize noise and error.
23, 43, 51I3.3 V Power Supply: This is the power supply voltage for the core and I/O
ports.
Philips Semiconductors
Volume 1Chapter 6: Pin Configuration
Table 58:Pin description …continued
SymbolPinTypeDescription
V
DDA
V
REF
V
BAT
7IAnalog 3.3 V Power Supply: This should be nominally the same voltage as
but should be isolated to minimize noise and error. This voltage is used to
V
DD
power the ADC(s).
63IA/D Converter Reference: This should be nominally the same voltage as
VDD but should be isolated to minimize noise and error. Level on this pin is
used as a reference for A/D convertor.
49IRTC Power Supply: 3.3 V on this pin supplies the power to the RTC.
[1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
[2] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If
configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[3] Open-drain 5 V tolerant digital I/O I2C-bus 400 kHz specification compatible pad. It requires external pull-up
to provide an output functionality.
[4] 5 V tolerant pad providing digital I/O (with TTL levels and h ysteresis and 10 ns slew rate control) and analog
input function. If configured for an input function, this pad utilizes built-in glitch filter that blocks pulses
shorter than 3
[5] 5 V tolerant pad providing digital I/O (with TTL levels and h ysteresis and 10 ns slew rate control) and analog
output function. When configured as the DAC output, digital section of the pad is disabled.
[6] 5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis
and 10
[7] Pad is designed in accordance with the Universal Serial Bus (USB) specification, revision 2.0 (Full-speed
and Low-speed mode only).
[8] 5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
[9] Pad provides special analog functionality.
ns. When configured as an ADC input, digital section of the pad is disabled.
ns slew rate control. The pull-up resistor’s value typically ranges from 60 kΩ to 300 kΩ.
The purpose of the Pin Connect Block is to configure the microcontroller pins to the
desired functions.
7.3 Description
The pin connect block allows selected pins of the microcontroller to have mor e than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on chip peripherals.
UM10139
Chapter 7: Pin Connect Block
Rev. 01 — 15 August 2005User manual
• Allows individual pin configuration.
Periphera ls should be connected to the appr opriate pins prior to being activ ated, and prior
to any related interrupt(s) being enab led. Acti vity of an y enab led peripheral f unction that is
not mapped to a related pin should be considered undefined.
Selection of a single function on a port pin completely excludes all other functions
otherwise available on the same pin.
The only partial exception from the abo v e rule of exclusion is the case of inputs to the A/D
converter. Regardless of the function that is selected for the port pin that also hosts the
A/D input, this A/D input can be read at any time and v ariations of the v oltage le v el on t his
pin will be reflected in the A/D readings. Howev er, valid analog reading(s) can be obtained
if and only if the function of an analog input is selected. Only in this case proper interface
circuit is active in between the physical pin and the A/D module. In all other cases, a part
of digital logic necessary for the digital function to be performed will be active, and will
disrupt proper behavior of the A/D.
7.4 Register description
The Pin Control Module contains 2 registers as shown in Table 59 below.
Table 59:Pin connect block register map
NameDescriptionAccessReset value
PINSEL0Pin function select
PINSEL1Pin function select
PINSEL2Pin function select
register 0.
register 1.
register 2.
[1]
Read/Write0x0000 00000xE002 C000
Read/Write0x0000 00000xE002 C004
Read/WriteSee Table 620xE002 C014
Address
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Table 60:Pin function Select register 0 (PINSEL0 - address 0xE002 C000) bit description
BitSymbolValueFunctionReset value
19:18P0.900GPIO Port 0.90
21:20P0.1000GPIO Port 0.100
23:22P0.1100GPIO Port 0.110
25:24P0.1200GPIO Port 0.120
27:26P0.1300GPIO Port 0.130
29:28P0.1400GPIO Port 0.140
31:30P0.1500GPIO Port 0.150
01RxD (UART1)
10PWM6
11EINT3
01Reserved
10Capture 1.0 (Timer 1)
11Reserved
01Reserved
10Capture 1.1 (Timer 1)
11SCL1 (I2C1)
01Reserved
10Match 1.0 (Timer 1)
11Reserved
01Reserved
10Match 1.1 (Timer 1)
11Reserved
01Reserved
10EINT1
11SDA1 (I2C1)
01Reserved
10EINT2
11Reserved
[1][2]
or RTS (UART1)
[1][2]
or AD1.2
[1][2]
or CTS (UART1)
[1][2]
or DSR (UART1)
[1][2]
or AD1.3
[1][2]
or DTR (UART1)
[1][2]
or AD1.4
[1][2]
or DCD (UART1)
[1][2]
or RI (UART1)
[1][2]
or AD1.5
UM10139
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[3]
[1] Available on LPC2141.
[2] Available on LPC2142.
[3] Available on LPC2144/6/8.
7.4.2 Pin function Select register 1 (PINSEL1 - 0xE002 C004)
The PINSEL1 register controls the functions of the pins as per the settings listed in
following tables. The direction control bit in the IO0DIR register is effective only when the
GPIO function is selected for a pin. For other functions direction is controlled
automatically.
[1] Available on LPC2141.
[2] Available on LPC2142.
[3] Available on LPC2144/6/8.
7.4.3 Pin function Select register 2 (PINSEL2 - 0xE002 C014)
The PINSEL2 register controls the functions of the pins as per the settings listed in
Table 62. The direction control bit in the IO1DIR register is effective only when the GPIO
function is selected for a pin. For other functions direction is controlled automatically.
Warning: use read-modify-write operation when accessing PINSEL2 register. Accidental
write of 0 to bit 2 and/or bit 3 results in loss of debug and/or trace functionality! Changing
of either bit 4 or bit 5 from 1 to 0 may cause an incorrect code execution!
Table 62:Pin function Select register 2 (PINSEL2 - 0xE002 C014) bit description
BitSymbolValue FunctionReset value
1:0--Reserved, user software should not write ones
2GPIO/DEBUG 0Pins P1.36-26 are used as GPIO pins.P1.26/RTCK
3GPIO/TRACE 0Pins P1.25-16 are used as GPIO pins.P1.20/
31:4 --Reserved, user software should not write ones
7.4.4 Pin function select register values
The PINSEL registers control the functions of device pins as shown below. Pairs of bits in
these registers correspond to specific device pins.
UM10139
NA
to reserved bits. The value read from a reserved
bit is not defined.
1Pins P1.36-26 are used as a Debug port.
TRACESYNC
1Pins P1.25-16 are used as a Trace port.
NA
to reserved bits. The value read from a reserved
bit is not defined.
Table 63:Pin function select register bits
PINSEL0 and PINSEL1 Values FunctionValue after Reset
00Primary (default) function, typically GPIO
port
01First alternate function
10Second alternate function
11Reserved
The direction control bit in the IO0DIR/IO1DIR register is e ffective only when the GPIO
function is selected for a pin. For other functions, direction is controlled automatically.
Each derivative typically has a different pinout and therefore a different set of functions
possible f or each pin. Details f or a specific deriv ativ e may be found in the approp riate data
sheet.
Chapter 8: General Purpose Input/Output ports (GPIO)
Rev. 01 — 15 August 2005User manual
• Every physical GPIO port is accessible via either the group of registers providing an
enhanced features and accelerated port access or the legacy group of registers
• Accelerated GPIO functions:
– GPIO registers are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged
– All registers are byte and half-word addressable
– Entire port value can be written in one instruction
• Bit-level set and clea r regist ers allo w a single instruction set or clear of any number of
bits in one port
• Direction control of individual bits
• All I/O default to inputs after reset
• Backward compatibility with other earlier devices is maintained with legacy registers
appearing at the original addresses on the VPB bus
8.2 Applications
• General purpose I/O
• Driving LEDs, or other indicators
• Controlling off-chip devices
• Sensing digital inputs
8.3 Pin description
Table 64:GPIO pin description
PinTypeDescription
P0.0-P.31
P1.16-P1.31
Input/
Output
General purpose input/output. The number of GPIOs actually available depends on the
use of alternate functions.
8.4 Register description
LPC2141/2/4/6/8 has two 32-b it Gener al Pu rpose I/O ports. Total of 30 input/output and a
single output only pin out of 32 pins are available on PORT0. PORT1 has up to 16 pins
available for GPIO functions. PORT0 and PORT1 are controlled via two groups of 4
registers as shown in
Table 65 and Table 66.
Legacy registers shown in Table 65 allow backward compatibility with earlier family
devices, using existing code. The functions and relative timing of older GPIO
implementations is preserved.
The registers in Table 66 represent the enhanced GPIO features available on the
LPC2141/2/4/6/8. All of these registers are located direct ly on the local b us of the CPU for
the fastest possible read and write timing. An additional feature has been added that
provides byte addressability of all GPIO registers. A mask register allows treating groups
of bits in a single GPIO port separately from other bits on the same port.
User must select whether a GPIO will be accessed via registers that provide enhanced
features or a legacy set of registers (see
register (SCS - 0xE01F C1A0)” on page 26). While both of a port’s fast and legacy GPIO
registers are controlling the same physical pins, these two port control branches are
mutually exclusive and operate independently. For example, changing a pin’s output via a
fast register will not be observable via the corresponding legacy register.
The following text will refer to the legacy GPIO as "the slow" GPIO, while GPIO equipped
with the enhanced features will be referred as "the fast" GPIO.
R/WNA0xE002 8000
state of the GPIO configured port pins can
always be read from this register, regardless
of pin direction.
R/W0x0000 0000 0xE002 8004
controls the state of output pins in
conjunction with the IOCLR register. Writing
ones produces highs at the corresponding
port pins. Writing zeroes has no effect.
register individually controls the direction of
each port pin.
register controls the state of output pins.
Writing ones produces lows at the
corresponding port pins and clears the
corresponding bits in the IOSET register.
Writing zeroes has no effect.
R/W0x0000 0000 0xE002 8008
WO0x0000 0000 0xE002 800C
UM10139
Section 3.6.1 “System Control and Status flags
value
[1]
PORT0
Address & Name
IO0PIN
IO0SET
IO0DIR
IO0CLR
PORT1
Address & Name
0xE002 8010
IO1PIN
0xE002 8014
IO1SET
0xE002 8018
IO1DIR
0xE002 801C
IO1CLR
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
R/W0x0000 0000 0x3FFF C000
This register individually controls the
direction of each port pin.
R/W0x0000 0000 0x3FFF C010
clears, and reads to port (done via writes to
FIOPIN, FIOSET, and FIOCLR, and reads of
FIOPIN) alter or return only the bits enabled
by zeros in this register.
R/W0x0000 0000 0x3FFF C014
The current state of digital port pins can be
read from this register, regardless of pin
direction or alternate function selection (as
long as pins is not configured as an input to
ADC). The value read is masked by ANDing
with FIOMASK. Writing to this register
places corresponding values in all bits
enabled by ones in FIOMASK.
R/W0x0000 0000 0x3FFF C018
FIOMASK. This register controls the state of
output pins. Writing 1s produces highs at the
corresponding port pins. Writing 0s has no
effect. Reading this regi st er re tu rns the
current contents of the port output register.
Only bits enabled by ones in FIOMASK can
be altered.
FIOMASK0. This register controls the state
of output pins. Writing 1s produces lows at
the corresponding port pins. Writing 0s has
no effect. Only bits enabled by ones in
FIOMASK0 can be altered.
WO0x0000 0000 0x3FFF C01C
[1]
PORT0
Address & Name
FIO0DIR
FIO0MASK
FIO0PIN
FIO0SET
FIO0CLR
UM10139
PORT1
Address & Name
0x3FFF C020
FIO1DIR
0x3FFF C030
FIO1MASK
0x3FFF C034
FIO1PIN
0x3FFF C038
FIO1SET
0x3FFF C03C
FIO1CLR
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
8.4.1 GPIO port Direction register (IODIR, Port 0: IO0DIR - 0xE002 8008 and
Port 1: IO1DIR - 0xE002 8018; FIODIR, Por t 0: FIO0DIR - 0x3FFF C000
and Port 1:FIO1DIR - 0x3FFF C020)
This word accessible register is used to c ontrol the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
Legacy registers are the IO0DIR and IO1DIR, while the enhanced GPIO functions are
supported via the FIO0DIR and FIO1DIR registers.
Table 67:GPIO port 0 Direction register (IO0DIR - address 0xE002 8008) bit description
Slow GPIO Direction control bits. Bit 0 controls P0.0 ... bit 30 controls P0.30.
Controlled pin is input.
0x0000 0000
Philips Semiconductors
UM10139
Volume 1Chapter 8: GPIO
T able 68:GPIO port 1 Direction register (IO1DIR - address 0xE002 8 018) bit description
BitSymbolValue DescriptionReset value
31:0P1xDIR
Table 69:Fast GPIO port 0 Direction register (FIO0DIR - address 0x3FFF C000) bit description
BitSymbolValue DescriptionReset value
31:0FP0xDIR
Table 70:Fast GPIO port 1 Direction register (FIO1DIR - address 0x3FFF C020) bit description
BitSymbolValue DescriptionReset value
31:0FP1xDIR
Slow GPIO Direction control bits. Bit 0 in IO1DIR controls P1.0 ... Bit 30 in
IO1DIR controls P1.30.
0
Controlled pin is input.
1Co ntrolled pin is output.
Fast GPIO Direction control bits. Bit 0 in FIO0DIR controls P0.0 ... Bit 30 in
FIO0DIR controls P0.30.
0
Controlled pin is input.
1Controlled pin is output.
Fast GPIO Direction control bits. Bit 0 in FIO1DIR controls P1.0 ... Bit 30 in
FIO1DIR controls P1.30.
0
Controlled pin is input.
1Controlled pin is output.
0x0000 0000
0x0000 0000
0x0000 0000
Aside from the 32-bit long and word only accessib le FIODIR regi ster , ev ery f ast GPIO port
can also be controlled via several byte and half-word accessible registers listed in
Table 71 and Table 72, too. Next to providing the same functions as the FIODIR register,
these additional registers allow easier and faster access to the physical port pins.
Table 71:Fast GPIO port 0 Direction control byte and half-word accessible register description
Register
name
FIO0DIR08 (byte)0x3FFF C000 Fast GPIO Port 0 Direction control register 0. Bit 0 in FIO0DIR0
FIO0DIR18 (byte)0x3FFF C001 Fast GPIO Port 0 Direction control register 1. Bit 0 in FIO0DIR1
FIO0DIR28 (byte)0x3FFF C002 Fast GPIO Port 0 Direction control register 2. Bit 0 in FIO0DIR2
FIO0DIR38 (byte)0x3FFF C003 Fast GPIO Port 0 Direction control register 3. Bit 0 in FIO0DIR3
FIO0DIRL16
FIO0DIRU16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
register corresponds to P0.0 ... bit 7 to P0.7.
register corresponds to P0.8 ... bit 7 to P0.15.
register corresponds to P0.16 ... bit 7 to P0.23.
register corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C000 Fast GPIO Port 0 Direction control Lower half-word register. Bit 0 in
FIO0DIRL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C002 Fast GPIO Port 0 Direction control Upper half-word register. Bit 0 in
FIO0DIRU register corresponds to P0.16 ... bit 15 to P0.31.
Table 72:Fast GPIO port 1 Direction control byte and half-word accessible register description
Register
name
FIO1DIR08 (byte)0x3FFF C020 Fast GPIO Port 1 Direction control register 0. Bit 0 in FIO1DIR0
FIO1DIR18 (byte)0x3FFF C021 Fast GPIO Port 1 Direction control register 1. Bit 0 in FIO1DIR1
FIO1DIR28 (byte)0x3FFF C022 Fast GPIO Port 1 Direction control register 2. Bit 0 in FIO1DIR2
FIO1DIR38 (byte)0x3FFF C023 Fast GPIO Port 1 Direction control register 3. Bit 0 in FIO1DIR3
FIO1DIRL16
FIO1DIRU16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
register corresponds to P1.0 ... bit 7 to P1.7.
register corresponds to P1.8 ... bit 7 to P1.15.
register corresponds to P1.16 ... bit 7 to P1.23.
register corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C020 Fast GPIO Port 1 Direction control Lower half-word register. Bit 0 in
FIO1DIRL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C022 Fast GPIO Port 1 Direction control Upper half-word register. Bit 0 in
FIO1DIRU register corresponds to P1.16 ... bit 15 to P1.31.
UM10139
8.4.2 Fast GPIO port Mask register (FIOMASK, Port 0: FIO0MASK 0x3FFF C010 and Port 1:FIO1MASK - 0x3FFF C030)
value
0x00
0x00
0x00
0x00
0x0000
0x0000
This register is av aila ble in the enhanced group of registers only. It is used to select port’s
pins that will and will not be affected by a write accesses to the FIOPIN, FIOSET or
FIOSLR register. Mask register also filters out port’s content when the FIOPIN register is
read.
A zero in this register’s bit enables an access to the corresponding physica l pin via a read
or write access. If a bit in this register is one, corresponding pin will not be changed with
write access and if read, will not be reflected in the updated FIOPIN register. F or software
examples, see
Table 73:Fast GPIO port 0 Mask register (FIO0MASK - address 0x3FFF C010) bit description
BitSymbolValue DescriptionReset value
31:0FP0xMASK
0
1Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN
Table 74:Fast GPIO port 1 Mask register (FIO1MASK - address 0x3FFF C030) bit description
BitSymbolValue DescriptionReset value
31:0FP1xMASK
0
1Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN
Fast GPIO physical pin access control.
Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers.
Current state of the pin will be observable in the FIOPIN register.
registers. When the FIOPIN register is read, this bit will not be updated with
the state of the physical pin.
Fast GPIO physical pin access control.
Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers.
Current state of the pin will be observable in the FIOPIN register.
registers. When the FIOPIN register is read, this bit will not be updated with
the state of the physical pin.
Aside from the 32-bit long and word only accessible FIOMASK register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 75 and Table 76, too. Next to providing the same functions as the FIOMASK
register, t hese add it ional re gist ers a llow easier and faster access to the ph ysical p ort pins.
Table 75:Fast GPIO port 0 Mask byte and half-word accessible register description
Register
name
FIO0MASK0 8 (byte)0x3FFF C010 Fast GPIO Port 0 Mask register 0. Bit 0 in FIO0MASK0 register
FIO0MASK1 8 (byte)0x3FFF C011 Fast GPIO Port 0 Mask register 1. Bit 0 in FIO0MASK1 register
FIO0MASK2 8 (byte)0x3FFF C012 Fast GPIO Port 0 Mask register 2. Bit 0 in FIO0MASK2 register
FIO0MASK3 8 (byte)0x3FFF C013 Fast GPIO Port 0 Mask register 3. Bit 0 in FIO0MASK3 register
FIO0MASKL 16
FIO0MASKU 16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
corresponds to P0.0 ... bit 7 to P0.7.
corresponds to P0.8 ... bit 7 to P0.15.
corresponds to P0.16 ... bit 7 to P0.23.
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C001Fast GPIO Port 0 Mask Lower half-word register. Bit 0 in
FIO0MASKL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C012Fast GPIO Port 0 Mask Upper half-word register. Bit 0 in
FIO0MASKU register corresponds to P0.16 ... bit 15 to P0.31.
value
0x00
0x00
0x00
0x00
0x0000
0x0000
Table 76:Fast GPIO port 1 Mask byte and half-word accessible register description
Register
name
FIO1MASK0 8 (byte)0x3FFF C010 Fast GPIO Port 1 Mask register 0. Bit 0 in FIO1MASK0 register
FIO1MASK1 8 (byte)0x3FFF C011 Fast GPIO Port 1 Mask register 1. Bit 0 in FIO1MASK1 register
FIO1MASK2 8 (byte)0x3FFF C012 Fast GPIO Port 1 Mask register 2. Bit 0 in FIO1MASK2 register
FIO1MASK3 8 (byte)0x3FFF C013 Fast GPIO Port 1 Mask register 3. Bit 0 in FIO1MASK3 register
FIO1MASKL 16
FIO1MASKU 16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
corresponds to P1.0 ... bit 7 to P1.7.
corresponds to P1.8 ... bit 7 to P1.15.
corresponds to P1.16 ... bit 7 to P1.23.
corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C001Fast GPIO Port 1 Mask Lower half-word register. Bit 0 in
FIO1MASKL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C012Fast GPIO Port 1 Mask Upper half-word register. Bit 0 in
FIO1MASKU register corresponds to P1.16 ... bit 15 to P1.31.
8.4.3 GPIO port Pin value register (IOPIN, Port 0: IO0PIN - 0xE002 8000 and
Port 1: IO1PIN - 0xE002 8010; FIOPIN, Port 0: FIO0PIN - 0x3FFF C014
and Port 1: FIO1PIN - 0x3FFF C034)
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or out put, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to be
read from the IOPIN register.
If a pin has an analog function as one of its optio ns, the pin state cannot be read if the
analog configuration is selected. Selecting the pin as an A/D input disconn ects the digital
features of the pin. In that case, the pin value read in the IOPIN register is not valid.
Writing to the IOPIN register stores the value in the port output register, bypassing the
need to use both the IOSET and IOCLR registers to obtain the entire written value. This
feature should be used carefully in an application since it affects the entire port.
Legacy registers are the IO0PIN and IO1PIN, while the enhanced GPIOs are supported
via the FIO0PIN and FIO1PIN registers. Access to a port pins via the FIOPIN register is
conditioned by the corresponding FIOMASK register (see
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK 0x3FFF C030)”).
Only pins masked with zeros in the Mask register (see Section 8.4.2 “Fast GPIO port
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK 0x3FFF C030)”) will be correlated to the current content of the Fast GPIO port pin value
register.
Table 77:GPIO port 0 Pin value register (IO0PIN - address 0xE002 8000) bit description
BitSymbolDescriptionReset value
31:0P0xVALSlow GPIO pin value bits. Bit 0 in IO0PIN corresponds to P0.0 ... Bit 31 in IO0PIN
corresponds to P0.31.
Section 8.4.2 “Fast GPIO port
UM10139
NA
Table 78:GPIO port 1 Pin value register (IO1PIN - address 0xE002 8010) bit description
BitSymbolDescriptionReset value
31:0P1xVALSlow GPIO pin value bits. Bit 0 in IO1PIN corresponds to P1.0 ... Bit 31 in IO1PIN
corresponds to P1.31.
Table 79:Fast GPIO port 0 Pin value register (FIO0PIN - address 0x3FFF C014) bit description
BitSymbolDescriptionReset value
31:0FP0xVALFast GPIO pin value bits. Bit 0 in FIO0PIN corresponds to P0.0 ... Bit 31 in FIO0PIN
corresponds to P0.31.
Table 80:Fast GPIO port 1 Pin value register (FIO1PIN - address 0x3FFF C034) bit description
BitSymbolDescriptionReset value
31:0FP1xVALFast GPIO pin value bits. Bit 0 in FIO1PIN corresponds to P1.0 ... Bit 31 in FIO1PIN
corresponds to P1.31.
Aside from the 32-bit long and word on ly accessib le FIOPIN reg ister, every fast GPIO po rt
can also be controlled via several byte and half-word accessible registers listed in
Table 81 and Table 82, too. Next to providing the same functions as the FIOPIN register,
these additional registers allow easier and faster access to the physical port pins.
Table 81:Fast GPIO port 0 Pin value byte and half-word accessible register description
Register
name
FIO0PIN08 (byte)0x3FFF C014Fast GPIO Port 0 Pin value register 0. Bit 0 in FIO0PIN0 register
FIO0PIN18 (byte)0x3FFF C015Fast GPIO Port 0 Pin value register 1. Bit 0 in FIO0PIN1 register
FIO0PIN28 (byte)0x3FFF C016Fast GPIO Port 0 Pin value register 2. Bit 0 in FIO0PIN2 register
FIO0PIN38 (byte)0x3FFF C017Fast GPIO Port 0 Pin value register 3. Bit 0 in FIO0PIN3 register
FIO0PINL16
FIO0PINU16
Table 82:Fast GPIO port 1 Pin value byte and half-word accessible register description
Register
name
FIO1PIN08 (byte)0x3FFF C034Fast GPIO Port 1 Pin value register 0. Bit 0 in FIO1PIN0 register
FIO1PIN18 (byte)0x3FFF C035Fast GPIO Port 1 Pin value register 1. Bit 0 in FIO1PIN1 register
FIO1PIN28 (byte)0x3FFF C036Fast GPIO Port 1 Pin value register 2. Bit 0 in FIO1PIN2 register
FIO1PIN38 (byte)0x3FFF C037Fast GPIO Port 1 Pin value register 3. Bit 0 in FIO1PIN3 register
FIO1PINL16
FIO1PINU16
Register
length (bits)
& access
(half-word)
(half-word)
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
corresponds to P0.0 ... bit 7 to P0.7.
corresponds to P0.8 ... bit 7 to P0.15.
corresponds to P0.16 ... bit 7 to P0.23.
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C014 Fast GPIO Port 0 Pin value Lower half-word register. Bit 0 in
FIO0PINL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C016 Fast GPIO Port 0 Pin value Upper half-word register. Bit 0 in
FIO0PINU register corresponds to P0.16 ... bit 15 to P0.31.
AddressDescriptionReset
corresponds to P1.0 ... bit 7 to P1.7.
corresponds to P1.8 ... bit 7 to P1.15.
corresponds to P1.16 ... bit 7 to P1.23.
corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C034 Fast GPIO Port 1 Pin value Lower half-word register. Bit 0 in
FIO1PINL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C036 Fast GPIO Port 1 Pin value Upper half-word register. Bit 0 in
FIO1PINU register corresponds to P1.16 ... bit 15 to P1.31.
value
0x00
0x00
0x00
0x00
0x0000
0x0000
value
0x00
0x00
0x00
0x00
0x0000
0x0000
8.4.4 GPIO port output Set register (IOSET, Port 0: IO0SET - 0xE002 8004
and Port 1: IO1SET - 0xE002 8014; FIOSET, Port 0: FIO0SET 0x3FFF C018 and Port 1: FIO1SET - 0x3FFF C038)
This register is used to produce a HIG H lev el output a t the port pins configured as GPIO in
an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins.
Writing 0 has no effect. If an y pin is configured as an input or a second ary function, writing
1 to the corresponding bit in the IOSET has no effect.
Reading the IOSET register returns the value of this register, as determined by previous
writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the
effect of any outside world influence on the I/O pins.
Legacy registers are the IO0SET and IO1SET, while the enhanced GPIOs are supported
via the FIO0SET and FIO1SET registers . Access t o a port pins via the FIOSET register is
conditioned by the corresponding FIOMASK register (see
Section 8.4.2 “Fast GPIO port
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK 0x3FFF C030)”).
Table 83:GPIO port 0 output Set register (IO0SET - address 0xE002 8004 bit description
BitSymbolDescriptionReset value
31:0P0xSETSlow GPIO output value Set bits. Bit 0 in IO0SET corresponds to P0.0 ... Bit 31
in IO0SET corresponds to P0.31.
Table 84:GPIO port 1 output Set register (IO1SET - address 0xE002 8014) bit description
BitSymbolDescriptionReset value
31:0P1xSETSlow GPIO output value Set bits. Bit 0 in IO1SET corresponds to P1.0 ... Bit 31
in IO1SET corresponds to P1.31.
Table 85:Fast GPIO port 0 output Set register (FIO0SET - address 0x3FFF C018) bit description
BitSymbolDescriptionReset value
31:0FP0xSETFast GPIO output value Set bits. Bit 0 in FIO0SET corresponds to P0.0 ... Bit 31
in FIO0SET corresponds to P0.31.
0x0000 0000
0x0000 0000
0x0000 0000
Table 86:Fast GPIO port 1 output Set register (FIO1SET - address 0x3FFF C038) bit description
BitSymbolDescriptionReset value
31:0FP1xSETFa st GPIO output v alue Set bits. Bit 0 F in IO1SET corresponds to P1.0 ... Bit 31
in FIO1SET corresponds to P1.31.
0x0000 0000
Aside from the 32-bit long and word only accessible FIOSET register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 87 and Table 88, too. Next to providing the same functions as the FIOSET register,
these additional registers allow easier and faster access to the physical port pins.
Table 87:Fast GPIO port 0 output Set byte and half-word accessible register description
Register
name
FIO0SET08 (byte)0x3FFF C018 Fast GPIO Port 0 output Set register 0. Bit 0 in FIO0SET0 register
FIO0SET18 (byte)0x3FFF C019 Fast GPIO Port 0 output Set register 1. Bit 0 in FIO0SET1 register
FIO0SET28 (byte)0x3FFF C01A Fast GPIO Port 0 output Set register 2. Bit 0 in FIO0SET2 register
FIO0SET38 (byte)0x3FFF C01B Fast GPIO Port 0 output Set register 3. Bit 0 in FIO0SET3 register
FIO0SETL16
FIO0SETU16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
value
0x00
corresponds to P0.0 ... bit 7 to P0.7.
0x00
corresponds to P0.8 ... bit 7 to P0.15.
0x00
corresponds to P0.16 ... bit 7 to P0.23.
0x00
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C018 Fast GPIO Port 0 output Set Lower half-word register. Bit 0 in
FIO0SETL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C01A Fast GPIO Port 0 output Set Upper half-word register. Bit 0 in
FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.
Table 88:Fast GPIO port 1 output Set byte and half-word accessible register description
Register
name
FIO1SET08 (byte)0x3FFF C038 Fast GPIO Port 1 output Set register 0. Bit 0 in FIO1SET0 register
FIO1SET18 (byte)0x3FFF C039 Fast GPIO Port 1 output Set register 1. Bit 0 in FIO1SET1 register
FIO1SET28 (byte)0x3FFF C03A Fast GPIO Port 1 output Set register 2. Bit 0 in FIO1SET2 register
FIO1SET38 (byte)0x3FFF C03B Fast GPIO Port 1 output Set register 3. Bit 0 in FIO1SET3 register
FIO1SETL16
FIO1SETU16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
corresponds to P1.0 ... bit 7 to P1.7.
corresponds to P1.8 ... bit 7 to P1.15.
corresponds to P1.16 ... bit 7 to P1.23.
corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C038 Fast GPIO Port 1 output Set Lower half-word register. Bit 0 in
FIO1SETL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C03A Fast GPIO Port 1 output Set Upper half-word register. Bit 0 in
FIO1SETU register corresponds to P1.16 ... bit 15 to P1.31.
UM10139
8.4.5 GPIO port output Clear register (IOCLR, Port 0: IO0CLR 0xE002 800C and Port 1: IO1CLR - 0xE002 801C; FIOCLR, Port 0:
FIO0CLR - 0x3FFF C01C and Port 1: FIO1CLR - 0x3FFF C03C)
value
0x00
0x00
0x00
0x00
0x0000
0x0000
This register is used to produce a LOW level output at port pins configured as GPIO in an
OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears
the corresponding bit in the IOSET register . Writing 0 has no eff ect. If any pin is conf igured
as an input or a secondary function, writing to IOCLR has no effect.
Legacy registers are the IO0CLR and IO1CLR, while the enhanced GPIOs are suppo rted
via the FIO0CLR and FIO1CLR registers. Acce ss to a port pins via the FIOCLR register is
conditioned by the corresponding FIOMASK register (see
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK 0x3FFF C030)”).
Table 89:GPIO port 0 output Clear register 0 (IO0CLR - address 0xE002 800C) bit description
BitSymbolDescriptionReset value
31:0P0xCLRSlow GPIO output value Clear bits. Bit 0 in IO0CLR corresponds to P0.0 ... Bit
31 in IO0CLR corresponds to P0.31.
Table 90:GPIO port 1 output Clear register 1 (IO1CLR - address 0xE002 801C) bit description
BitSymbolDescriptionReset value
31:0P1xCLRSlow GPIO output value Clear bits. Bit 0 in IO1CLR corresponds to P1.0 ... Bit
31 in IO1CLR corresponds to P1.31.
Table 91:Fast GPIO port 0 output Clear register 0 (FIO0CLR - address 0x3FFF C01C) bit description
BitSymbolDescriptionReset value
31:0FP0xCLRFast GPI O output v alue C lear bits . Bit 0 in FIO0CLR corresponds to P0.0 ... Bit
Table 92:Fast GPIO port 1 output Clear register 1 (FIO1CLR - address 0x3FFF C03C) bit description
BitSymbolDescriptionReset value
31:0FP1xCLRFast GPIO output value Clear bits . Bit 0 in FIO1CLR corresponds to P1.0 ... Bit
31 in FIO1CLR corresponds to P1.31.
0x0000 0000
Aside from the 32-bit long and word only accessible FIOCLR register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 93 and Table 94, too. Next to providing the same functions as the FIOCLR register,
these additional registers allow easier and faster access to the physical port pins.
Table 93:Fast GPIO port 0 output Clear byte and half-wor d accessible register description
Register
name
FIO0CLR08 (byte)0x3FFF C01C Fast GPIO Port 0 output Clear register 0. Bit 0 in FIO0CLR0 register
FIO0CLR18 (byte)0x3FFF C01D Fast GPIO Port 0 output Clear register 1. Bit 0 in FIO0CLR1 register
FIO0CLR28 (byte)0x3FFF C01E Fast GPIO Port 0 output Clear register 2. Bit 0 in FIO0CLR2 register
FIO0CLR38 (byte)0x3FFF C01F Fast GPIO Port 0 output Clear register 3. Bit 0 in FIO0CLR3 register
FIO0CLRL16
FIO0CLRU16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
value
0x00
corresponds to P0.0 ... bit 7 to P0.7.
0x00
corresponds to P0.8 ... bit 7 to P0.15.
0x00
corresponds to P0.16 ... bit 7 to P0.23.
0x00
corresponds to P0.24 ... bit 7 to P0.31.
0x3FFF C01C Fast GPIO Port 0 output Clear Lower half-word register. Bit 0 in
FIO0CLRL register corresponds to P0.0 ... bit 15 to P0.15.
0x3FFF C01E Fast GPIO Port 0 output Clear Upper half-word register. Bit 0 in
FIO0SETU register corresponds to P0.16 ... bit 15 to P0.31.
0x0000
0x0000
Table 94:Fast GPIO port 1 output Clear byte and half-wor d accessible register description
Register
name
FIO1CLR08 (byte)0x3FFF C03C Fast GPIO Port 1 output Clear register 0. Bit 0 in FIO1CLR0 register
FIO1CLR18 (byte)0x3FFF C03D Fast GPIO Port 1 output Clear register 1. Bit 0 in FIO1CLR1 register
FIO1CLR28 (byte)0x3FFF C03E Fast GPIO Port 1 output Clear register 2. Bit 0 in FIO1CLR2 register
FIO1CLR38 (byte)0x3FFF C03F Fast GPIO Port 1 output Clear register 3. Bit 0 in FIO1CLR3 register
FIO1CLRL16
FIO1CLRU16
Register
length (bits)
& access
(half-word)
(half-word)
AddressDescriptionReset
corresponds to P1.0 ... bit 7 to P1.7.
corresponds to P1.8 ... bit 7 to P1.15.
corresponds to P1.16 ... bit 7 to P1.23.
corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C03C Fast GPIO Port 1 output Clear Lower half-word register. Bit 0 in
FIO1CLRL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C03E Fast GPIO Port 1 output Clear Upper half-word register. Bit 0 in
FIO1CLRU register corresponds to P1.16 ... bit 15 to P1.31.
8.5.1 Example 1: sequential accesses to IOSET and IOCLR affecting the
same GPIO pin/bit
State of the output configured GPIO pin is determined by writes into the pin’s port IOSET
and IOCLR registers. Last of these accesses to the IOSET/IOCLR register will determine
the final output of a pin.
pin P0.7 is configured as an output (write to IO0DIR reg ister). After this , P0. 7 output is set
to low (first write to IO0CLR register). Short high pulse follows on P0.7 (write access to
IO0SET), and the final write to IO0CLR register sets pin P0.7 back to low level.
UM10139
8.5.2 Example 2: an immediate output of 0s and 1s on a GPIO port
Write access to port’s IOSET followed by write to the IOCLR register results with pins
outputting 0s being slightly later then pins outputting 1s. There are systems that can
tolerate this delay of a valid output, but for some applications simultaneous output of a
binary content (mixed 0s and 1s) within a group of pins on a single GPIO port is required.
This can be accomplished by writing to the port’s IOPIN register.
Following code will preserve existing output on POR T0 pins P0.[31:16] and P0.[7:0] and at
the same time set P0.[15:8] to 0xA5, regardless of the previous value of pins P0.[15:8]:
IO0PIN = (IO0PIN && 0xFFFF00FF) || 0x0000A500
The same outcome can be obtained using the fast port access.
Solution 1: using 32-bit (word) accessible fast GPIO registers
FIO0MASK = 0xFFFF00FF;
FIO0PIN = 0x0000A500;
Solution 2: using 16-bit (half-word) accessible fast GPIO registers
FIO0MASKL = 0x00FF;
FIO0PINL = 0xA500;
Solution 3: using 8-bit (byte) accessible fast GPIO registers
Write to the IOSET/IOCLR register allows easy change of the port’ s selected output p in(s)
to high/low level at a time. Only pin/bit(s) in the IOSET/IOCLR written with 1 will be set to
high/low level, while those written as 0 will remain unaffected. However, by just writing to
either IOSET or IOCLR register it is not possible to instant aneously output arbitr ary binary
data containing mixture of 0s and 1s on a GPIO port.
Write to the IOPIN register enables instantaneous output of a desired content on the
parallel GPIO. Binary data written into the IOPIN register will affect all output configured
pins of that parallel port: 0s in the IOPIN will produce low level pin outputs and 1s in IOPIN
will produce high level pin outputs. In order to change output of only a g roup of port’s pins ,
application must logically AND readout from the IOPIN with mask containing 0s in bits
corresponding to pins that will be changed, and 1s for all others. Finally, this result has to
be logically ORred with the desired content and stored back into the IOPIN register.
Example 2 from above illustrates output of 0xA5 on PORT0 pins 15 to 8 while preserving
all other PORT0 output pins as they were before.
8.5.4 Output signal frequency considerations when using the legacy and
enhanced GPIO registers
UM10139
The enhanced features of the fast GPIO ports available on this microcontroller make
GPIO pins more responsive to the code that has task of controlling them. In particular,
software access to a GPIO pin is 3.5 times faster via the fast GPIO registers than it is
when the legacy set of registers is used. As a result of the access speed increase, the
maximum output frequency of the digital pin is increased 3.5 times, too. This tremendous
increase of the output frequency is not always that visible when a plain C code is used,
and a portion of an application handling the fast port output might hav e to be written in an
assembly code and executed in the ARM mode.
Here is a code where the pin control section is written in assembly language for ARM. It
illustrates the difference between the fast and slow GPIO port output capabilities. Once
this code is compiled in the ARM mode, its execution from the on-chip Flash will yield the
best results when the MAM module is configured as described in
notes” on page 49. Execution from the on-chip SRAM is independent from the MAM
setup.
ldrr0,=0xe01fc1a0/*register address--enable fast port*/
movr1,#0x1
strr1,[r0] /*enable fast port0*/
ldrr1,=0xffffffff
ldrr0,=0x3fffc000 /*direction of fast port0*/
strr1,[r0]
ldrr0,=0xe0028018/*direction of slow port 1*/
strr1,[r0]
ldrr0,=0x3fffc018/*FIO0SET -- fast port0 register*/
ldrr1,=0x3fffc01c/*FIO0CLR0 -- fast port0 register*/
ldrr2,=0xC0010000/*select fast port 0.16 for toggle*/
ldrr3,=0xE0028014/*IO1SET -- slow port1 register*/
ldrr4,=0xE002801C/*IO1CLR -- slow port1 register*/
ldrr5,=0x00100000/*select slow port 1.20 for toggle*/
/*Generate 2 pulses on the fast port*/
strr2,[r0]
• Register locations conform to ‘550 industry standard.
• Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
• Built-in fractional baud rate generator with autobauding capabilities.
• Mechanism that enables software and hardware flow control implementation.
9.2 Pin description
Table 95:UART0 pin description
PinTypeDescription
RXD0InputSerial Input. Serial receive data.
TXD0OutputSerial Output. Serial transmit data.
9.3 Register description
UART0 contains registers organized as shown in Table 96. The Divisor Latch Access Bit
(DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.
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The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains
the oldest character received and can be read via the bus interface. The LSB (bit 0)
represents the “oldest” receive d data bit. If the character received is less than 8 bits, the
unused MSBs are padded with zeroes.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0RBR. The U0RBR is always Read Only.
Since PE, FE and BI bits correspond to the byte sitting on the top of the RBR FIFO (i.e.
the one that will be read in the next read from the RBR), the right approach fo r f etching the
valid pair of received byte and its status bits is first to read the content of the U0LSR
register, and then to read a byte from the U0RBR.
T able 97: UART0 Receiver Buffer Register (U0RBR - address 0xE000 C000, when DLAB = 0,
BitSymbolDescriptionReset value
7:0RBRThe UART0 Receiver Buffer Register contains the oldest
The U0THR is the top byte of the U AR T0 TX FIFO. The top byte is the new est character in
the TX FIFO and can be written via the bus interface. The LSB represents the first bit to
transmit.
The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the
U0THR. The U0THR is always Write Only.
7:0THRWriting to the UART0 Transmit Holding Register causes the data
to be stored in the UART0 transmit FIFO. The byte will be sent
when it reaches the bottom of the FIFO and the transmitter is
available.
NA
9.3.3 UART0 Divisor Latch Registers (U0DLL - 0xE000 C000 and U0DLM 0xE000 C004, when DLAB = 1)
The UAR T0 Divisor Latch is part of the U ART0 Fractional Baud Rate Gener ator an d holds
the value used to divide the clock supplied by the fractional prescaler in order to produce
the baud rate clock, which must be 16x the desired baud rate (
and U0DLM registers together f orm a 16 bit divisor where U0DLL co ntains the lo wer 8 bits
of the divisor and U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is
treated like a 0x0001 v alue as di vision b y zero is not allo wed. The Divisor Latch Access Bit
(DLAB) in U0LCR must be one in order to access the UART0 Divisor Latches.
Equation 1). The U0DLL
Details on how to select the right value for U0DLL and U0DLM can be found later on i n
this chapter.
The UAR T0 F ractional Divider Register ( U0FDR) controls the cloc k pre-scaler for the baud
rate generation and can be rea d and written at user’s discretion. This pre-scaler takes t he
VPB clock and generates an output clock per specified fractional requirements.
T able 101: UAR T0 Fractional Divider Register (U0FDR - address 0xE000 C028) bit description
BitFunctionDescriptionReset value
3:0DIVADDVAL Baudrate generation pre-scaler divisor value. If this field is 0,
7:4MULVALBaudrate pre-scaler multiplier value. This field must be greater
31:8 -Reserved, user software should not write ones to reserved bits.
= 1) bit description
DLAB
register, determines the baud rate of the UART0.
= 1) bit description
DLAB
register, determines the baud rate of the UART0.
fractional baudrate generator will not impact the UART0
baudrate.
or equal 1 for UART0 to operate properly, regardless of
whether the fractional baudrate generator is used or not.
The value read from a reserved bit is not defined.
UM10139
0x01
0x00
0
1
NA
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of U AR T0 disabled making sure that U ART0 is
fully software and hardware compatible with UARTs not equipped with this feature.
UART0 baudrate can be calculated as:
(1)
UART0
Where PCLK is the peripheral clock, U0DLM and U0DLL are the standard UART0 baud
rate divider registers, and DIVADDVAL and MULVAL are UART0 fractional baudrate
generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
If the U0FDR register value does not comply to these two requests then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled
and the clock will not be divided.
The value of the U0FDR should not be modified while transmitting/receiving data or data
may be lost or corrupted.
Usage Note: For practical pu rposes, UART0 baudrate formula can be written in a way
that identifies the part of a UART baudrate generated without the fractional baudrate
generator, and the correction factor that this module adds:
UM10139
(2)
UART0
Based on this representation, fractional baudrate generator contribution can also be
described as a prescaling with a factor of MULVAL
[1] Values in the row represent decimal equivalent of a 16 bit long content (DLM:DLL).
[2] Values in the row represent hex equivalent of a 16 bit long content (DLM:DLL).
[3] Refers to the percent error between desired and actual baudrate.