Philips HEF4511BU, HEF4511BT, HEF4511BPB, HEF4511BP, HEF4511BDB Datasheet
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DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4511B
MSI
BCD to 7-segment
latch/decoder/driver
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver
HEF4511B
MSI
DESCRIPTION
The HEF4511B is a BCD to 7-segment
latch/decoder/driver with four address inputs (DAto DD),
an active LOW latch enable input (EL), an active LOW
ripple blanking input (BI), an active LOW lamp test input
(LT), and seven active HIGH n-p-n bipolar transistor
segment outputs (Oato Og).
When
EL is LOW, the state of the segment outputs (Oato
Og) is determined by the data on DAto DD.
When EL goes HIGH, the last data present on DAto
DDare stored in the latches and the segment outputs
remain stable. When LT is LOW, all the segment outputs
are HIGH independent of all other input conditions. With
LT HIGH, a LOW on BI forces all segment outputs LOW.
The inputs LT and BI do not affect the latch circuit.
Fig.1 Functional diagram.
PINNING
HEF4511BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4511BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4511BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
D
A
to D
D
address (data) inputs
EL latch enable input (active LOW)
BI ripple blanking input (active LOW)
LT lamp test input (active LOW)
O
a
to O
g
segment outputs
Fig.2 Pinning diagram.
Fig.3 Schematic diagram of output stage.
FAMILY DATA, IDDLIMITS category MSI
See Family Specifications
Fig.4 Segment
designation.
January 1995 3
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver
HEF4511B
MSI
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Fig.5 Logic diagram; for one latch see Fig.6.
January 1995 4
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver
HEF4511B
MSI
FUNCTION TABLE
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
* Depends upon the BCD code applied during the LOW to HIGH transition of
EL.
INPUTS OUTPUTS
EL BI LTDDDCDBDAOaObOcOdOeOfOgDISPLAY
XXLXXXXHH HHHHH 8
X L H X X X X L L L L L L L blank
LHHL L L LHHHHHHL 0
LHHLLLHLHHLLLL 1
LHHLLHLHHLHHLH 2
LHHL L H H H H H H L L H 3
LHHLHLLLHHLLHH 4
LHHLHLHHLHHLHH 5
LHHLHH LL L HHHHH 6
LHHLHHHHHHLLLL 7
LHHHL L LHH HHHHH 8
LHHH L L H H H H L L HH 9
L H H H L H L L L L L L L L blank
L H H H L H H L L L L L L L blank
L H H H H L L L L L L L L L blank
L H H H H L H L L L L L L L blank
L H H H H H L L L L L L L L blank
L H H H H H H L L L L L L L blank
HHHX X X X * *
Fig.6 Logic diagram (one latch); see also Fig.5.
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