Philips HEF4511BU, HEF4511BT, HEF4511BPB, HEF4511BP, HEF4511BDB Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4511B MSI
BCD to 7-segment latch/decoder/driver
Product specification |
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January 1995 |
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File under Integrated Circuits, IC04 |
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Philips Semiconductors |
Product specification |
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BCD to 7-segment latch/decoder/driver
HEF4511B
MSI
DESCRIPTION
The HEF4511B is a BCD to 7-segment latch/decoder/driver with four address inputs (DA to DD),
an active LOW latch enable input (EL), an active LOW ripple blanking input (BI), an active LOW lamp test input (LT), and seven active HIGH n-p-n bipolar transistor segment outputs (Oa to Og).
Fig.1 Functional diagram.
Fig.3 Schematic diagram of output stage.
When EL is LOW, the state of the segment outputs (Oa to Og) is determined by the data on DA to DD.
When EL goes HIGH, the last data present on DA to DD are stored in the latches and the segment outputs
remain stable. When LT is LOW, all the segment outputs are HIGH independent of all other input conditions. With LT HIGH, a LOW on BI forces all segment outputs LOW. The inputs LT and BI do not affect the latch circuit.
Fig.2 Pinning diagram.
HEF4511BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4511BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4511BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
PINNING |
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DA to DD |
address (data) inputs |
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latch enable input (active LOW) |
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EL |
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ripple blanking input (active LOW) |
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BI |
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lamp test input (active LOW) |
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LT |
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Oa to Og |
segment outputs |
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Fig.4 Segment
designation.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995 |
2 |
_
1995 January
3
Fig.5 Logic diagram; for one latch see Fig.6.
latch/decoder/driver segment-7 to BCD
HEF4511B MSI
Semiconductors Philips
specification Product
Philips Semiconductors |
Product specification |
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BCD to 7-segment latch/decoder/driver
HEF4511B
MSI
Fig.6 Logic diagram (one latch); see also Fig.5.
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
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DD |
DC |
DB |
DA |
Oa |
Ob |
Oc |
Od |
Oe |
Of |
Og |
DISPLAY |
EL |
BI |
LT |
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X |
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X |
L |
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X |
X |
X |
X |
H |
H |
H |
H |
H |
H |
H |
8 |
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X |
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L |
H |
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X |
X |
X |
X |
L |
L |
L |
L |
L |
L |
L |
blank |
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L |
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H |
H |
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L |
L |
L |
L |
H |
H |
H |
H |
H |
H |
L |
0 |
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L |
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H |
H |
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L |
L |
L |
H |
L |
H |
H |
L |
L |
L |
L |
1 |
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L |
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H |
H |
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L |
L |
H |
L |
H |
H |
L |
H |
H |
L |
H |
2 |
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L |
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H |
H |
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L |
L |
H |
H |
H |
H |
H |
H |
L |
L |
H |
3 |
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L |
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H |
H |
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L |
H |
L |
L |
L |
H |
H |
L |
L |
H |
H |
4 |
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L |
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H |
H |
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L |
H |
L |
H |
H |
L |
H |
H |
L |
H |
H |
5 |
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L |
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H |
H |
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L |
H |
H |
L |
L |
L |
H |
H |
H |
H |
H |
6 |
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L |
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H |
H |
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L |
H |
H |
H |
H |
H |
H |
L |
L |
L |
L |
7 |
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L |
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H |
H |
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H |
L |
L |
L |
H |
H |
H |
H |
H |
H |
H |
8 |
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L |
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H |
H |
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H |
L |
L |
H |
H |
H |
H |
L |
L |
H |
H |
9 |
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L |
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H |
H |
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H |
L |
H |
L |
L |
L |
L |
L |
L |
L |
L |
blank |
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L |
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H |
H |
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H |
L |
H |
H |
L |
L |
L |
L |
L |
L |
L |
blank |
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L |
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H |
H |
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H |
H |
L |
L |
L |
L |
L |
L |
L |
L |
L |
blank |
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L |
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H |
H |
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H |
H |
L |
H |
L |
L |
L |
L |
L |
L |
L |
blank |
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L |
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H |
H |
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H |
H |
H |
L |
L |
L |
L |
L |
L |
L |
L |
blank |
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L |
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H |
H |
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H |
H |
H |
H |
L |
L |
L |
L |
L |
L |
L |
blank |
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H |
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H |
H |
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X |
X |
X |
X |
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* |
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* |
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Note
1.H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial
*Depends upon the BCD code applied during the LOW to HIGH transition of EL.
January 1995 |
4 |
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