INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4510B
MSI
BCD up/down counter
Product specification |
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January 1995 |
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File under Integrated Circuits, IC04 |
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Philips Semiconductors |
Product specification |
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BCD up/down counter
HEF4510B
MSI
DESCRIPTION
The HEF4510B is an edge-triggered synchronous up/down BCD counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (P0 to P3), four parallel outputs (O0 to O3), an active LOW terminal count output
(TC), and an overriding asynchronous master reset input (MR).
Information on P0 to P3 is loaded into the counter while PL is HIGH, independent of all other input conditions except the MR input, which must be LOW. With PL LOW, the counter changes on the LOW to HIGH transition of CP if CE is LOW. UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when O0 and O3 are HIGH and
CE is LOW. When counting down, TC is LOW when O0 to
O3 and CE are LOW. A HIGH on MR resets the counter (O0 to O3 = LOW) independent of all other input conditions.
Fig.1 Functional diagram.
HEF4510BP(N): |
16-lead DIL; plastic |
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(SOT38-1) |
HEF4510BD(F): |
16-lead DIL; ceramic (cerdip) |
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(SOT74) |
HEF4510BT(D): |
16-lead SO; plastic |
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(SOT109-1) |
( ): Package Designator North America
PINNING |
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PL |
parallel load input (active HIGH) |
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P0 to P3 |
parallel inputs |
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count enable input (active LOW) |
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CE |
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CP |
clock pulse input (LOW to HIGH, |
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edge triggered) |
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up/down count control input |
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UP/DN |
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MR |
master reset input |
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terminal count output (active LOW) |
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TC |
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O0 to O3 |
parallel outputs |
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FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.2 Pinning diagram.
January 1995 |
2 |
Philips Semiconductors |
Product specification |
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BCD up/down counter
HEF4510B
MSI
Fig.3 Logic diagram (continued in Fig.4).
January 1995 |
3 |
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