Philips HEF4508BU, HEF4508BT, HEF4508BPB, HEF4508BP, HEF4508BD Datasheet
DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4508B
MSI
Dual 4-bit latch
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Dual 4-bit latch
HEF4508B
MSI
DESCRIPTION
The HEF4508B is a dual 4-bit latch, which consists of two
identical independent 4-bit latches with separate strobe
(ST), master reset (MR), output-enable input (EO) and
3-state outputs (O).
With the ST input in the HIGH state, the data on the D
inputs appear at the corresponding outputs providedEO is
LOW. Changing the ST input to the LOW state locks the
data into the latch. A HIGH on the reset line forces the
outputs to a LOW level regardless of the state of the ST
input. The 3-state outputs are controlled by the
output-enable input. A HIGH on
EO causes the outputs to
assume a high impedance OFF-state regardless of other
input conditions. This allows the outputs to interface
directly with bus orientated systems. When EO is LOW the
contents of the latches are available at the outputs.
FAMILY DATA, I
DD
LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
January 1995 3
Philips Semiconductors Product specification
Dual 4-bit latch
HEF4508B
MSI
PINNING
FUNCTION TABLE
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Z = high impedance OFF state
HEF4508BP(N): 24-lead DIL; plastic
(SOT101-1)
HEF4508BD(F): 24-lead DIL; ceramic (cerdip)
(SOT94)
HEF4508BT(D): 24-lead SO; plastic
(SOT137-1)
( ): Package Designator North America
D
0A
to D3A, D0B to D
3B
data inputs
ST
A
, ST
B
strobe inputs
MR
A
, MR
B
master reset inputs
EOA, EO
B
output enable inputs
O
0A
to O3A,O0Bto O
3B
3-state outputs
INPUTS OUTPUT
MR ST
EO D
n
O
n
LHL H H
LHL L L
L L L X latched
HXL X L
XXH X Z
Fig.2 Pinning diagram.
Loading...