Philips HEF4076BU, HEF4076BT, HEF4076BPB, HEF4076BP, HEF4076BDB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4076B MSI

Quadruple D-type register with 3-state outputs

Product specification			January 1995
File under Integrated Circuits, IC04

Philips Semiconductors	Product specification

Quadruple D-type register with 3-state outputs

HEF4076B

MSI

DESCRIPTION

The HEF4076B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), two active LOW

data enable inputs (ED0 and ED1), a common clock input (CP), four 3-state outputs (O0 to O3), two active LOW

output enable inputs (EO0 and EO1), and an overriding asynchronous master reset input (MR).

Fig.1 Functional diagram.

Information on D0 to D3 is stored in the four flip-flops on the LOW to HIGH transition of CP if both ED0 and ED1 are

LOW. A HIGH on either ED0 or ED1 prevents the flip-flops from changing on the LOW to HIGH transition of CP, independent of the information on D0 to D3. When both

EO0 and EO1 are LOW, the contents of the four flip-flops

are available at O0 to O3. A HIGH on either EO0 or

EO1 forces O0 to O3 into the high impedance OFF-state. A HIGH on MR resets all four flip-flops, independent of all other input conditions.

Fig.2 Pinning diagram.

HEF4076BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF4076BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4076BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

PINNING									FAMILY DATA, IDD LIMITS category MSI
	D0 to D3							data inputs	See Family Specifications
						1		data enable inputs (active LOW)
	ED	0,		ED
							1	output enable inputs (active LOW)
	EO		0,		EO
	CP							clock input (LOW to HIGH, edge-triggered)
	MR							master reset input
	O0 to O3							data outputs

January 1995

2

Philips Semiconductors	Product specification

Quadruple D-type register with 3-state outputs

HEF4076B

MSI

Fig.3 Logic diagram.

January 1995

3