Philips HEF4069UBU, HEF4069UBT, HEF4069UBPB, HEF4069UBP, HEF4069UBDB Datasheet

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC

∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC

HEF4069UB gates

Hex inverter

Product specification			January 1995
File under Integrated Circuits, IC04

Philips Semiconductors	Product specification

Hex inverter

HEF4069UB gates

DESCRIPTION

The HEF4069UB is a general purpose hex inverter. Each of the six inverters is a single stage.

Fig.2 Pinning diagram.

HEF4069UBP(N): 14-lead DIL; plastic (SOT27-1)

HEF4069UBD(F): 14-lead DIL; ceramic (cerdip) (SOT73)

HEF4069UBT(D): 14-lead SO; plastic (SOT108-1)

( ): Package Designator North America

Fig.1 Functional diagram.

FAMILY DATA, IDD LIMITS category GATES

See Family Specifications for VIH/VIL unbuffered stages

Fig.3 Schematic diagram (one inverter).

January 1995

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Philips Semiconductors Product specification

Hex inverter										HEF4069UB
										gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times £ 20 ns
		VDD	SYMBOL	TYP. MAX.			TYPICAL EXTRAPOLATION FORMULA
		V
Propagation delays	5			45	90	ns		18 ns	+	(0,55 ns/pF) CL
In ® On	10		tPHL	20	40	ns		9 ns	+	(0,23 ns/pF) CL
HIGH to LOW	15			15	25	ns		7 ns	+	(0,16 ns/pF) CL
	5			40	80	ns		13 ns	+	(0,55 ns/pF) CL
LOW to HIGH	10		tPLH	20	40	ns		9 ns	+	(0,23 ns/pF) CL
	15			15	30	ns		7 ns	+	(0,16 ns/pF) CL
Output transition times	5			60	120	ns		10 ns	+	(1,0 ns/pF) CL
HIGH to LOW	10		tTHL	30	60	ns		9 ns	+	(0,42 ns/pF) CL
	15			20	40	ns		6 ns	+	(0,28 ns/pF) CL
	5			60	120	ns		10 ns	+	(1,0 ns/pF) CL
LOW to HIGH	10		tTLH	30	60	ns		9 ns	+	(0,42 ns/pF) CL
	15			20	40	ns		6 ns	+	(0,28 ns/pF) CL
		VDD	TYPICAL FORMULA FOR P (mW)
		V
Dynamic power		5	600 fi + å (foCL) ´ VDD2						where
dissipation per		10	4 000 fi + å (foCL) ´ VDD2						fi = input freq. (MHz)
package (P)		15	22 000 fi + å (foCL) ´ VDD2						fo = output freq. (MHz)
									CL = load capacitance (pF)
									å (foCL) = sum of outputs
									VDD = supply voltage (V)

January 1995

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