Philips hef4069ub DATASHEETS
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4069UB
gates
Hex inverter
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors Product specification
Hex inverter
DESCRIPTION
The HEF4069UB is a general purpose hex inverter. Each
of the six inverters is a single stage.
HEF4069UB
gates
Fig.2 Pinning diagram.
Fig.1 Functional diagram.
HEF4069UBP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4069UBD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4069UBT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
FAMILY DATA, IDDLIMITS category GATES
See Family Specifications for V
unbuffered stages
IH/VIL
Fig.3 Schematic diagram (one inverter).
January 1995 2
Philips Semiconductors Product specification
Hex inverter
HEF4069UB
AC CHARACTERISTICS
V
= 0 V; T
SS
Propagation delays 5 45 90 ns 18 ns + (0,55 ns/pF) C
In→ O
HIGH to LOW 15 15 25 ns 7 ns + (0,16 ns/pF) C
LOW to HIGH 10 t
Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) C
HIGH to LOW 10 t
LOW to HIGH 10 t
=25°C; CL= 50 pF; input transition times ≤ 20 ns
amb
V
DD
V
n
10 t
SYMBOL TYP. MAX.
PHL
54080ns13ns+(0,55 ns/pF) C
PLH
15 15 30 ns 7 ns + (0,16 ns/pF) C
THL
15 20 40 ns 6 ns + (0,28 ns/pF) C
5 60 120 ns 10 ns + (1,0 ns/pF) C
TLH
15 20 40 ns 6 ns + (0,28 ns/pF) C
TYPICAL EXTRAPOLATION FORMULA
20 40 ns 9 ns + (0,23 ns/pF) C
20 40 ns 9 ns + (0,23 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
30 60 ns 9 ns + (0,42 ns/pF) C
gates
L
L
L
L
L
L
L
L
L
L
L
L
V
DD
V
TYPICAL FORMULA FOR P (µW)
Dynamic power 5 600 f
dissipation per 10 4 000 f
package (P) 15 22 000 f
+∑(foCL) × V
i
+∑(foCL) × V
i
+∑(foCL) × V
i
DD
DD
DD
2
2
2
where
fi= input freq. (MHz)
fo= output freq. (MHz)
C
= load capacitance (pF)
L
∑ (f
) = sum of outputs
oCL
= supply voltage (V)
V
DD
January 1995 3
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