Philips HEF4067BU, HEF4067BT, HEF4067BPB, HEF4067BP, HEF4067BDB Datasheet
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DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4067B
MSI
16-channel analogue
multiplexer/demultiplexer
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
16-channel analogue
multiplexer/demultiplexer
HEF4067B
MSI
DESCRIPTION
The HEF4067B is a 16-channel analogue
multiplexer/demultiplexer with four address inputs (A0to
A3), an active LOW enable input (E), sixteen independent
inputs/outputs (Y0to Y15) and a common input/output (Z).
The device contains sixteen bidirectional analogue
switches, each with one side connected to an independent
input/output (Y
0
to Y15) and the other side connected to
the common input/output (Z).
With E LOW, one of the sixteen switches is selected (low
impedance ON-state) by A0to A3. All unselected switches
are in the high impedance OFF-state. With E HIGH all
switches are in the high impedance OFF-state,
independent of A0to A3.
The analogue inputs/outputs (Y0to Y15and Z) can swing
between VDDas a positive limit and VSSas a negative
limit. VDDto VSSmay not exceed 15 V.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
PINNING
HEF4067BP(N): 24-lead DIL; plastic
(SOT101-1)
HEF4067BD(F): 24-lead DIL; ceramic (cerdip)
(SOT94)
HEF4067BT(D): 24-lead SO; plastic
(SOT137-1)
( ): Package Designator North America
Y
0
to Y
15
independent inputs/outputs
A
0
to A
3
address inputs
E enable input (active LOW)
Z common input/output
Fig.2 Pinning diagram.
January 1995 3
Philips Semiconductors Product specification
16-channel analogue
multiplexer/demultiplexer
HEF4067B
MSI
FUNCTION TABLE
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
INPUTS CHANNEL
EA
3
A
2
A
1
A
0
ON
LLLLLY
0
−Z
LLLLHY
1
−Z
LLLHLY
2
−Z
LLLHHY
3
−Z
LLHLLY
4
−Z
LLHLHY
5
−Z
LLHHLY
6
−Z
LLHHHY
7
−Z
LHLLLY
8
−Z
LHLLHY
9
−Z
LHLHLY
10
− Z
LHLHHY
11
− Z
LHHLLY
12
− Z
LHHLHY
13
− Z
LHHHLY
14
− Z
LHHHHY
15
− Z
H X X X X none
Fig.3 Schematic diagram (one switch).
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