Philips HEF4066BU, HEF4066BT, HEF4066BPB, HEF4066BP, HEF4066BDB Datasheet
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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4066B gates
Quadruple bilateral switches
Product specification |
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January 1995 |
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File under Integrated Circuits, IC04 |
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Philips Semiconductors |
Product specification |
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Quadruple bilateral switches
HEF4066B gates
DESCRIPTION
The HEF4066B has four independent bilateral analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to VDD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connected to VSS the switch is
Fig.1 Functional diagram.
HEF4066BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4066BD(F): 14-lead DIL; ceramic (cerdip) (SOT73))
HEF4066BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
disabled and a high impedance between Y and Z is established (OFF condition).
The HEF4066B is pin compatible with the HEF4016B but exhibits a much lower ON resistance. In addition the ON resistance is relatively constant over the full input signal range.
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Fig.2 Pinning diagram. |
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PINNING |
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E0 to E3 |
enable inputs |
Y0 to Y3 |
input/output terminals |
Z0 to Z3 |
input/output terminals |
APPLICATION INFORMATION
An example of application for the HEF4066B is:
∙ Analogue and digital switching
Fig.3 Schematic diagram (one switch).
January 1995 |
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Philips Semiconductors |
Product specification |
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Quadruple bilateral switches
HEF4066B gates
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Power dissipation per switch |
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P |
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max. 100 mW |
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For other RATINGS see Family Specifications |
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DC CHARACTERISTICS |
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Tamb = 25 °C |
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VDD |
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SYMBOL |
MIN. |
TYP. |
MAX. |
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CONDITIONS |
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V |
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5 |
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− |
350 |
2500 |
Ω |
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En at VDD |
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ON resistance |
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10 |
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RON |
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− |
80 |
245 |
Ω |
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Vis = VSS to VDD |
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15 |
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− |
60 |
175 |
Ω |
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see Fig.4 |
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5 |
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− |
115 |
340 |
Ω |
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En at VDD |
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ON resistance |
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10 |
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RON |
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− |
50 |
160 |
Ω |
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Vis = VSS |
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15 |
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− |
40 |
115 |
Ω |
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see Fig.4 |
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5 |
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− |
120 |
365 |
Ω |
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En at VDD |
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ON resistance |
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10 |
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RON |
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− |
65 |
200 |
Ω |
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Vis = VDD |
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15 |
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− |
50 |
155 |
Ω |
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see Fig.4 |
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‘ ’ ON resistance |
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5 |
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− |
25 |
− |
Ω |
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En at VDD |
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between any two |
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10 |
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RON |
− |
10 |
− |
Ω |
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Vis = VSS to VDD |
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channels |
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15 |
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− |
5 |
− |
Ω |
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see Fig.4 |
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OFF state leakage |
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5 |
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− |
− |
− |
nA |
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current, any |
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10 |
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IOZ |
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− |
− |
− |
nA |
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En at VSS |
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channel OFF |
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15 |
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− |
− |
200 |
nA |
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En input voltage |
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5 |
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− |
2,25 |
1 |
V |
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Iis = 10 μA |
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LOW |
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10 |
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VIL |
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− |
4,50 |
2 |
V |
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see Fig.9 |
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15 |
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− |
6,75 |
2 |
V |
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VDD |
SYMBOL |
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Tamb (°c) |
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CONDITIONS |
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V |
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−40 |
+25 |
+85 |
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MAX. |
MAX. |
MAX. |
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Quiescent device |
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5 |
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1,0 |
1,0 |
7,5 |
μA |
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VSS = 0; all valid |
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current |
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10 |
IDD |
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2,0 |
2,0 |
15,0 |
μA |
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input combinations; |
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15 |
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4,0 |
4,0 |
30,0 |
μA |
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VI = VSS or VDD |
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Input leakage current at En |
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15 |
± IIN |
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− |
300 |
1000 |
nA |
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En at VSS or VDD |
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January 1995 |
3 |
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