Philips HEF4066BU, HEF4066BT, HEF4066BPB, HEF4066BP, HEF4066BDB Datasheet
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DATA SH EET
Product specification
File under Integrated Circuits, IC04
January 1995
INTEGRATED CIRCUITS
HEF4066B
gates
Quadruple bilateral switches
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
DESCRIPTION
The HEF4066B has four independent bilateral analogue
switches (transmission gates). Each switch has two
input/output terminals (Y/Z) and an active HIGH enable
input (E). When E is connected to VDDa low impedance
bidirectional path between Y and Z is established (ON
condition). When E is connected to VSSthe switch is
disabled and a high impedance between Y and Z is
established (OFF condition).
The HEF4066B is pin compatible with the HEF4016B but
exhibits a much lower ON resistance. In addition the ON
resistance is relatively constant over the full input signal
range.
Fig.1 Functional diagram. Fig.2 Pinning diagram.
HEF4066BP(N): 14-lead DIL; plastic (SOT27-1)
HEF4066BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73))
HEF4066BT(D): 14-lead SO; plastic (SOT108-1)
( ): Package Designator North America
PINNING
APPLICATION INFORMATION
An example of application for the HEF4066B is:
• Analogue and digital switching
E
0
to E
3
enable inputs
Y
0
to Y
3
input/output terminals
Z
0
to Z
3
input/output terminals
Fig.3 Schematic diagram (one switch).
January 1995 3
Philips Semiconductors Product specification
Quadruple bilateral switches
HEF4066B
gates
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
DC CHARACTERISTICS
T
amb
=25°C
Power dissipation per switch P max. 100 mW
For other RATINGS see Family Specifications
V
DD
V
SYMBOL MIN. TYP. MAX. CONDITIONS
ON resistance
5
R
ON
− 350 2500 Ω Enat V
DD
10 − 80 245 Ω Vis=VSSto V
DD
15 − 60 175 Ω see Fig.4
ON resistance
5
R
ON
− 115 340 Ω Enat V
DD
10 − 50 160 Ω Vis=V
SS
15 − 40 115 Ω see Fig.4
ON resistance
5
R
ON
− 120 365 Ω Enat V
DD
10 − 65 200 Ω Vis=V
DD
15 − 50 155 Ω see Fig.4
‘∆’ ON resistance 5
∆R
ON
− 25 −Ω Enat V
DD
between any two 10 − 10 −Ω Vis=VSSto V
DD
channels 15 − 5 −Ω see Fig.4
OFF state leakage 5
I
OZ
−−−nA
E
n
at V
SS
current, any 10 −−−nA
channel OFF 15 −−200 nA
E
n
input voltage 5
V
IL
− 2,25 1 V
I
is
=10µA
see Fig.9
LOW 10 − 4,50 2 V
15 − 6,75 2 V
V
DD
V
SYMBOL T
amb
(°c) CONDITIONS
−40 +25 +85
MAX. MAX. MAX.
Quiescent device 5
I
DD
1,0 1,0 7,5 µAV
SS
= 0; all valid
current 10 2,0 2,0 15,0 µA input combinations;
15 4,0 4,0 30,0 µAV
I=VSS
or V
DD
Input leakage current at E
n
15 ± I
IN
− 300 1000 nA Enat VSSor V
DD
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