Philips Semiconductors HEF4053B Datasheet
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4053B
MSI
Triple 2-channel analogue
multiplexer/demultiplexer
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors Product specification
Triple 2-channel analogue
multiplexer/demultiplexer
DESCRIPTION
The HEF4053B is a triple 2-channel analogue
multiplexer/demultiplexer with a common enable input (E).
Each multiplexer/demultiplexer has two independent
inputs/outputs (Y0and Y1), a common input/output (Z),
and select inputs (Sn). Each also contains two-bidirectional
analogue switches, each with one side connected to an
independent input/output (Y0and Y1) and the other side
connected to a common input/output (Z).
HEF4053B
MSI
With
E LOW, one of the two switches is selected (low
impedance ON-state) by Sn. WithE HIGH, all switches are
in the high impedance OFF-state, independent of SAto SC.
VDDand VSSare the supply voltage connections for the
digital control inputs (SAto SC and E).
The VDDto VSSrange is 3 to 15 V. The analogue
inputs/outputs (Y0,Y1 and Z) can swing between VDDas a
positive limit and VEEas a negative limit. VDD−VEEmay not
exceed 15 V.
For operation as a digital multiplexer/demultiplexer, VEEis
connected to VSS(typically ground).
Fig.1 Functional diagram.
FAMILY DATA, I
See Family Specifications
January 1995 2
LIMITS category MSI
DD
Philips Semiconductors Product specification
Triple 2-channel analogue
multiplexer/demultiplexer
Fig.2 Pinning diagram.
HEF4053BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4053BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4053BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
HEF4053B
PINNING
to Y
Y
0A
0C
to Y
Y
1A
1C
S
to S
A
C
E enable input (active LOW)
Z
to Z
A
C
FUNCTION TABLE
INPUTS CHANNEL
ES
LL Y
LH Y
H X none
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
independent inputs/outputs
independent inputs/outputs
select inputs
common inputs/outputs
n
ON
0n−Zn
1n−Zn
MSI
Fig.3 Schematic diagram (one switch).
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage (with reference to VDD)V
EE
−18 to + 0,5 V
Note
1. To avoid drawing V
current out of terminal Z, when switch current flows into terminals Y, the voltage drop across
DD
the bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no VDDcurrent will flow out
of terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may
not exceed VDDor VEE.
January 1995 3
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