INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
∙The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC
∙The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4047B MSI
Monostable/astable multivibrator
Product specification |
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January 1995 |
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File under Integrated Circuits, IC04 |
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Philips Semiconductors |
Product specification |
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Monostable/astable multivibrator
HEF4047B
MSI
DESCRIPTION
The HEF4047B consists of a gatable astable multivibrator with logic techniques incorporated to permit positive or negative edge-triggered monostable multivibrator action with retriggering and external counting options.
Inputs include + TRIGGER, − TRIGGER, ASTABLE, ASTABLE, RETRIGGER and MR (Master Reset). Buffered outputs are O, O and OSCILLATOR OUTPUT. In all modes of operation an external capacitor (Ct) must be connected between CTC and RCTC, and an external resistor (Rt) must be connected between RTC and
RCTC (continued on next page).
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995 |
2 |
Philips Semiconductors |
Product specification |
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Monostable/astable multivibrator
HEF4047B
MSI
Astable operation is enabled by a HIGH level on the ASTABLE input. The period of the square wave at O and O outputs is a function of the external components employed. ‘True’ input pulses on the ASTABLE or ‘complement’ pulses on the ASTABLE input, allow the circuit to be used as a gatable multivibrator. The OSCILLATOR OUTPUT period will be half of the O output in the astable mode. However, a 50% duty factor is not guaranteed at this output.
In the monostable mode, positive edge-triggering is accomplished by applying a leading-edge pulse to the
+TRIGGER input and a LOW level to the − TRIGGER
input. For negative edge-triggering, a trailing-edge pulse is applied to the − TRIGGER and a HIGH level to the
+TRIGGER. Input pulses may be of any duration relative to the output pulse. The multivibrator can be retriggered (on the leading-edge only) by applying a common pulse to both the RETRIGGER and + TRIGGER inputs. In this mode the output pulse remains HIGH as long as the input pulse period is shorter than the period determined by the RC components.
An external count down option can be implemented by coupling O to an external ‘N’ counter and resetting the counter with the trigger pulse. The counter output pulse is fed back to the ASTABLE input and has a duration equal to N times the period of the multivibrator. A HIGH level on the MR input assures no output pulse during an ON-power condition. This input can also be activated to terminate the output pulse at any time. In the monostable mode, a HIGH level or power-ON reset pulse must be applied to MR, whenever VDD is applied.
HEF4047BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4047BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4047BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
January 1995 |
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1995 January
4
(1)Special input protection that allows operating input voltages outside the supply voltage lines. Compared to the standard input protection pin 3 is more sensitive to static discharge; extra handling precautions are recommended.
Fig.3 Logic diagram.
multivibrator Monostable/astable
HEF4047B MSI
Semiconductors Philips
specification Product
Philips Semiconductors Product specification
Monostable/astable multivibrator |
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HEF4047B |
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MSI |
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FUNCTIONAL CONNECTIONS |
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PINS CONNECTED TO |
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OUTPUT |
OUTPUT |
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FUNCTION |
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PULSE |
PERIOD |
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INPUT |
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VDD |
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VSS |
FROM |
OR |
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PULSE |
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PINS |
PULSE WIDTH |
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astable multivibrator |
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free running |
4, 5, 6, 14 |
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7, 8, 9, 12 |
− |
10, 11, 13 |
at pins 10, 11: |
true gating |
4, 6, 14 |
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7, 8, 9, 12 |
5 |
10, 11, 13 |
tA = 4,40 RtCt |
complement gating |
6, 14 |
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5, 7, 8, 9, 12 |
4 |
10, 11, 13 |
at pin 13: |
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tA = 2,20 RtCt |
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monostable multivibrator |
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pos. edge-triggering |
4, 14 |
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5, 6, 7, 9, 12 |
8 |
10, 11 |
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neg. edge-triggering |
4, 8, 14 |
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5, 7, 9, 12 |
6 |
10, 11 |
at pins 10, 11: |
retriggerable |
4, 14 |
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5, 6, 7, 9 |
8, 12 |
10, 11 |
tM = 2,48 RtCt |
external count down(1) |
14 |
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5, 6, 7, 8, 9, 12 |
− |
10, 11 |
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Notes
1.Input pulse to RESET of external counting chip; external counting chip output to pin 4.
2.In all cases, external resistor between pins 2 and 3, external capacitor between pins 1 and 3.
DC CHARACTERISTICS
VSS = 0 V; inputs at VSS or VDD
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VDD |
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Tamb (°C) |
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SYMBOL |
−40 |
+ 25 |
+ 85 |
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V |
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MAX. |
MIN. |
MAX. |
MAX. |
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Leakage current |
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pin 3 at |
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pin 3; output |
15 |
I3 |
0,3 |
− |
0,3 |
1 |
μA |
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VDD or VSS |
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transistor OFF |
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January 1995 |
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