Philips HEF4020BU, HEF4020BT, HEF4020BPB, HEF4020BP, HEF4020BDB Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC04

January 1995

INTEGRATED CIRCUITS

HEF4020B
MSI

14-stage binary counter

For a complete data sheet, please also download:

•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC

•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC

January 1995 2

Philips Semiconductors Product specification

14-stage binary counter

HEF4020B

MSI

DESCRIPTION

The HEF4020B is a 14-stage binary ripple counter with a
clock input (CP), an overriding asynchronous master reset
input (MR) and twelve fully buffered outputs (O0, O3 to
O13). The counter advances on the HIGH to LOW
transition of CP. A HIGH on MR clears all counter stages
and forces all outputs LOW, independent of the state of
CP. Each counter stage is a static toggle flip-flop. A feature
of the HEF4020B is: high speed (typ. 35 MHz at
VDD= 15 V).

Fig.1 Functional diagram.

Fig.2 Pinning diagram.

PINNING

FAMILY DATA, IDDLIMITS category MSI

See Family Specifications

HEF4020BP(N): 16-lead DIL; plastic

(SOT38-1)

HEF4020BD(F): 16-lead DIL; ceramic (cerdip)

(SOT74)

HEF4020BT(D): 16-lead SO; plastic

(SOT109-1)

( ): Package Designator North America

CP clock input (HIGH to LOW edge

triggered)
MR master reset input (active HIGH)
O

0

, O3 to O

13

parallel outputs