Philips FT18-TG, FT18-SG, FT18-IG Datasheet

IMAGE SENSORS

FT 18

Frame Transf er CCD Image Sensor

Product specification 2000 January 7 File under Image Sensors

Philips Semiconductors

TRAD

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FT 18

• 2/3-inch optical format

• 1M active pixels (1024H x 1024V)

• Progressive scan

• Excellent anti-blooming

• V ariable electr onic shuttering

• Square pixel structure

• Hor . and Vert. binning

• 100% optical fill factor

• High dynamic range (>60dB)

• High sensitivity

• Low dark current and fixed pattern noise

• Low read-out noise

• Data rate up to 40 MHz

• Frame rate up to 30 Hz

• Mirrored read-out option

Device structure

Optical size: 7.68 mm (H) x 7.68 mm (V) Chip size: 8.9 mm (H) x 17.0 mm (V) Pixel size: 7.5 µm x 7.5 µm Active pixels: 1024 (H) x 1024 (V) Total no. of pixels: 1072 (H) x 1048 (V) Optical black pixels: Left: 20 Right: 20 Timing pixels: Left: 4 Right: 4 Dummy register cells: Left: 7 Right: 7 Contour lines: Bottom: 1 Top: 4 Optical black lines: Bottom: 11 Top: 8

Description

The FT 18 is a monochrome progressive-scan frame-transf er image sensor offering 1K x 1K pixels at 30 frames per second through a single output buffer . The combination of high speed and a high linear dynamic range (>10 true bits at room temperature without cooling) makes this device the perf ect solution f or high-end real time medical X-ray, scientific and industrial applications. A second output can be used for mirrored images. The device structure is shown in figure 1.

8 black lines

4 contour lines

8 black lines

Image

1024 active pixels

pix

Section

1 contour line

11 black lines

1024 active lines

20 pix

2096 lines

Figure 1 - Device structure

2000 January 2

Output amplifier

Storage

Section

1072 cells

Output register

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FT 18

Architecture of the FT 18

The FT18 consists of a shielded storage section and an open image section. Both sections have the same structure with identical cells and properties. The only difference between the two sections is the optical light shield.

The storage section is controlled by four storage clocks (B1 to B4). An output register is located below the storage section for read-out. The output register has buffers at both ends . This allo ws either normal or mirrored read-out.

The optical centres of all pixels in the image section form a square grid. The charge is generated and integrated in this section. The image section is controlled by four image clocks (A1 to A4). After integration, the image charge is completely shifted to the storage section. The integration time is electronically controlled by charge reset (CR).

IMAGE SECTION

Image diagonal Aspect ratio Active image width x height Total width x height Pixel width x height Geometric fill factor Image clock pins Capacity of each clock phase Number of active lines Number of contour lines Number of black lines Total number of lines Number of active pixels per line Number of overscan (timing) pixels per line Number of black reference pixels per line Total number of pixels per line

10.9 mm 1:1

7.680 x 7.680 mm

8.040 x 7.860 mm

7.5 x 7.5 µm 100% A1, A2, A3, A4 <3.75nF per pin 1024 4 (top) + 1 (bottom) 8 (top) + 11 (bottom) 1048 1024 8 (2x4) 40 (2x20) 1072

Transport of the pixels in the output register is controlled by three register clock phases (C1 to C3). The register can be used for v ertical binning. Horizontal binning can be achieved by summing pixel charges under the floating diffusion. More information can be found in the application note. Figure 2 shows the detailed internal structure.

STORAGE SECTION

Storage width x height Cell width x height Storage clock phases Capacity of each B phase Number of cells per line x number of lines

8.040 x 7.860 mm

7.5 x 7.5 µm

B1, B2, B3, B4 <4.1nF per pin 1072 x 1048

OUTPUT REGISTER

Output buffers (three-stage source foll ower) Number of registers Number of register cells below storage Number of extra cells to output Output register horizontal transport clock pins Capacity of each C-clock phase Overlap capacity between neighbouring C-clocks Reset Gate clock phases Capacity of each RG

2 1 (bidirectional below storage) 1072 2 x 7 3 (C1..C3) <85pF per pin <35pF 2 pins (RGL, RGR) <15pF

2000 January 3

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FT 18

A2 A3 A4

One Pixel

OUTL

C3 C3 C3C3 C3 C3 C3 C3 C3 C3 C3 C3

OG C1

A3 A4

A2 A3 A4

A1 B2

B3 B4

A1 B3 B4

B1 B2

B3 B4

A1 B3 B4

B1 B2

B3 B4 B3

A1 B3 B4

column

7 extra cells

20 black & 4 timing columns

12 lines

1K active

IMAGE

images lines

12 lines

FT CCD

STORAGE

1048 storage lines

C1C1C2 C2 C2 C1 C2 C1 C2C1

C2 C1 C2 C1 C2 C2C1 C1 C2 C1 C2 C1 C2

column

24+1

1K image pixels

column

24+1K

4 timing & 20 black columns

A2 A3 A4

A1 B2

B3 B4

A1 B3 B4

B1 B2

B3 B4

A1 B3 B4

B1 B2

B3 B4 B3

A1A1 B3 B4

column

24+1K+24

7 extra cells

OUTR

A1, A2, A3, A4: clocks of image section B1, B2, B3, B4: clocks of storage section C1, C2, C3: clocks of horizontal register OG: output gate

Figure 2 - Detailed internal structure

2000 January 4

Philips Semiconductors Product specification

Frame Transfer CCD Image Sensor FT 18

Specifications

Absolute Maximum Ratings Min. Max. Unit

GENERAL: storage temperature ambient temperature during operation voltage between any two gates DC current through any clock (absolute value) OUT current (no short circuit protections)

VOLTAGES IN RELAT ION TO VNS: VPS, SFS SFD RD All other pins

VOLTAGES IN RELAT ION TO VPS: VNS SFD, RD SFS All other pins

-55

-40

-20

-0.2 0

-30

-8

-15

-32

-0.5 +0

-8

-20

+80 +60 +20 +0.2 6

+0.5 +8 +0.5 +0.5

+30 +30 +8 +20

°C °C V µA mA

V V V V

VNS VPS SFD SFS VCS OG RD

N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain

DC Conditions

AC Clock Level Conditions

IMAGE CLOCKS: A-clock swing A-clock low level Charge Reset (CR) level on A-clocks

Charge Pump (CP) level on A- clocks STORAGE CLOCKS (duty cycle=5/8):

B-clock swing B-clock low level

OUTPUT REGISTER CLOCKS (duty cycle=1/2): C-clock swing C-clock low level

OTHER CLOCKS: Reset Gate (RG) swing Reset Gate (RG) low level

Min. Typical Max. Unit

16 2 18

-2 3 12

Min. Typical Max. Unit

9.5

adjusted 4 20 0 0

5.4 13

10 0

-5 0

10 0

5 3

10 1

24 6 22

3 8 15

V V V V V V V

V V V V

V V

All voltages in relation to SFS.

To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values.

Guaranteed charge reset requires the CR voltage to last at least 1.2µs.

2000 January 5

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