Philips fb2040a DATASHEETS

Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

1995 May 25 853-1801 15279

FEATURES

•8-bit BTL transceivers

•Separate I/O on TTL A-port

•Inverting

•Drives heavily loaded backplanes with equivalent load

impedances down to 10Ω.

•High drive 100mA BTL open collector drivers on B-port

•Allows incident wave switching in heavily loaded backplane buses

•Reduced BTL voltage swing produces less noise and reduces

power consumption

•Built-in precision band-gap reference provides accurate receiver

thresholds and improved noise immunity

•Compatible with IEEE Futurebus+ or proprietary BTL backplanes

•Controlled output ramp and multiple GND pins minimize ground

bounce

•Each BTL driver has a dedicated Bus GND for a signal return

•Glitch-free power up/power down operation

•Low I

current

•Tight output skew

•Supports live insertion

•Pins for the optional JTAG boundary scan function are provided

•High density packaging in plastic Quad Flat Pack

QUICK REFERENCE DATA

SYMBOL PARAMETER TYPICAL UNIT

PLH

PHL

Propagation delay AIn to Bn

4.4

3.1

PLH

PHL

Propagation delay Bn

to AOn

3.4

3.2

Output capacitance (B0 – B7 only) 4 pF

Output current (B0 – B7 only) 100 mA

Standby 4

AIn to Bn

(outputs Low or High)

Bn to AOn

(outputs Low)

Bn to AOn

(outputs High)

ORDERING INFORMATION

PACKAGES

COMMERCIAL RANGE

= 5V±10%; T

amb

= 0°C to +70°C

DRAWING

NUMBER

52-pin Plastic Quad Flat Pack (QFP) FB2040BB SOT379-1

ABSOLUTE MAXIMUM RATINGS

Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.

SYMBOL

PARAMETER RATING UNIT

Supply voltage -0.5 to +7.0 V

AI0 – AI7, OEB0, OEB1, OEA -1.2 to +7.0

Input voltage

B0 – B7 -1.2 to +5.5

Input current -18 to +5.0 mA

OUT

Voltage applied to output in High output state -0.5 to +V

A0 – A7 48

OUT

Current applied to output in Low output state

B0 – B7 200

amb

Operating free-air temperature range -40 to ++85 °C

STG

Storage temperature -65 to +150 °C

Supply current

Current applied to output in Low

Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

1995 May 25

PIN CONFIGURATION

52 51 50 49 48 47 46 45 44 43 42 41 40

39 38 37 36 35 34 33

32 31 30 29 28 27

1 2 3 4 5 6 7

9 10 11 12 13

14 15 16 17 18 19 20 21 22 23 24 25 26

BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND

LOGIC GND

AI1

AI2

AO2

LOGIC GND

AO3

LOGIC GND

AI3

AI4

AO4

LOGIC GND

AO5

LOGIC GND

AI5

LOGIC GND

AO6

BG GND

TDO (option)

TDI (option)

AI6

BUS V

BG V

AO1

AO0

OEA

TCK (option)

TMS (option)

BUS GND

OEB1

BIAS V

B0/B0

BUS V

LOGIC V

OEB0

8-Bit Transceiver

FB2040A

52-lead PQFP

AI0

AI7

AO7

SG00076

DESCRIPTION

The FB2040A is an 8-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FB2040A is an inverting transceiver.

The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V .

The B-port interfaces to “Backplane Transceiver Logic” (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes.

The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEA goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEA goes Low, A-port drivers become High impedance without any extra delay. During power on/of f cycles, the A-port drivers are held in a High impedance state when V

is below 2.5V.

The B-port has two output enables, OEB0 and OEB1

. When OEB0

is High and OEB1

is Low the output is enabled. When OEB0 is Low

or if OEB1

is High, the B-port is inactive and is at the level of the

backplane signal. To support live insertion, OEB0 is held Low during power on/off

cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while V

is Low. If live insertion is not a requirement, the

BIAS V pin should be tied to a V

pin.

The LOGIC GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package.

Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a “hard” signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot.

The LOGIC V

and BUS VCC pins are also isolated internally to minimize noise and may be externally decoupled separately or simply tied together.

JTAG boundary scan pins are provided with signals TMS, TCK, TDI and TDO. TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally. Boundary scan functionality is not implemented at this time.

Philips Semiconductors Product specification

FB2040A8-bit Futurebus+ transceiver

1995 May 25

PIN DESCRIPTION

SYMBOL PIN NUMBER TYPE NAME AND FUNCTION

AI0 – AI7 51, 2, 3, 8, 9, 14, 18, 24 Input Data inputs (TTL)

AO0 – AO7 50, 52, 4, 6, 10, 12, 16, 20 Output 3-state outputs (TTL)

B0 – B7

40, 38, 36, 34,

32, 30, 28, 26

I/O Data inputs/Open Collector outputs. High current drive (BTL)

OEB0 46 Input Enables the B outputs when High OEB1 45 Input Enables the B outputs when Low

OEA 47 Input Enables the A outputs when High

BUS GND 41, 39, 37, 35, 33, 31, 29, 27 GND Bus ground (0V)

LOGIC GND 1, 5, 7, 11, 13, 15 GND Logic ground (0V)

BUS V

23, 43 Power Positive supply voltage

LOGIC V

49 Power Positive supply voltage

BG V

17 Power Band Gap threshold voltage reference

BG GND 19 GND Band Gap threshold voltage reference ground

BIAS V 48 Power Live insertion pre-bias pin

TMS 42 Input Test Mode Select (optional, if not implemented then no-connect) TCK 44 Input Test Clock (optional, if not implemented then no-connect)

TDI 22 Input Test Data In (optional, if not implemented then shorted to TDO)

TDO 21 Output Test Data Out (optional, if not implemented then shorted to TDI)

NC 25 NC No Connect

FUNCTION TABLE

INPUTS OUTPUTS

MODE

AIn Bn* OEB0 OEB1 OEA AOn Bn*

L — H L L Z H**

H — H L L Z L

AIn to Bn

L — H L H L H**

H — H L H H L

X X L X X X H**

Disable Bn outputs

X X X H X X H** X L L X H H Input X H X H H L Input

Bn to AOn

X L X H H H Input

to AOn

X H L X H L Input

Disable AOn outputs — X X X L Z X

H** = Goes to level of pull-up voltage B* = Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.

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