CXA1616N/S
Sync Discriminator for CRT Displays
Description
The CXA1616N/S automatically selects one of three types of sync signals – separate sync, composite sync, or sync-on video – to shape the waveform. It is ideally suited as a synchronous signal processor for auto tracking type displays.
Features
•Output of synchronous signal polarity information is obtainable
•Supported polarities and amplitudes of input signals are as follows:
—V. separate sync
(positive/negative polarity, 1 to 5Vp-p For capacitor input 1.5 to 5Vp-p)
— H. separate sync
(positive/negative polarity, 1 to 5Vp-p)
— Composite sync
(positive/negative polarity, 1 to 5Vp-p)
— Sync-on video
(negative polarity sync level: 0.2 to 0.6Vp-p, picture level: 0 to 2.1Vp-p)
Applications
CRT display monitors
Pin Configuration (Top View)
(SSOP)
CXA1616N |
CXA1616S |
24 pin SSOP (Plastic) |
22 pin SDIP (Plastic) |
Absolute Maximum Ratings (Ta = 25°C) |
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• Supply voltage |
Vcc |
14 |
V |
• Operating temperature |
Topr |
–20 to +75 |
°C |
• Storage temperature |
Tstg |
–65 to +150 |
°C |
• Allowable power dissipation |
PD |
900 |
mW |
Operating Condition |
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Supply voltage |
Vcc |
12 ± 0.5 |
V |
(SDIP)
VS IN |
1 |
24 |
VCC |
VS IN |
1 |
22 |
VCC |
PVC |
2 |
23 |
VD |
PVC |
2 |
21 |
VD |
EVC |
3 |
22 |
V IN |
EVC |
3 |
20 |
V IN |
CS IN |
4 |
21 |
V OUT |
CS IN |
4 |
19 |
V OUT |
PHC |
5 |
20 |
HD |
PHC |
5 |
18 |
HD |
EHC |
6 |
19 |
PV |
EHC |
6 |
17 |
PV |
VIDEO IN |
7 |
18 |
PH |
VIDEO IN |
7 |
16 |
PH |
HD SEL |
8 |
17 |
EV |
HD SEL |
8 |
15 |
EV |
TIMING |
9 |
16 |
EH |
TIMING |
9 |
14 |
EH |
CLAMP |
10 |
15 |
IN/EXT |
CLAMP |
10 |
13 |
IN/EXT |
GND |
11 |
14 |
V REF |
GND |
11 |
12 |
V REF |
NC |
12 |
13 |
NC |
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Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E92Y01C7Y-PS
CXA1616N/S
Block Diagram
(SSOP) |
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PVC |
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EVC |
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2 |
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3 |
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Polarity |
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V. Ramp |
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Exist |
EV |
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VS IN |
1 |
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Check |
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Generator |
Check |
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20 |
HD |
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PV |
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Polarity |
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Exist |
Logic |
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CS IN |
4 |
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8 |
HD SEL |
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Check |
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Check |
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PH |
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23 |
VD |
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PHC |
5 |
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EH |
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EHC |
6 |
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Clamp |
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Pulse |
10 |
CLAMP |
VIDEO IN |
7 |
Sync |
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Generator |
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Sep |
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9 |
TIMING |
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Bias |
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19 |
18 |
17 |
16 15 |
21 |
22 |
14 |
11 |
24 |
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PV |
PH |
EV |
EH |
IN/EXT |
OUTV |
INV |
REFV |
GND |
VCC |
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(SDIP) |
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PVC |
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EVC |
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2 |
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3 |
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Polarity |
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V. Ramp |
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Exist |
EV |
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VS IN |
1 |
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Check |
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Generator |
Check |
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18 |
HD |
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PV |
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Polarity |
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Exist |
Logic |
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CS IN |
4 |
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8 |
HD SEL |
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Check |
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Check |
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PH |
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21 |
VD |
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PHC |
5 |
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EH |
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EHC |
6 |
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Clamp |
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Pulse |
10 |
CLAMP |
VIDEO IN |
7 |
Sync |
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Generator |
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Sep |
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9 |
TIMING |
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Bias |
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17 |
16 |
15 |
14 13 |
19 |
20 |
12 |
11 |
22 |
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PV |
PH |
EV |
EH |
IN/EXT |
OUTV |
INV |
REFV |
GND |
VCC |
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– 2 – |
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CXA1616N/S |
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Pin Description |
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(Ta = 25°C, VCC = 12V) |
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Pin No. |
Symbol |
Pin voltage |
Equivalent circuit |
Description |
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SDIP SSOP |
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VCC |
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Inputs the vertical separate sync. |
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200k |
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Inputs at TTL level and polarity is |
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1 |
1 |
VS IN |
— |
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positive/negative. |
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1k |
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8k |
V Low ≤ 0.5V |
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1 |
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V High ≥ 4.5V |
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20k |
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Connect a pull-down resistance of |
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8k |
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470kΩ or less to GND. |
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VCC |
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2 |
2 |
PVC |
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48k |
Connection pin of an integral capacitor |
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for the polarity discriminator circuit |
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(Polarity Check); connects a 0.22µF |
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0.3, 3.4V |
2 |
96k |
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capacitor to GND. |
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32k |
When the capacitor is connected at |
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1k |
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5 |
5 |
PHC |
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8k |
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positive polarity: 3.4V; |
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32k |
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negative polarity: 0.3V. |
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No input : 3.7V. |
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Vertical ramp waveform generator. |
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Generates a ramp waveform |
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synchronized to the input separate |
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sync frequency. Connects a 0.68µF |
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capacitor to GND. |
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VCC |
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The charging time constant (rising |
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edge) of ramp waveform is determined |
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5V |
48k |
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by the 2kΩ resistance and the external |
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2k |
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0.68µF capacitor, and the discharging |
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3 |
3 |
EVC |
4.3 to 7.9V |
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time constant (falling edge) by the |
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3 |
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external 0.68µF capacitor and the |
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8k |
32k |
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internal 17µA current. |
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When there is a verticai separate |
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17µA |
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sync, the voltage at Pin 3 rises |
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between 5.5 and 7.9V, existence |
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discrimination (Exist Check) is |
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performed, and an input signal is |
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judged to exist. |
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The voltage is 4.3V when no input |
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signal exists. |
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VCC |
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72k |
2k |
100µA |
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Inputs the composite and horizontal |
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4 |
4 |
CS IN |
4.2V |
200 |
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separate sync (positive/negative |
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4 |
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polarity). Amplitude is 1 to 5Vp-p. Input |
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400k |
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through a capacitor. |
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4V |
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– 3 –
CXA1616N/S
Pin No. |
Symbol |
Pin voltage |
Equivalent circuit |
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Description |
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SDIP SSOP |
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Connects a quasi-peak hold circuit |
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VCC |
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with a 33kΩ resistance and 0.22µF |
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capacitor to discriminate input signal |
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200 |
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20k |
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existence during composite sync input. |
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6 |
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8k |
When there is a composite sync, the |
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1k |
voltage is held by the quasi-peak hold |
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6 |
6 |
EHC |
3.0, 4.8V |
1k |
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circuit at 4.2 to 4.8V. This voltage is |
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3.8V |
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12k |
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then compared to a 3.8V reference |
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30µA |
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voltage, and an input signal is judged |
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16k |
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to exist. |
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The voltage is 3.0V when no input |
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signal exists. |
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Inputs the sync-on video (sync is |
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negative polarity). Connect a 0.47µF |
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capacitor and a 270Ω resistance in |
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VCC |
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series between the pin and its signal |
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source. |
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8.3V |
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4k |
5.8V |
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The slice level is determined by the |
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relationship between the sync |
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7 |
7 |
VIDEO IN |
4.5V |
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frequency and Pulse width and the |
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200 |
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sum of the 200Ω internal resistance |
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and the 270Ω external resistance |
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7 |
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multiplied by the 29µA current. |
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29µA |
16k |
72k |
V ≈29µA × (T2/T1) × (200 + 270) |
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V |
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T1 |
T2 |
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4.5V |
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Selects whether or not to output the |
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VD interval portion of HD (H Drive |
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200k |
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70k |
Pulse). |
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Input is at TTL Ievel. |
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8 |
8 |
HD SEL |
— |
1k |
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V Low ≤ 0.5V |
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V High ≥ 2.0V |
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Low level: The VD interval HD is not |
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output. |
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High level or open: The VD interval HD |
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is output as is. |
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VCC |
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100 |
10k |
Connect a desired capacitor and a |
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12kΩ resistance in parallel to GND. |
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9 |
9 |
TIMING |
10.5V |
9 |
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This capacitor changes the output |
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1k |
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pulse width of clamp pulse. |
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(See Fig. 1) |
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30µA |
17k |
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– 4 –
CXA1616N/S
Pin No.
Symbol Pin voltage |
Equivalent circuit |
Description |
SDIP SSOP
VCC 
56k
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2.7V |
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Clamp pulse output. |
10 |
10 |
CLAMP |
0.15V |
10 |
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10k |
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This is an open collector at positive |
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polarity. |
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5k |
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11 |
11 |
GND |
0V |
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— |
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GND |
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VCC |
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Reference for the vertical sync |
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1k |
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12 |
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separator circuit. |
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20 |
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1k |
) |
Connect an external resistance |
12 |
14 |
V REF |
— |
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( 14 |
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( 22 |
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between Vcc and GND to apply the |
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30µA |
16k |
36k |
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reference voltage. |
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Based on 4.4V. (See Fig. 2) |
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4.5V |
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13 |
15 |
IN/EXT |
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13 |
14 |
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20k |
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Outputs the polarity and existence |
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14 |
16 |
EH |
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15 |
16 |
17 |
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information of a sync signal. |
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15 |
17 |
EV |
0.12, 4.5V |
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8k |
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See "Description of Operation" for |
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16 |
18 |
PH |
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15 |
16 |
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their l/O matrix. |
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17 |
19 |
PV |
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18 |
19 |
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VCC |
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8k |
8k |
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HD (H Drive Pulse) output. |
18 |
20 |
HD |
0.15V |
18 |
8k |
This is an open collector at positive |
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( 20 ) |
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polarity. |
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10k |
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VCC |
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45k |
Outputs the sync signal separated |
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19 |
15k |
from the composite sync or sync-on |
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19 |
21 |
V OUT |
2.3V |
video for the vertical sync separator. |
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( 21 ) |
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60k |
Positive polarity output at an amplitude |
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2k |
of 2.3 to 6.0V. |
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– 5 –
CXA1616N/S
Pin No. |
Pin voltage |
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Equivalent circuit |
Description |
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Symbol |
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SDIP SSOP |
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Input for vertical sync separation |
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VCC |
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comparator. Connect an integrator |
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with a 3.9kΩ resistance and a 3300pF |
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1k |
1k |
12 capacitor between Pins 19 and 20. |
20 |
22 V IN |
— |
20 |
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( 14 ) The comparator operates when the |
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( 22 ) |
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voltage of the integrated sync signal at |
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30µA |
16k 36k |
the vertical interval becomes higher |
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than the voltage which lowers by VBE |
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(approximately 0.7V) from the voltage |
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at Pin 12. |
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VCC |
8k |
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8k |
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21 |
23 |
VD |
0.15V |
21 |
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8k |
VD (V Drive Pulse) output. |
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This is an open collector at positive |
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( 23 |
) |
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10k |
polarity. |
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22 |
24 VCC |
12V |
— |
Power supply. |
– 6 –
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