Philips CXA1616S, CXA1616N Datasheet

CXA1616N/S

Sync Discriminator for CRT Displays

Description

The CXA1616N/S automatically selects one of three types of sync signals – separate sync, composite sync, or sync-on video – to shape the waveform. It is ideally suited as a synchronous signal processor for auto tracking type displays.

Features

• Output of synchronous signal polarity information is

obtainable

• Supported polarities and amplitudes of input sig-

nals are as follows:

— V. separate sync

(positive/negative polarity, 1 to 5Vp-p For capacitor input 1.5 to 5Vp-p)

— H. separate sync

(positive/negative polarity, 1 to 5Vp-p)

— Composite sync

(positive/negative polarity, 1 to 5Vp-p)

— Sync-on video

(negative polarity sync level: 0.2 to 0.6Vp-p,

picture level: 0 to 2.1Vp-p)

CXA1616N

24 pin SSOP (Plastic)

CXA1616S

22 pin SDIP (Plastic)

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage Vcc 14 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation PD 900 mW

Operating Condition

Supply voltage Vcc 12 ± 0.5 V

Applications

CRT display monitors

Pin Configuration (Top View)

(SSOP) (SDIP)

1

VS IN

2

PVC

3

EVC

4

CS IN

5

PHC

6

EHC

GND

NC

7 8

9 10 11 12

VIDEO IN

HD SEL TIMING CLAMP

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

24 23 22 21 20 19 18 17 16 15 14 13

VCC VD V IN V OUT HD PV PH EV EH IN/EXT V REF NC

VS IN

PVC EVC

CS IN

PHC EHC

VIDEO IN

HD SEL TIMING CLAMP

GND

2 3 4 5 6 7 8

9 10 11

22 21 20 19 18 17 16 15 14 13 12

VCC VD V IN V OUT HD PV PH EV EH IN/EXT V REF

– 1 –

E92Y01C7Y-PS

Block Diagram

(SSOP)

CXA1616N/S

VS IN

CS IN

PHC

EHC

VIDEO IN

PVC

2

1

4

5

6

7

Polarity

Check

PV

Sync

Sep

19

18

PV

V. Ramp

Generator

17

EV

PH

3

16

EVC

Polarity

Check

PH

15

EH

IN/EXT

Check

21

V OUT

Exist

Check

22

V IN

Exist

14

EV

EH

V REF

Logic

Clamp

Pulse

Generator

Bias

11

24

GND

CC

V

20

8

23

10

9

HD

HD SEL VD

CLAMP

TIMING

(SDIP)

VS IN

CS IN

PHC

EHC

VIDEO IN

PVC

2

1

4

5

6

7

Polarity

Check

PV

Sync

Sep

17

16

PV

V. Ramp

Generator

15

EV

PH

3

14

EVC

Polarity

Check

PH

13

EH

IN/EXT

Check

19

V OUT

Exist

20

EV

Exist

Check

12

V IN

V REF

EH

Logic

Clamp

Pulse

Generator

Bias

11

22

GND

CC

V

18

21

10

9

8

HD

HD SEL VD

CLAMP

TIMING

– 2 –

CXA1616N/S

Pin Description (Ta = 25°C, VCC = 12V)

Pin No.

SSOPSDIP

1

2

5

3

Symbol

Pin voltage

Equivalent circuit

CC

V

200k

Description

Inputs the vertical separate sync. Inputs at TTL level and polarity is positive/negative.

1

VS IN

2

PVC

—

1k

1

20k

V

CC

8k

48k

V Low ≤ 0.5V

V High ≥ 4.5V Connect a pull-down resistance of 470kΩ or less to GND.

Connection pin of an integral capacitor for the polarity discriminator circuit (Polarity Check); connects a 0.22µF

0.3, 3.4V

5

PHC

2

1k

32k

96k

32k

8k

capacitor to GND. When the capacitor is connected at positive polarity: 3.4V; negative polarity: 0.3V. No input : 3.7V.

Vertical ramp waveform generator. Generates a ramp waveform synchronized to the input separate sync frequency. Connects a 0.68µF capacitor to GND.

VCC

5V

3

EVC

4.3 to 7.9V

3

48k

2k

The charging time constant (rising edge) of ramp waveform is determined by the 2kΩ resistance and the external

0.68µF capacitor, and the discharging time constant (falling edge) by the external 0.68µF capacitor and the

8k

32k

17µA

internal 17µA current. When there is a verticai separate sync, the voltage at Pin 3 rises between 5.5 and 7.9V, existence discrimination (Exist Check) is performed, and an input signal is judged to exist. The voltage is 4.3V when no input signal exists.

CC

V

72k

2k

100µA

Inputs the composite and horizontal

4

CS IN

4.2V

200

4

400k

separate sync (positive/negative polarity). Amplitude is 1 to 5Vp-p. Input through a capacitor.

4V

– 3 –

CXA1616N/S

Pin No.

SSOPSDIP

6

7

6

7

Symbol

EHC

VIDEO IN

Pin voltage

3.0, 4.8V

4.5V

Equivalent circuit

VCC

6

1k

3.8V

30µA

VCC

7

8.3V

200

29µA

200

4k

16k

1k

12k

5.8V

16k

20k

8k

72k

Description

Connects a quasi-peak hold circuit with a 33kΩ resistance and 0.22µF capacitor to discriminate input signal existence during composite sync input. When there is a composite sync, the voltage is held by the quasi-peak hold circuit at 4.2 to 4.8V. This voltage is then compared to a 3.8V reference voltage, and an input signal is judged to exist. The voltage is 3.0V when no input signal exists.

Inputs the sync-on video (sync is negative polarity). Connect a 0.47µF capacitor and a 270Ω resistance in series between the pin and its signal source. The slice level is determined by the relationship between the sync frequency and Pulse width and the sum of the 200Ω internal resistance and the 270Ω external resistance multiplied by the 29µA current. ∆V ≈ 29µA × (T2/T1) × (200 + 270)

∆V

T2T1

4.5V

Selects whether or not to output the VD interval portion of HD (H Drive

200k

70k

Pulse). Input is at TTL Ievel.

HD SEL

8

—

1k

8

V Low ≤ 0.5V

V High ≥ 2.0V Low level: The VD interval HD is not output. High level or open: The VD interval HD is output as is.

VCC

100

TIMING

9

10.5V

9

1k

10k

Connect a desired capacitor and a 12kΩ resistance in parallel to GND. This capacitor changes the output pulse width of clamp pulse. (See Fig. 1)

30µA

17k

– 4 –

CXA1616N/S

Pin No.

10

11

12

13 14 15 16 17

Symbol

Pin voltage

Equivalent circuit

Description

SSOPSDIP

V

10

CLAMP

0.15V

CC

10

10k

56k

2.7V

Clamp pulse output. This is an open collector at positive polarity.

5k

11

GND

0V

—

VCC

GND

Reference for the vertical sync

12

separator circuit. Connect an external resistance

( )

14

between Vcc and GND to apply the reference voltage. Based on 4.4V. (See Fig. 2)

Outputs the polarity and existence information of a sync signal.

8k

See "Description of Operation" for their l/O matrix.

14

15 16 17 18 19

V REF

IN/EXT EH EV PH PV

—

0.12, 4.5V

20

( )

22

13

15

17

16

18

30µA

14

16

1k

4.5V

17

19

16k

1k

36k

20k

18

19

20

21

HD

V OUT

0.15V

2.3V

VCC

18

( )

20

VCC

19

( )

21

8k 8k

8k

10k

45k

15k

60k

2k

HD (H Drive Pulse) output. This is an open collector at positive polarity.

Outputs the sync signal separated from the composite sync or sync-on video for the vertical sync separator. Positive polarity output at an amplitude of 2.3 to 6.0V.

– 5 –

CXA1616N/S

Pin No.

20

21

22

Symbol

Pin voltage

Equivalent circuit

Description

SSOPSDIP

Input for vertical sync separation

VCC

comparator. Connect an integrator with a 3.9kΩ resistance and a 3300pF

22

V IN

—

20

( )

22

1k

30µA

16k

36k

1k

12

( )

14

The comparator operates when the voltage of the integrated sync signal at the vertical interval becomes higher than the voltage which lowers by VBE

capacitor between Pins 19 and 20.

(approximately 0.7V) from the voltage at Pin 12.

23

24

VD

VCC

0.15V

12V

VCC

21

( )

23

8k 8k

8k

10k

—

VD (V Drive Pulse) output. This is an open collector at positive polarity.

Power supply.

– 6 –