Philips _chtcm20e_sm_166 Datasheet

Page 1
Colour TV Chassis
MG8
ME8
TCM2.0E
MG8
ME8
Contents Page Contents Page
1. Technical Specifications, Connections, and Chassis Overview 2
2. Safety Instructions, Warnings, and Notes 5
3. Directions for Use 6
4. Mechanical Instructions 7
5. Service Modes, Error Codes, and Fault Finding 12
6. Block Diagrams, Test Point Overview, and
Waveforms
Wiring Diagram Of Connector 19", 20", and 22" 19 Wiring Diagram Of Connector 26" 19 Block Diagram MT5335 20
7. Circuit Diagrams and PWB Layouts Diagram PWB Main Power Supply (20") (A)21 22 Main Power Supply (26") (A1)23 25 Standby Power Supply (26") (A2)24 26 SSB: Tuner (B01)27 46-47 SSB: MCU Standby (B02)28 46-47 SSB: DC / DC (B03)29 46-47 SSB: Digital Channel Decoder (B04)30 46-47 SSB: DVBT/ CI Decoder (B05)31 46-47 SSB: Audio Amplifier (B06)32 46-47 SSB: MT5335 Video Processor (B07)33 46-47 SSB: MT5335 Interface USB/HDMI (B08)34 46-47 SSB: Interface LVDS TTL (B09)35 46-47 SSB: Flash Memory (B10)36 46-47 SSB: SDRAM (B11)37 46-47 SSB: MT5335 Interface VGA (B12)38 46-47 SSB: D/A Converter (B13)39 46-47 SSB: HDMI Switch (B14)40 46-47 SSB: I/O Scart (B15)41 46-47 SSB: I/O Side AV, S-Video, Audio (B16)42 46-47 SSB: MT5335 Interface YPbPr & VGA (B17)43 46-47 SSB: I/O VGA (B17)44 46-47 SSB: LVDS Receiver (B18)45 46-47
©
Copyright 2008 Koninklijke Philips Electronics N.V. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted, in any form or by any means, electronic, mechanical, photocopying, or otherwise without the prior permission of Philips.
Keyboard Control Panel (E)48 48 Inverter Panel (I)49 50 IR LED Panel (J)51 51
8. Alignments 53
9. Circuit Descriptions, Abbreviation List, and IC Data Sheets 54 Abbreviation List 55 IC Data Sheets 58
10. Spare Parts List & CTN Overview 66
11. Revision List 66
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Published by JY 0871 BU TV Consumer Care Printed in the Netherlands Subject to modification EN 3122 785 17952
Page 2
EN 2 TCM2.0E LA1.
Technical Specifications, Connections, and Chassis Overview

1. Technical Specifications, Connections, and Chassis Overview

Index of this chapter:

1.1 Technical Specifications

1.2 Connection Overview
1.3 Chassis Overview
Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).
1.1 Technical Specifications

1.1.1 Vision

Display type : LCD Screen size : 19" (48 cm), 16:9
: 20" (51 cm), 4:3 : 22" (56 cm), 16:9 : 26" (66 cm), 16:9
Resolution (H × V pixels) : 640×480 (20")
2
Light output (cd/m
Contrast ratio : 800:1 (20", 26")
Typ. response time (ms) : 12 (20")
Viewing angle (H × V degrees) : 178×178 (20")
Tuning system : PLL Colour systems : PAL, SECAM Video playback : PAL, SECAM, NTSC Tuner bands : UHF, VHF, S, Hyper
) : 300 (19", 20", 22")
: 1366×768 (26") : 1440×900 (19") : 1680×1050 (22")
: 500 (26")
: 1000:1 (19", 22")
: 8 (26") : 5 (19", 22")
: 170×160 (19", 22") : 160×160 (26")

1.1.3 Miscellaneous

Power supply
- Mains voltage (V
- Mains frequency (Hz) : 50, 60 Power consumption (W) : ~50 (19")
Stand-by (W) : < 0.3 Dimensions (W × H × D in mm) : 475 × 334 × 71 (19")
Weight (kg) : ? (19")
) : 100 to 240
AC
: ~58 (20") : ~53 (22") : ~120 (26")
: 470 × 406 × 71 (20") : 538 × 375 × 71 (22") : 671 × 458 × 90 (26")
: 5.8 (20") : ? (22") : 7.7 (26")
Supported Computer Formats 60 Hz : 640×480(max.for 20") 60 Hz : 800×600 (all exc.20") 60 Hz : 1024×768(all exc.20") 60 Hz : 1280×768 (26" only) 60 Hz : 1280×1024 (26" only) 60 Hz : 1366×768 (26" only) 50 Hz, 75 Hz : 1440×900 (26", only)
Supported Video Formats 60 Hz : 480i 60 Hz : 480p 50 Hz : 576i 50 Hz : 576p 50 Hz, 60 Hz : 720p 50 Hz, 60 Hz : 1080i 50 Hz, 60 Hz : 1080p (19", 22" only)

1.1.2 Sound

Sound systems : Mono
:Stereo
Maximum power (W) : 2 × 3 (19", 20")
:2 × 5 (22", 26")
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Technical Specifications, Connections, and Chassis Overview

1.2 Connection Overview

EN 3TCM2.0E LA 1.
COMMON INTERFACE
HDMI 1
HDMI 2 VGA PC EXT 1
Note: The following connector colour abbreviations are used
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Grey, Rd= Red, Wh= White, and Ye= Yellow.

1.2.1 Side connections

EXT 2: Cinch: Video CVBS - In, Audio - In
Ye - Video CVBS 1 V Wh - Audio L 0.5 V Rd - Audio R 0.5 V
/ 75 ohm jq
PP
/ 10 kohm jq
RMS
/ 10 kohm jq
RMS
EXT 2: S-Video (Hosiden): Video Y/C - In
1 -Ground Y Gnd H 2 -Ground C Gnd H 3 -Video Y 1 V 4 -Video C 0.3 V
/ 75 ohm j
PP
P / 75 ohm j
PP
EXT 2: Mini Jack: Audio Head phone - Out
Bk - Head phone 32 - 600 ohm / 10 mW ot
EXT 2: Common Interface
68p - See diagram B05 jk

1.2.2 Rear Connections

USB2.0
EXT 3
YPrPb
VGA
LR
AUDIO SPDIF

Figure 1-1 Rear and side I/O connections

1 -D2+ Data channel j 2 -Shield Gnd H 3 -D2- Data channel j 4 -D1+ Data channel j 5 -Shield Gnd H 6 -D1- Data channel j 7 -D0+ Data channel j 8 -Shield Gnd H 9 -D0- Data channel j 10 - CLK+ Data channel j 11 - Shield Gnd H 12 - CLK- Data channel j 13 - n.c. 14 - n.c. 15 - DDC_SCL DDC clock j 16 - DDC_SDA DDC data jk 17 - Ground Gnd H 18 - +5V j 19 - HPD Hot Plug Detect j 20 - Ground Gnd H
VGA PC: Video RGB - In and Service UART
S-VIDEO
TV (75Ω)
1
6
11
L AUDIO R
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5
CVBS
EXT 2
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10
15
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Figure 1-4 VGA Connector
1 2 3 4
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Figure 1-2 USB (type A)
1-+5V k 2 -Data (-) jk 3 -Data (+) jk 4 -Ground Gnd H
HDMI 1 & 2: Digital Video, Digital Audio - In
19
18 2
1
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Figure 1-3 HDMI (type A) connector
1 -Video Red 0.7 V 2 -Video Green 0.7 V 3 -Video Blue 0.7 V
/ 75 ohm j
PP
/ 75 ohm j
PP
/ 75 ohm j
PP
4-n.c. 5 -Ground Gnd H 6 -Ground Red Gnd H 7 -Ground Green Gnd H 8 -Ground Blue Gnd H 9 -+5V_dc +5 V j 10 - Ground Sync Gnd H 11 - n.c. 12 - DDC_SDA DDC data j 13 - H-sync 0 - 5 V j 14 - V-sync 0 - 5 V j 15 - DDC_SCL DDC clock j
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EN 4 TCM2.0E LA1.
Technical Specifications, Connections, and Chassis Overview
EXT 3: Cinch: Video YPbPr - In, Audio - In
Gn - Video Y 1 V Bu - Video Pb 0.7 V Rd - Video Pr 0.7 V Wh - Audio L 0.5 V Rd - Audio R 0.5 V
EXT 3: Mini Jack: VGA Audio - In
Bk - Audio L/R 0.5 V
EXT 1: Video RGB/YC - In, CVBS - In/Out, Audio - In/Out
20
21
Figure 1-5 SCART connector
1 -Audio R 0.5 V 2 -Audio R 0.5 V 3 -Audio L 0.5 V 4 -Ground Audio Gnd H
/ 75 ohm jq
PP
/ 75 ohm jq
PP
/ 75 ohm jq
PP
/ 10 kohm jq
RMS
/ 10 kohm jq
RMS
/ 10 kohm jq
RMS
2
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RMS
RMS
RMS
1
050404
/ 1 kohm k / 10 kohm j / 1 kohm k

1.3 Chassis Overview

5 -Ground Blue Gnd H 6 -Audio L 0.5 V 7 -Video Blue/C-out 0.7 V 8 -Function Select 0 - 2 V: INT
4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3 j 9 - Ground Green Gnd H 10 - Easylink P50 0 - 5 V / 4.7 kohm jk 11 - Video Green 0.7 V 12 - n.c. 13 - Ground Red Gnd H 14 - Ground P50 Gnd H 15 - Video Red/C 0.7 V 16 - Status/FBL 0 - 0.4 V: INT
1 - 3 V: EXT / 75 ohm j 17 - Ground Video Gnd H 18 - Ground FBL Gnd H 19 - Video CVBS 1 V 20 - Video CVBS/Y 1 V 21 - Shield Gnd H
Aerial - In
- - IEC-type (EU) Coax, 75 ohm D
Cinch: S/PDIF - Out
Bk - Coaxial 0.4 - 0.6V
/ 10 kohm j
RMS
/ 75 ohm jk
PP
/ 75 ohm j
PP
/ 75 ohm j
PP
/ 75 ohm k
PP
/ 75 ohm j
PP
/ 75 ohm kq
PP
SMALL SIGNAL BOARD
B
A(1)
MAIN POWER SUPPLY

Figure 1-6 PWB/CBA locations (26" model)

INVERTER PANEL
(OPTONAL)
KEYBOARD
CONTROL PANEL
STANDBY POWER
SUPPLY UNIT
(OPTIONAL)
IR LED PANEL
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Safety Instructions, Warnings, and Notes

2. Safety Instructions, Warnings, and Notes

EN 5TCM2.0E LA 2.
Index of this chapter:

2.1 Safety Instructions

2.2 Warnings

2.3 Notes

2.1 Safety Instructions
Safety regulations require the following during a repair:
• Connect the set to the Mains/AC Power via an isolation transformer (> 800 VA).
• Replace safety components, indicated by the symbol h, only by components identical to the original ones. Any other component substitution (other than original type) may increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, the set must be returned in its original condition. Pay in particular attention to the following points:
• Route the wire trees correctly and fix them with the mounted cable clamps.
• Check the insulation of the Mains/AC Power lead for external damage.
• Check the strain relief of the Mains/AC Power cord for proper function.
• Check the electrical DC resistance between the Mains/AC Power plug and the secondary side (only for sets that have a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the “on” position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the tuner or the aerial connection on the set. The reading should be between 4.5 MΩ and 12 MΩ.
4. Switch “off” the set, and remove the wire between the
two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to prevent touching of any inner parts by the customer.
2.2 Warnings
• All ICs and many other semiconductors are susceptible to electrostatic discharges (ESD w). Careless handling during repair can reduce life drastically. Make sure that, during repair, you are connected with the same potential as the mass of the set by a wristband with resistance. Keep components and tools also at this same potential.
• Be careful during measurements in the high voltage section.
• Never replace modules or other components while the unit is switched “on”.
• When you align the set, use plastic rather than metal tools. This will prevent any short circuits and the danger of a circuit becoming unstable.
2.3 Notes

2.3.1 General

• Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode (see chapter 5) with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and picture carrier at 475.25 MHz for PAL, or
61.25 MHz for NTSC (channel 3).
• Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the voltages in the power supply section both in normal operation (G) and in stand-by (F). These values are indicated by means of the appropriate symbols.

2.3.2 Schematic Notes

• All resistor values are in ohms, and the value multiplier is often used to indicate the decimal point location (e.g. 2K2 indicates 2.2 kΩ).
• Resistor values with no multiplier may be indicated with either an “E” or an “R” (e.g. 220E or 220R indicates 220 Ω).
• All capacitor values are given in micro-farads (μ=× 10 nano-farads (n =× 10
• Capacitor values may also use the value multiplier as the decimal point indication (e.g. 2p2 indicates 2.2 pF).
• An “asterisk” (*) indicates component usage varies. Refer to the diversity tables for the correct values.
• The correct component values are listed in the Spare Parts List. Therefore, always check this list when there is any doubt.

2.3.3 BGA (Ball Grid Array) ICs

Introduction
For more information on how to handle BGA devices, visit this URL: www.atyourservice.ce.philips.com (needs subscription, not available for all regions). After login, select “Magazine”, then go to “Repair downloads”. Here you will find Information on how to deal with BGA-ICs.
BGA Temperature Profiles
For BGA-ICs, you must use the correct temperature-profile, which is coupled to the 12NC. For an overview of these profiles, visit the website www.atyourservice.ce.philips.com (needs subscription, but is not available for all regions) You will find this and more technical information within the “Magazine”, chapter “Repair downloads”. For additional questions please contact your local repair help desk.

2.3.4 Lead-free Soldering

Due to lead-free technology some rules have to be respected by the workshop during a repair:
• Use only lead-free soldering tin Philips SAC305 with order code 0622 149 00106. If lead-free solder paste is required, please contact the manufacturer of your soldering equipment. In general, use of solder paste within workshops should be avoided because paste is not easy to store and to handle.
• Use only adequate solder tools applicable for lead-free soldering tin. The solder tool must be able: – To reach a solder-tip temperature of at least 400°C. – To stabilize the adjusted temperature at the solder-tip. – To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature of around 360°C - 380°C is reached and stabilized at the solder joint. Heating time of the solder-joint should not exceed ~ 4 sec. Avoid temperatures above 400°C, otherwise wear-out of tips will increase drastically and flux-fluid will be destroyed. To avoid wear-out of tips, switch “off” unused equipment or reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering tin/parts is possible but PHILIPS recommends strongly to avoid mixed regimes. If this cannot be avoided, carefully clear the solder-joint from old tin and re-solder with new tin.
-9
), or pico-farads (p =× 10
-12
-6
),
).
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EN 6 TCM2.0E LA3.

2.3.5 Alternative BOM identification

It should be noted that on the European Service website,
“Alternative BOM” is referred to as “Design variant”.
The third digit in the serial number (example: AG2B0335000001) indicates the number of the alternative B.O.M. (Bill Of Materials) that has been used for producing the specific TV set. In general, it is possible that the same TV model on the market is produced with e.g. two different types of displays, coming from two different suppliers. This will then result in sets which have the same CTN (Commercial Type Number; e.g. 28PW9515/12) but which have a different B.O.M. number. By looking at the third digit of the serial number, one can identify which B.O.M. is used for the TV set he is working with. If the third digit of the serial number contains the number “1” (example: AG1B033500001), then the TV set has been manufactured according to B.O.M. number 1. If the third digit is a “2” (example: AG2B0335000001), then the set has been produced according to B.O.M. no. 2. This is important for
ordering the correct spare parts!
For the third digit, the numbers 1...9 and the characters A...Z can be used, so in total: 9 plus 26= 35 different B.O.M.s can be indicated by the third digit of the serial number.
Identification: The bottom line of a type plate gives a 14-digit serial number. Digits 1 and 2 refer to the production centre (e.g. AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers to the Service version change code, digits 5 and 6 refer to the production year, and digits 7 and 8 refer to production week (in example below it is 2006 week 17). The 6 last digits contain the serial number.
Directions for Use
MODEL :
PROD.NO:

2.3.6 Board Level Repair (BLR) or Component Level Repair (CLR)

If a board is defective, consult your repair procedure to decide if the board has to be exchanged or if it should be repaired on component level. If your repair procedure says the board should be exchanged completely, do not solder on the defective board. Otherwise, it cannot be returned to the O.E.M. supplier for back charging!

2.3.7 Practical Service Precautions

• It makes sense to avoid exposure to electrical shock.
• Always respect voltages. While some may not be
32PF9968/10
AG 1A0617 000001
Figure 2-1 Serial number (example)
While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard.
dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.
MADE IN BELGIUM
220-240V 50/60Hz
~
VHF+S+H+UHF
BJ3.0E LA
S
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128W
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3. Directions for Use

You can download this information from the following websites:
http://www.philips.com/support http://www.p4c.philips.com
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4. Mechanical Instructions

Mechanical Instructions
EN 7TCM2.0E LA 4.
Index of this chapter:

4.1 Cable Dressing

4.2 Service Positions
4.3 Assy/Panel Removal
4.4 Set Re-assembly
4.1 Cable Dressing
Notes:
• Figures below can deviate slightly from the actual situation, due to the different set executions.
• Follow the disassemble instructions in described order. They apply mostly to the 26" model unless otherwise specified, but the described method is comparable for the other screen sizes.

Figure 4-1 Cable dressing (20" model)

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EN 8 TCM2.0E LA4.
Mechanical Instructions

4.2 Service Positions

For easy servicing of this set, there are a few possibilities created:
• The buffers from the packaging.
• Foam bars (created for Service).

4.2.1 Foam Bars

1
Required for sets
1
42"
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Figure 4-2 Cable dressing (26" model)

The foam bars (order code 3122 785 90580 for two pieces) can be used for all types and sizes of Flat TVs. See figure “Foam bars” for details. Sets with a display of 42” and larger, require four foam bars [1]. Ensure that the foam bars are always supporting the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! By laying the TV face down on the (ESD protective) foam bars, a stable situation is created to perform measurements and alignments. By placing a mirror under the TV, you can monitor the screen.
Figure 4-3 Foam bars
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4.3 Assy/Panel Removal

4.3.1 Stand

1. Refer to next figure.
2. Place the TV set upside down on a table top, using the foam bars (see section “Service Position”).
3. Remove the screws that secure the stand and remove the stand.
Mechanical Instructions
EN 9TCM2.0E LA 4.
1
1
Figure 4-4 Stand

4.3.2 Rear Cover

Warning: Disconnect the mains power cord before you remove
the rear cover.
1. Refer to next figures.
2. Place the TV set upside down on a table top, using the foam bars (see section “Service Positions”).
3. Remove the screws that secure the rear cover. The screws are located at the sides. Be careful: Some models (mainly the smaller screen sizes) use latches for securing the rear and front cover together (see figure “Front cover latch location”). These
must be unlocked first before you can open the TV-set!
To open them, use e.g. a (plastic) putty knife. Insert the tool into the gap between the front and rear cover (be extremely careful not to scratch or dent the cabinet when inserting the tool). Gently release the internal latches. Note: You will hear little popping sounds as the latches release and the rear cover moves away from the front cover.
4. Now the rear cover could be lifted but the SSB and power supply panel(s) are mounted in the rear cover and still connected to the LCD panel and other boards. Those
cables should be released first!
5. To release the LVDS cable lift the back cover a few centimetres and move it downwards the set. Now unplug the LVDS connector [2]. Caution: be careful, as this is a very fragile connector!
6. Remove the screw [3].
7. Now the rear cover can be lifted to gain access to the speaker cables and the IR/LED panel cable. Release the connectors [4].
1
1
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Figure 4-5 Front cover latch location [1/2]
Side
Side
Top
Figure 4-6 Front cover latch location [2/2]
2
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3
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Figure 4-7 LVDS release
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EN 10 TCM2.0E LA4.
Mechanical Instructions
4
Figure 4-8 Speaker and IR/LED panel cable release

4.3.3 Keyboard Control Board

1. Refer to next figure.
2. Unscrew two screws[1]
3. Unplug connector [2] and remove the board. When defective, replace the whole unit
1
4
4
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22 22
1 1
Figure 4-10 IR/LED Board and Speakers

4.3.5 Power Supply Board

Due to different set executions this chassis is supplied with one or two power supply boards and figures may differ. Caution: it is absolutely mandatory to remount all different screws and cables at their original position during re-assembly. Failure to do so may result in damaging the power supply.
1. Refer to next figure.
2. Unplug all the connectors [1].
3. Remove the fixation screws [2]
4. Remove the main power supply board.
5. Unplug all the connectors [3].
6. Remove the fixation screws [4]
7. Remove the stand-by power supply board.
2
2
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2
1
Figure 4-9 Keyboard control board

4.3.4 IR/LED Board and Speakers

1. Refer to next figure.
2. Remove the screws [1] and remove the IR/LED board.
3. Remove the screws [2] and remove the speakers. When defective, replace the whole unit.
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1
1
2
2
Figure 4-11 Power Supply Unit(s)
4
4
3
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4
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4.3.6 Inverter Board (19", 20", and 22" versions)

Due to different set executions this chassis some versions are supplied with an inverter board. Figures may differ.
1. Refer to next figure.
2. Unplug all connectors [1].
3. Release the clips [2]
4. Take out the inverter board.
Mechanical Instructions
2
EN 11TCM2.0E LA 4.
2
4
4
3
2
1
2
Figure 4-12 Inverter Board
1
1
2
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2
Figure 4-14 SSB

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse order.
Notes:
• While re-assembling, make sure that all cables are placed and connected in their original position. See figure “Cable dressing”.
• Pay special attention not to damage the EMC foams at the SB shields. Make sure, that EMC foams are put correctly on their places.
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4.3.7 Small Signal Board (SSB)

Caution: it is absolutely mandatory to remount all different
screws at their original position during re-assembly. Failure to do so may result in damaging the SSB.
Removing the SSB
1. See next figures.
2. Remove the screws [1] from the SSB connector plate.
3. Remove the screws [2] from the SSB.
4. On the outside of the set, lift the rear cover near the tuner connector approximately 3 mm in the indicated direction and keep it lifted, while
5. On the inside of the set, slide the metal plate in the indicated direction.
6. Gently lift the board from the rear cover.
7. Now unplug the LVDS connector [3]. Caution: be careful, as this is a very fragile connector! Unplug the rest of the cables [4].
1 1
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Figure 4-13 SSB connector plate
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EN 12 TCM2.0E LA5.
Service Modes, Error Codes, and Fault Finding

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter:

5.1 Test Points

5.2 Service Modes

5.3 Error Codes
5.5 Service Tools
5.1 Test Points
This chassis is NOT equipped with test points in the service printing. No test points are mentioned in the service manual.
5.2 Service Modes
The Service Mode feature is split into different parts:
• Service Alignment Mode (SAM).
• Service Default Mode (SDM).
• Customer Service Mode (CSM).
SDM and SAM offer features, which can be used by the Service engineer to repair/align a TV set. Some features are:
• Activates the blinking LED procedure for error identification when no picture is available (SDM).
• Make alignments (e.g. white tone), (de)select options, enter options codes, reset the error buffer (SAM).
• Display information (“SAM” indication in upper right corner of screen, error buffer, software version, options and option codes, sub menus).
The CSM is a Service Mode that can be enabled by the consumer. The CSM displays diagnosis information, which the customer can forward to the dealer or call centre. In CSM mode, “CSM”, is displayed in the top right corner of the screen. The information provided in CSM and the purpose of CSM is to:
• Increase the home repair hit rate.
• Decrease the number of nuisance calls.
• Solved customers' problem without home visit.

5.2.1 Service Alignment Mode (SAM)

How to Enter
To enter SAM, use the following method:
• Press on the remote control the code “062596” directly followed by the “INFO” key.
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Figure 5-2 SAM menu, Clear
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Figure 5-3 SAM menu, RGB Align
050808
050808
After entering SAM, the following screen is visible, the values can be adjusted according to the requested (see Chapter 8).
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050808
Figure 5-1 SAM menu, System Information
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Figure 5-4 SAM menu, NVM Editor
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Figure 5-5 SAM menu, NVM Update
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Service Modes, Error Codes, and Fault Finding
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Figure 5-6 SAM menu, Clear OAD
EN 13TCM2.0E LA 5.
How to Activate CSM
Key in the code “123654” via the standard RC transmitter.
Contents of CSM
050808
How to EXIT
Put set in <stand-by> by using the remote control.

5.2.2 Service Default Mode (SDM)

Purpose
• To create a pre-defined setting, to get the same measurements as given in this manual.
• To override SW protections.
• To start the blinking LED procedure.
How to enter
To enter SAM, use the following method:
• Press on the remote control the code “062596” directly followed by the “MENU” key.
After entering SDM, the following screen is visible.
I_17950_043.eps
Figure 5-7 SDM menu
From top to bottom, it gives the following information:
• Operation hours
• Software version
• Error buffer display.
080508
I_17950_044.eps
080508
Figure 5-8 CSM Menu -1-
I_17950_045.eps
080508
Figure 5-9 CSM Menu -2-
Menu Explanation
1. Model Number. Type number and region.
2. Production Serial Number. Product serial no.
3. SW Version. Software cluster and version is displayed (TC = TCL, M2 = MTK2, E = Europe, 0.49 = software version).
4. Codes. Error buffer contents.
5. SSB. SSB serial number.
6. DISPLAY. Display type.
7. NVM Version. NVM version.
8. Key (HDCP) HDMI. Shows valid or invalid HDCP key when HDMI connected. Else blank.
9. Digital Signal Quality. Quality of antenna signal in %.
10. Audio System. Audio system (Mono/Stereo/NICAM)
11. n.a.
12. Video Format. Video format.
13. Stand-by μP SW ID. SW version Stand-by microprocessor.

5.2.3 Customer Service Mode (CSM)

Purpose
When a customer is having problems with his TV-set, he can call his dealer or the Customer Help desk. The service technician can then ask the customer to activate the CSM, in order to identify the status of the set. Now, the service technician can judge the severity of the complaint. In many cases, he can advise the customer how to solve the problem, or he can decide if it is necessary to visit the customer. The CSM is a read only mode; therefore, modifications in this mode are not possible.
How to exit
Press “MENU” on the RC-transmitter.
Page 14
EN 14 TCM2.0E LA5.
Service Modes, Error Codes, and Fault Finding

5.2.4 Blinking LED Procedure

The software is capable of identifying different kinds of errors. Because it is possible that more than one error can occur over time, an error buffer is available which is capable of storing the last five errors that occurred. This is useful if the OSD is not working properly.
Errors can also be displayed by the blinking LED procedure. The method is to repeatedly let the front LED pulse with as many pulses as the error code number, followed by a period of
1.5 seconds in which the LED is “off”. Then this sequence is repeated. Any RC command terminates the sequence. Error code LED blinking is in white colour.
Example: the contents of the error buffer is “013 007 000 000 000”. After entering SDM, the following occurs:
• 1 long blink of 5 seconds to start the sequence
• 1 medium blink of 3 seconds and then 3 short blinks followed by a pause of 1.5 seconds
• 7 short blinks followed by a pause of 1.5 seconds
• 1 long blink of 1.5 seconds to finish the sequence.
The sequence starts again with 12 short blinks.

5.4 Fault Finding

5.3 Error Codes

The error code buffer contains all errors detected since the last time the buffer was erased. The buffer is written from left to right. When an error occurs that is not yet in the error code buffer, it is displayed at the left side and all other errors shift one position to the right.
Basically there are six kind of errors:
Code Description Detection method Type
0 no error
3 μP Control I
4 General I
bus Error
7 Tuner I
8 Demodulator I
10 MT8295 I
13 HDMI switch I
2
C-bus Error log +
2
C
I2C-bus Protection +
2
C-bus Error log +
2
C-bus Error log +
2
C-bus Error log +
2
C-bus Error log +
blinking in SDM
spontaneous
blinking in SDM
blinking in SDM
blinking in SDM
blinking in SDM
No Picture, no sound, no Black light, Fuse Broken
For P804 ,Pin 8~11
is 12V& Pin2~3 of
is 5v
, OK?
NO NO
Check PSU
YES YES
For Q800,pin5~6
of is 5V & pin7~8
is12V , OK?
Check Pin 10 Of
U810. is it 3.3v?
Is
U800~U808&U2
01 OK?
NO
Replace the bad
one of
u800~u808&U201
YES
Check
LQFP jointing of
U203
Check
X200,C221,C222,C
23,L214 & IIC Bus
Check jointing of
U204,R271~R288,R
248~R260.
YES
YES

Figure 5-10 No picture, no sound, no backlight, fuse broken (19", 20", and 22" sets)

I_17950_009.eps
080508
Page 15
Service Modes, Error Codes, and Fault Finding
EN 15TCM2.0E LA 5.
No Picture, no sound, no Black light, Fuse Broken
Pin 8~11 of P804 is
12V, OK?
NO NO
Pin2~3 of P804 is 5v&Pin 1 is 5v,OK?
YES
Check Main
Check sub PSU
PSU
YES YES
pin4~5 is 5V &
pin7~8 is12V of
U505 OK?
U800~U808&U2
Is
01 OK?
NO
Check Pin 4 Of
UM01 is 3.3v
NO
Replace the
bad one of
u800~u808&U2
01
for standby

Figure 5-11 No Picture, no sound, no backlight, fuse broken (26" sets)

YES
Check
LQFP jointing of
U203
YES
Check X200,C221,C222,C 23,L214 & IIC Bus
YES
Check jointing of U204,R271~R288
,R248~R260.
I_17950_010.eps
080508
No Picture, Black light & Sound OK
Check the
output voltage
of Q203. is it
OK?
Yes
Check
waveform of
L200~L209 is
OK?
No
Is
Pin220,229,238
of U203 shorted
to earth?
No
Yes
No
Check the voltage of
C of Q204.
check the
cable to panel
check Pin
221~228&Pin
230~242 of U203
Yes
Replace Q203
I_17950_011.eps
080508

Figure 5-12 No Picture, Backlight & Sound OK

Page 16
EN 16 TCM2.0E LA5.
Service Modes, Error Codes, and Fault Finding
Picture OK, No sound
Check the voltage of
No
Pin 3,13 of u600,is it 12v?
Yes
Check stby
Pin 7 & Mute Pin6 of U600,is it OK?
Yes
Check the wave of
pin186,185 of
U203,is it OK?
No
TV source
Yes
No
R & L speaker
Check the wave
of Pin of source
input,such as
pin170~177.
Yes
Check IF circuit
or Replace
Replace
U100

Figure 5-13 Picture OK, No sound

Check Q800
Check
u203
NO
Yes
Check C of Q602 is
5V,B of Q602 is Low
OK?
Yes
Check
Pin 7 of U600 is
6V
No
Check
the input circuit
No
NO
Change the
damage
component
Replace U600
I_17950_012.eps
080508
Colour system is
Right & another
channel colour is
right ?
No
Reset
To
Local system
Yes
No colour
Dose the TV
signal too weak?
YES
Check
Tuner Input
cable & antenna

Figure 5-14 No colour

NO
Check
Pin 17 of U100
OK?
YES
Check E2PROM
U205
YES
Fine Frequency
NO
Check
U100
I_17950_013.eps
080508
Page 17
Service Modes, Error Codes, and Fault Finding

5.5 Service Tools

5.5.1 ComPair

Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips Consumer Electronics products. and offers the following:
1. ComPair helps you to quickly get an understanding on how to repair the chassis in a short and effective way.
2. ComPair allows very detailed diagnostics and is therefore capable of accurately indicating problem areas. You do not have to know anything about I yourself, because ComPair takes care of this.
3. ComPair speeds up the repair time since it can automatically communicate with the chassis (when the uP is working) and all repair information is directly available.
4. ComPair features TV software upgrade possibilities.
Specifications
ComPair consists of a Windows based fault finding program and an interface box between PC and the (defective) product. The (new) ComPair II interface box is connected to the PC via an USB cable. For the TV chassis, the ComPair interface box and the TV communicate via a bi-directional cable via the service connector(s).
2
C or UART commands
EN 17TCM2.0E LA 5.
How to Connect
This is described in the ComPair chassis fault finding database.
TO TV
UART SERVICE
CONNECTOR
2
I
C
TO
RS232 /UART
ComPair II
RC in
Optional
Switch
Power ModeLink/
Activity
UART SERVICE
CONNECTOR
RC out
TO
TO
I2C SERVICE
CONNECTOR
Multi
function
PC
ComPair II Developed by Philips Brugge
Optional power
HDMI
2
I
C only
5V DC
E_06532_036.eps
150208
Figure 5-15 ComPair II interface connection
Caution: It is compulsory to connect the TV to the PC as
shown in the picture above (with the ComPair interface in between), as the ComPair interface acts as a level shifter. If one connects the TV directly to the PC (via UART), ICs will be blown!
How to Order
ComPair II order codes:
• ComPair II interface: 312278591020.
• For latest software see Philips Service website.
• ComPair UART interface cable: 312278591070.
Note: If you encounter any problems, contact your local support desk.
Page 18
EN 18 TCM2.0E LA5.
Service Modes, Error Codes, and Fault Finding

5.6 Software Upgrading

5.6.1 Introduction

Software upgrading can be done by ComPair but this feature is a back up solution in case the normal procedure via USB does not work. Please use the USB upgrade method first. When the software is programmed via USB, you need the UPGRADE.PKG file on the USB stick. This file is available for customers on the Consumer Care website. When the software is programmed via ComPair, you need a *.BIN file. This file is only available for service workshops on the Servicer Network Support website.
The software upgrade feature does only work with the ComPairII interface.
A newer version of software is
detected.
Do you want to upgrade?
YES NO
layout 1
An equal/older version of software is
detected.
Do you want to proceed?
Note: Should be done on ly if
necessary.
YES NO
layout 2

5.6.2 Main Software Upgrade

In “normal” conditions, so when there is no major problem with the TV, the main software and the default software upgrade application can be upgraded with the “upgrade.pkg”. This software can be downloaded (as ZIP file) from the Philips Service website (an account is required). If named otherwise, rename the unzipped file always to “upgrade.pkg“.
How to upgrade:
1. Copy the “upgrade.pkg” file to the root of your USB stick.
2. Insert the USB stick in the USB connector on the TV while the TV is in “on” mode. The set will restart, and the upgrading will start automatically (see flowchart below). As soon as the programming is finished, you will get the message that you can remove your USB stick and restart the TV-set.
User software upgrade flow chart
Power off the set
Plug-in th e USB
stick
Power- on the set
Kindly remove the USB stick and
restart the set.
layout 3
Software update failed!
Would you like to try again?
YES NO
layout 4
Prompt user to
remove USB
and restart the
set
See layout 3
‘break-in’ and
check autorun fi le
Valid auto-r un
sw newer than
Prompt user to
See layout 1
N
Set re-start &
Proceed with sw
Y
Detect USB
file?
Y
Is USB sw
version > set
sw?
Y
Display USB
the TV sw.
confirm
Proceed?
Y
upgrade
Successful?
N
N
N
See layout 4
Is USB sw
version =< set
sw?
Y
Display USB
sw equal/older
than TV sw.
Prompt user to
confirm
See layout 2
Display
upgrade
progress
Prompt user to
try again?
N
End
End
N
Retry?
Figure 5-16 SW upgrade flowchart
Y
I_17920_046.eps
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Page 19
Block Diagrams, Test Point Overview, and Waveforms
_
_
19TCM2.0E LA 6.

6. Block Diagrams, Test Point Overview, and Waveforms

Wiring Diagram Of Connector 19", 20", and 22"

P800
1 2 3 4 5 6
40-LDMK35-MAE2XG
7
MAIN BOARD
P805
5VSB
1 2 3 4 5 6
8 9
DIIR GND
STANDBY
POWER_ON KEY
GND 5VSB
5V_KEY
BL ON/OFF NU/SELECT DIMMING GND GND INVERTER_PWR 12V INVERTER_PWR 12V
1
INVERTER_PWR 12V
INVERTER_PWR 12V
INVERT-SW
DIMMING
GND GND
ON-LCD
SB-LCD
GND
IR
5V-SB
KEY
GND
5VSB-OUT
5VSB-IN
CN1
P1
P601

Wiring Diagram Of Connector 26"

PANEL INVERTER CONNECTOR
40-L20PFL-IRC1XG
IR BOARD
40-L19PFL-KEC1XG
KEY BOARD
P800
P805
GND GND GND GND GND +24V +24V +24V +24V +24V
BL ON/OFF NU/SELECT DIMMING GND GND INVERTER INVERTER
5VSB DIIR GND STANDBY POWER_ON KEY GND 5VSB 5V_KEY
PWR 12V PWR 12V
+24V +24V +24V +24V +24V GND
1
GND GND GND GND VDIM VBLON PDIM GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
P1
ON-LCD
SB-LCD
GND
IR
5V-SB
1 2 3 4 5
P601
KEY
GND
5VSB-OUT
5VSB-IN
1 2 3 4
P5
40-1PL37C-PWF1XG
MAIN POWER
INVERTER BOARD
1 2 3 4 5 6
9 11 13 15 17 19 21 23 25 27
40-LDMK35-MAE2XG
1 2 3 4 5 6 7
1 2 3 4 5 6
8 9
1 2 3 4 5
1 2 3 4
40-L20PFL-IRC1XG
IR BOARD
40-L19PFL-KEC1XG
KEY BOARD
MAIN BOARD
10
P4
P804
1SP 408P
1 2 3 4 5 6 7
9
NU 5V-PW 5V-PW GND GND GND GND
12V-IN 12V-IN
12V-IN 12V-IN
5V-PW
5V-PW GND
GND GND GND
12V-IN 12V-IN
12V-IN 12V-IN
1 2 3 4 5 6
7
8 9 10
40-PWL20C-PWI1XG
POWER BOARD
1 2 3 4 5 6 7
9 10 11
NU 5V-PW 5V-PW GND GND GND GND
12V-IN 12V-IN
12V-IN 12V-IN
+12V +12V GND GND +12V +12V GND +12V GND
GND
+5V GND ON/OFF
P5
1 2 3 4 5 6 7 8 9
10
1 2 3
40-1PL37C-PWF1XG
MAIN POWER
40-PWL01B-STE1XG
STB POWER
11
I_17951_001.eps
050808
I_17951_002.eps
050808
Page 20
Block Diagrams, Test Point Overview, and Waveforms
/

Block Diagram MT5335

MT5335
20TCM2.0E LA 6.
V0.1
DC-DC
12V to 5V RT8110
VCC
8051 WT6702F
15 KEY 9 POWERON
11 STANDBY 14 IR
KEY BOARD
ON
OFF
MT5335
152 KEY
93 IR
+12V
+5V/
Standby+5v
EEPROM
M24C16MN
POWER
SUPPLY CONNECTOR
TUNER
TDQG4-601A
I2C
205 SCL
206 SDA
SAW-D9453D
SAW-K7270M
SIF
VIF
TD
A98
IF+/IF-
86T
132 TV_CVBS
MT5133
PARALLEL TS
SERIAL TS
MT8295
PARALLEL TS
CI
CARD
PARALLEL TS
PANEL
FLASH
32Mbit
DDR
32Mb
x16
CEC
COMMAND
62 OSCL1 63OSDA1
73 HDMI_5V
79 RX0_CB 80 RX0_C
81 RX0_0B 82 RXO_0
83 RX0_1B 84RXO_1
85 RX0_2B 86 RX0_2
205 DDC_SCL
204 DDC_SDA
HDMI SWITCH
SI8195
104 R
98 B
102 G
96 VSYNC
97 HSYNC
120 Y_IN
121 Pb_IN
123 Pr_IN
173 YPbPr_L
174 YPbPr_R
176 VGA_R
177 VGA_L
170 SCT_R_IN
171 SCT_L_IN
116 SCT_R
108 SCT_G
114 SCT_B
149 SCT_FS
107 SCT_FB
187 SCT_R_OUT
189 SCT_L_OUT
O/P
201
SPDIF
_OUT
129 CVBS
172 R_IN
173 L_IN
126 SY
125 SC
185
HP_R_OUT
186
HP_L_OUT
LVDS LV
DS
To
TTL
386
LVDS
Broken line is option for TTL
interface panel!
PRE AUDIO
R
L
AMP
TTL
AUDIO
AMP
R
L
EDID
EDID EDID
HDMI1
HDM2
VGA
YPbPr
SCART
SPDIF
AV
HEAD PHONE
I_17950_042.eps
080508
Page 21
Circuit Diagrams and PWB Layouts

7. Circuit Diagrams and PWB Layouts

Main Power Supply (20")

21TCM2.0E LA 7.
A A
MAIN POWER SUPPLY 20”
I_17930_024.eps
220408
Page 22
Circuit Diagrams and PWB Layouts

Layout Main Power Supply (20") (Top Side)

22TCM2.0E LA 7.

Layout Main Power Supply (20") (Bottom Side)

I_17930_025.eps
220408
I_17930_026.eps
220408
Page 23

Main Power Supply (26")

Circuit Diagrams and PWB Layouts
23TCM2.0E LA 7.
A1 A1
MAIN POWER SUPPLY 26”
I_17930_027.eps
220408
Page 24
Circuit Diagrams and PWB Layouts

Standby Power Supply (26")

24TCM2.0E LA 7.
A2 A2
STANDBY POWER SUPPLY 26”
I_17930_028.eps
220408
Page 25
Circuit Diagrams and PWB Layouts

Layout Main Power Supply (26") (Top Side)

25TCM2.0E LA 7.

Layout Main Power Supply (26") (Bottom Side)

I_17930_029.eps
220408
I_17930_030.eps
220408
Page 26
Circuit Diagrams and PWB Layouts

Layout Standby Power Supply (26") (Top Side)

26TCM2.0E LA 7.
Personal Notes:
I_17930_075.eps
250408
E_06532_012.eps
131004
Page 27

SSB: Tuner

8 76 543 21
Circuit Diagrams and PWB Layouts
27TCM2.0E LA 7.
2
C122
6V3
B1
DV33
DV33
NC/GND1
3
6V3
NC/100U
TUNER
NC
NC/GND2
NC/RFAGC
6
4
5
0R
R148
RF-AGC
L103
120R
C102
100U
R99
8
OUT3
C103
7
OUT2
6
OUT1
5
OC
NC/TPS2049
R95
NC/100R
Q105
2N7002
Q104
2N7002
TU
GND1
111412
TUNER_5V
NC
U206
GND
IN1
IN2
EN
AV_5V
10K
AV_ 5V
10K
SCL
SDA
NC1
15
13
R132
C125
22P
22P
1
2
NC/4K7
3
4
R96
NC/100R
5V-TUNER-INPUT
R828
TUNER_SDA0_5V
R829
TUNER_SCL0_5V
AS
ANALOG_IF
18
16
17
NC
C124
1U
C100
R97
5V-TUNER-ON/OF
IFAGC
XTALOUT
19
20
R135 4K7
R127
R126
TUNER_5V
L104 NC/120
IFOUT2
21
IFOUT1
100R
100R
R112
33R
0
L106
R124
100R
R125
100R
IF_AGC
R120
NC
C118
1000P
R118
NC
BA592
D100
Q103
C124ET
2
FAT_ IN-
FAT_IN+
TUNER_SDA0_5V
TUNER_SCL0_5V
C123
0.01U
L100
1UH
5V-OUT
R109 2K2
0.01U
C104
1000P
C105
R111
0.56UH
L101
C
B
E
1000P
C106
2K2
R133
33R
D101
BA982
D102
R113 6K8
R110 2K2
R117 NC
BA982
0R
X101
IN
R139 6K8
R123
5V-OUT
Q102
BC847C
IN/GND
C
E
GND
R140 6K8
B
OUT1
54321
D103
BA982
R100 680K
X102
IN
OUT2
R137 220K
R119
IN/GND
R108
5K6
5K6
GND
0.1U
C137
RF-AGC
R141
22K
0.01U
C109
OUT1
54321
U100
0.01U
C108
TUNER_5V
5
VCC
U101
Y
1
NC\0R
OUT2
23
24
SIF2
VIF1
1
2
R149
SIF1
VIF2
C107
2
OP2
OP1
390P
Z
R101
330R
21
AFC
FMPLL
C116
4
E
GND
3
C111
C110
20
VP
DEEM
574133 22
0.01U
MT5133-GPIO-AD
0.1U
C138
4LVC1G66GV
1500P
0.22U
18
19
VPLL
AGND
AFD
DGND
6
C117 0.47U
C139
C114
AUD CVBS
8 17
1000P
0.1U
0.47U
9 16
C128
L108
TUNER_5V
R145
12K
6V3
C2
47U
ATV-IF-AGC
D110
LL4148
30R
5V-OUT
R121
22K
12K
R146
0.01U
C119
ATV-IF-AGC
4M
X100
0.1U
C115
C112
20P
15
14
NC
REF
TAG C
VAG C
R114
22K
CVBS_OUT
R147
100K
TDA9886T
TOP
SDA
SCL
SIOMAD
11
10
12
C127
0.1U
R106
NC\6K8
R103
NC\1K5
R102
NC\180R
C
B
Q101
E
NC\BC847C
R104
NC\47R
R105 NC
C3
0.01U
B
CVBS-OUT
R107
R138
C
Q100
E
0R
220R
BC847C
R129
75R
R130
L107
120R
R93 NC\100R
TUNER_SCL0
TUNER_SDA0
75R
C113
SIF
5V-OUT
0.01U
R128
0R
R116 100R
R115 100R
R94
NC\100R
L102
6V3
C121
47P
1P5
C120
OSCL0
OSDA0
B01 B01
Z100
F
ANTPWR
1
E
D
C
B
A
0.1U
NC/0.1U
C126
TUNER_SDA0
TUNER_SCL0
AV_5V
120R
C101
100U
TUNER_5V
CVBS0
R131
0R
GND_TUNER
0.01U
C131
SIFP
SIFN
C132
0.01U
TUNER_SCL0_5V
TUNER_SDA0_5V
F
E
D
C
B
A
I_17950_021.eps
12345678
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Page 28

SSB: MCU Standby

8 76 543 21
Circuit Diagrams and PWB Layouts
28TCM2.0E LA 7.
B02 B02
F
KEY_5335
E
MCU STANDBY
STANDBY
POWER_ON
+3V3SB
35KEY_5V
3K3
R842 NC
2N7002/NC
Q817
R819
KEY
5V_KEY
D
+3V3SB_UP
HDMI_INT
C
SHORT_PROTECT
SW_UPDATE_CTL1
HSYNC
L811 600R
NC
R817
R815
4K7
5V_KEY
33R
NC
R833
5VSB
OIRI
L821
R813
R83433R
R8350R
R81233R
L822
L823
5V_KEY
5V_KEY
10K
R142
600R
600R
600R
+3V3SB_UP
R809 10K
600R
1
2
3
4
5
6
7
8
9
R807 10K
P805
OSCO
OSCI
CEC_IRQ
+3V3SB_UP
L820
600R
C871 1U
U810
116
OSCO VDD
2
OSCI
3
VSS
4
NRST
5
PWMI
6
RXD/IRQ3
7
TXD/IRQ2
8
HIN
WT6702F
AD0
AD3/IR
SCL1
SDA1
SCL2
SDA2
VIN
15
14
13
12
11
10
9
C823
0.1U
R81010K
R824 33R
R820
R823
R825
R814 33R
CEC
+3V3SB_UP
LL4148
R806
27K
33R
33R
33R
D801
C876
NC\1000P
C875
R822
R830
R805
100R
1000P
STANDBY
3V3SB_EN
VSYNC
OSCO
33R
33R
CEC_IRQ
100P
C819
R816
33R
KEY
OIRI_MCU
20P
C821
+3V3SB_UP
10K
R826
X800 32K7
R827
10K
OSCL0_SB
OSDA0_SB
OSCI
20P
C822
DV33
+3V3SB
R22 0R
Q810
2N7002
+3V3SB_UP
C820
0.1U
R10 0R
Q809
1
2
3
4
OSCL0
2N7002
OSDA0
ISP PORT
P802
F
E
D
C
1U
C802
OPTION for CEC Stand by Function
BT3904
OIRI_MCU
Q4
C
E
B
+3V3SB_UP
+3V3SB
1U
C824
L809
120R
RT9166
U811
2
C809
100U
6V3
0.1U
C825
GND
1
3
INOUT
6V3
0.1U
C826
C872
100U
5VSB
R144
4K7
GND
R143
10K
B
OIRI
B
A
A
I_17950_022.eps
070508
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Page 29

SSB: DC / DC

8 76554 3 21
Circuit Diagrams and PWB Layouts
29TCM2.0E LA 7.
C
E
GND/ADJ
1
ADJ/GND
U801
C840
0.1U
U804
C842
DV10
0.1U
0.1U
Q801
1
C865
R857 1K
BT3904
VIN
3
+5V
R851
Back Light circuit
10K
C
Q802
B
BT3904
+5V
E
LL4148
D804
C810
100U
16V
R831
2R7
23
OUTVIN
330R
4
4
GND/ADJ
OUT
1
2
4
4
GND/ADJ
OUT
VIN
1
2
3
100R
R847 NC
DIMMING
C827
1U
LD1117S12
U803
R832
2R7
DV33A
R801
6V3
6V3
R848
0.1U
6V3
C862
47U
C848
100U
0.1U
C818
C870
47U
R8012NC
R8013NC
5V_PW
BL ON/OFF
L815
600R
600R
1
2
3
SELECT
L814
4
R846
10K
5
6
7
+3V3SB
R856 IS FOR 26"
19"20"22" NC
R9NC
R852
4K7
R8001
R8003
10K
0R
5VSB
12V_IN
R856
4K7
ON/OFF
C
Q803
B
BT3904
E
R855
4K7
C852
1U
R854
0R
R8 47K
0.1U C829
Q800
A04803
8
D2A
7
D2B
D1A
D1B
5V_OUTSIDE
6
5
C854
1U
C828
C858
1U
0.1U
1
S2
2
G2
3 S1
4
G1
P800
NC
C863
4
4
GND/ADJ
OUT
VIN
1
2
3
120R
R802
L802
200R
C839
0.1U
AV12AV12
C807
0.1U
100U
6V3
DV33
AV33AV33
0.1U C837
AV25
C811
0.1U C843
4
4
U802
LD1117S
R803
5R1
12V
OUT
VIN
0.1U
C845
C849
GND/ADJ
123
3V3SB_EN
12V
C846
0.1U
D818
R92
2K2
R887
2K2
R889
4K7
R891
4K7
R893
4K7
CI_DV18
LD1117S50
16V
U805
47U
LL4148
C814
R898
B
R896
8K2
D809
LL4148
R894
100K
R895
10K
12V
R897
D810
LL4148
AV_5V
6V3
100U
D805
LL4148
D806
LL4148
D807
LL4148
R858
2K7
R859
4K7
R861
3K
R862
6K8
R863
3K
R864
6K8
C815
0.1U
C851
D811
LL4148
D812
LL4148
D817
LL4148
4
4
GND/ADJ
OUT
VIN
1
2
3
C850
0.1U
47K
C
Q807
BT3904
E
680R
CI_VCC
DDRV
AV25
LL4148
D816
R4
10K
AV_5V
3K9
R91
+5V
3K9
R886
R888
2K7
DV33
R890
2K7
AV33
R892
2K7
+3V3SB
AV9VAV9V
R804
6R8
R884
1K
6K2
R885
C813
100U
16V
C844
0.1U
5VSB
R8006
10K
R2
510R
C
Q805
B
BT3904
E
R5
10K
SHORT_PROTECT
B03 B03
F
DC-DC
P804
12V/4A
11
10
9
8
CONNECTOR
C859
0.1U 12V_IN
BL_ON/OFF
7
POWER CINCH
6
5
4
3
2
5V/2A
1
5V_PW
0.1U
C860
L813
30R
0R
5V_KEY
R865
5VSB
10K
Q816
BT3904
R8011
R8010
C
4K7
B
E
ON/OFF
BL_DIM
12V_IN
R860
0R
5VSB
E
R46
AV33
R850
4K7
R849
10K
AV33
+5V
NC
R845
1K
R844
R843
4K7
B
10K
L819
L818
200R
200R
12V
L14
200R
L15
200R
1000U
C804
4U7
0.1U
C832
0.1U
22K
R866
D
D808 LL4148
1
BOOT
2
DRIVE
3 6
FB GND
4
VCC
10R
R867
U807
RT8110
PHASE
UGATE
LGATE
8
7
5
G2
4
S2 3
G1
2
S1
1
D13N03LT
U808
about 1mm
D2B
D2A
D1B
GND
5VSB
C805
1U
GND
C
B
R10R
C
Q806
BT3904
12V
120R
L816
100U
16V
B
E
C816
C867
0.1U
+5V
3V9
D814
R6
10K
R7
10K
C869
R879
0.1U
R3
1K
U806
MP1411
4
IN
1K
1
NC1
9
EN
3
NC2
10
SS
C868
0.01U
C831
L800
15UH
5
6
7
D1A
8
C834
0.01U
10R
R869
NC
C833
NC
GND
2
BS
5
SW
7
FB
8
COMP
GND
6
C800
16V
LD1117S33
5V_OUTSIDE
GND
R876
NC
C830
NC
C803 4U7
1000U
C801
1K2
16V
L804
200R
L805
200R
+5V
T
6V3
U800
Z805
100U
4
4
OUT
VIN
2
3
U809
NC/KD1084-33
C841
C806
0.1U
0.1U
R871
R872
220R
R870
R868
GND
6V3
47U
LD1117S33
C812
LD1117S25
C864
0.01U
L801
L13
15UH
200R
C874
C817
330U
16V
4U7 R882 15K
C835
NC R874
4K7
C866 120P
0.01U
D803
SK24
R883
51K
F
12V
C853
0.1U
E
D
C
B
A
I_17950_023.eps
8
467
3 21
A
070508
Page 30
Circuit Diagrams and PWB Layouts

SSB: Digital Channel Decoder

8 76 543 21
30TCM2.0E LA 7.
B04 B04
F
E
D
DIGITAL CHANNEL DECODER
FAT_ IN-
TS0INDATA7
TS0INDATA6
TS0INDATA5
27M
X500
1
2
3
R500
1M
R536
33R
27P
C506
27P
C507
FAT_IN+
8
7
6
NC
L506
XTALI
AVDD33
DVDD12
DVD D33
C527
XTALO
NC
0.22U
C512
C511
1 2
3
4 5 6 7
8
9 10 11 12
U502
C513
1000P
C514
1000P
0.22U
AVSS33_3 AVSS33_2 XTALI XTALO AVDD33_2 ALC_IN VDD1.2 DGND1.2 TSDATA 7 TSDATA 6 TSDATA 5 VDD3.3
ADVDD33_1
48
C510
REFTOP
AVD D33_3
0.22U
VCMEXT
REFBOT
VCMEXT
REF_TOP
C568
NC/20P
C569
NC/20P
DVDD12
AVDD33
TUNER_SCL
TUNER_SDA
3738394041424344454647
IN-
IN+
REFBOT
AVDD33_1
VDD1.2_3
AVSS33_1
DGND1.2_1
TUNER_SCL
TUNER_SDA
VDD3.3_3
XTAL_SEL1 XTAL_SEL0
DGND3.3_1
VDD3.3_2
VDD1.2_2 HOST_SDA HOST_SCL
RF_AGC
IF_AGC
GPIO0
/RESET
R508
R507
MT5131_IF_AGC
36 35 34 33 32 31 30
29 28 27 26 25
0R
0R
SIF_SDA SIF_SCL
DV33 DV33
DVD D33
0.1U
C508
DVDD33
DVDD12
R503
R134
10K
R150
NC/1K
1K
NC
R506
R504
R501
0R
R502 0R
R136
10K
TUNER_SCL0
TUNER_SDA0
DV33
R151
NC/10K
MT5133-GPIO-AD
IF_AGC
CLOSE TO MT5133
C509
0.047U
R505
100R
10K
OSDA0
OSCL0
MT5133_RESET
AV12
AV12
L500
AV33
600R
Digital 1.8V Bypass Caps
1U
C500
C517
0.1U
0.1U
C519
C516
Digital 3.3V Bypass Caps
L501
600R
1U
0.1U C523
C521
C501
Analog 3.3V Bypass Caps
0.1U
0.1U
0.1U
C518
0.1U
C520
DVD D12
0.1U
C515
DVDD33DV33
0.1U
C522
AVD D33
45
AV33
L502
600R
L503
600R
1U
C502
0.1U
C525
ADVDD33_1
0.1U
C524
0.1U
C526
1U
C503
TSDATA 4
TSDATA 3
TSDATA 2
TSDATA 1
TSDATA 0
TSERR
TSVAL
TSSYNC
TSCLK
VDD3.3_1
DGND3.3
VDD1.2_1
R535
33R
TS0INDATA4
TS0INDATA3
C
TS0INDATA2
TS0INDATA1
TS0INDATA0
TS0INVALID
TS0INSYNC
TS0INCLK
1
2
3
45
R54233R
33R R543
R54433R
33R R545
MT5133
8
7
6
1314151617181920212223
L510
120R
24
DVDD33
DVDD12
F
E
D
C
B
120P/NC
C504
120P/NC
C505
B
A
A
I_17950_024.eps
070508
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Page 31

SSB: DVBT/ CI Decoder

8 76554 3 21
Circuit Diagrams and PWB Layouts
31TCM2.0E LA 7.
B05 B05
DVBT-CI-DECODER
CLOSE TO CI CONNECTOR
CI_VCCCI_VCCCI_VCC
R522
CI_VS2#
10K
CI_WAIT#
R523
10K
CI_VS1#
CLOSE TO MT8295
0.1U
C539
C538
27P
R509 1M
X501 27M
CI_RESET#
CI_XTALO
GND
GND
CI_AV33
CI_AV18
CI_XTALI
107
110
109
108
111
112
113
XTALI
XTALO
AVSS18_PLL
AVDD18_PLL
AVSS33_XTAL
AVDD 33_XTAL
A13
A14
A19
A20
WE#
VCC33_2
5355575962
52
0.1U
C529
CI_OEB
106
RESETB
A21
27P
CI_ALE
105
CI_RB
READY
GND
104
CI_CLE
A22
0.1U
CLOSE TO MT8295
C528
CI_POWE#
114
CI_INT
CI_DATA1
U501
A8
A18
C535
CI_CLE
103
GND33_4
A16
0.1U
102
CI_ALE
CI_DATA3
A23
A15
CI_INT
101
CI_DATA4
GND33_3
+5V+5V+5V
R524
10K
0.1U
C560
0.1U
C534
CI_DV33
CI_RB
CI_POCE1#
98
9997100
CI_DATA6
CI_DATA5
A24
A12
63
CI_DV33DV33 CI_DV18
L508
600R
C556
6V3
47U
3.3V: 0.2W (60mA)
1.8V: 0.2W (100mA)
CI_DV18CI_DV33
CI_GPIO1
CI_GPIO0
C554
1U
4K7
R511
C540
0.1U C541
0.1U
0.1U
0.1U
C536
C537
R510
4K7
U500
C552
1U
LD1117S18
2
3
OUT
VIN
4
4
L505
600R
1
GND/ADJ
C544
0.1U
CI_AV18CI_DV18
C545
0.1U
C557
6V3
47U
DV33
R548
NC
R513
0R
R5474K7
R546
4K7
R5144K7
CI_DV33
CI_PDD2
96
CI_WEB
95
CI_CEB
GPIO9 GPIO8 GPIO7
CD2#
BVD1
BVD2
REG#
WAIT#
RESET
VS2#
CI_PDD6
94
CI_PDD7 CI_VCC_EN
93 92
CI_VPP33_EN
91
CI_VPP5_EN
90
GND CI_IOIS16#
89
WP
88
CI_CD2#
87
CI_D2
D2
86
CI_OUTDATA2
D10
CI_D1
85
D1
CI_OUTDATA1
84
D9
83
CI_D0
D0
CI_DV18
82
CI_OUTDATA0
81
D8
CI_A0
80
A0
79
CI_OUTSYNC
78
CI_A1
A1
CI_OUTVALID
77
GND
76 75
CI_A2
A2
CI_REG#
74
CI_A3
73
A3
72
CI_INPACK#
71
CI_A4
A4
CI_WAIT#
70 69
CI_A5
A5
CI_DV33
68 67
CI_RESET CI_A6
66
A6
65
CI_OUTCLK
VCC33_4
CI_DATA2
CI_DATA7
GND18_1
VCC18_1
GND33_2
INPACK#
VCC33_3
A25
A7
64
R512
10K
MTK_IC_RESET
CLOSE TO MT8295
OPWM1
OPWM2
CI_DV33
CI_VCC CI_VPP
C561
10P
CI_IOIS16#
CI_D3 CI_D4 CI_D5 CI_D6 CI_D7 CI_CE1# CI_A10 CI_OE# CI_A11 CI_A9 CI_A8 CI_A13 CI_A14 CI_WE# CI_IREQ#
CI_INVALID CI_INCLK CI_A12 CI_A7 CI_A6 CI_A5 CI_A4 CI_A3 CI_A2 CI_A1 CI_A0 CI_D0 CI_D1 CI_D2
NC/0R
R531
P500
1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
30 31 32 33 34
35 36 37 38 39
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
CI_CD1# CI_OUTDATA3 CI_OUTDATA4 CI_OUTDATA5 CI_OUTDATA6 CI_OUTDATA7 CI_CE2# CI_VS1# CI_IORD# CI_IOWR# CI_INSYNC CI_INDATA0 CI_INDATA1 CI_INDATA2 CI_INDATA3
CI_INDATA4 CI_INDATA5 CI_INDATA6 CI_INDATA7
CI_VS2#
CI_RESET CI_WAIT#
CI_REG# CI_OUTVALID CI_OUTSYNC CI_OUTDATA0 CI_OUTDATA1 CI_OUTDATA2 CI_CD2#
CI_VCC CI_VPP
CLOSE TO MT8295
CLOSE TO CI CONNECTOR
+5V
0.1U R528
CI_VCC_EN
NC\0R
C546
NC\C124ET
CI_INPACK#
10K/NC
C
B
E
R532
CI_VCC
L509
30R
D
S
Q501
G
NC\A03401A
R527
47K/NC
Q502
CI_WE##
CI_IORD##
CI_IOWR##
NC\0.1U
C558
100K/NC
R526
0.1U/NC
C547
R549
CI_CE1## CI_CE1#
CI_OE##
CI_VS2#
100R
100R
100R
100R
100R
100R
R550
R551
R552
R553
R533
L507
C562
C563
C564
C565
C566
C567
CI_VPP
30R
C550
100U
6V3
10P
CI_OE#
10P
CI_WE#
10P
CI_IORD#
10P
CI_IOWR#
10P
CI_OUTCLK
10P
L504
600R
C543
CI_VCC
R519
NC\10K
R518
10K
0.1U
CI_IOIS16#
CI_AV33CI_DV33
0.1U
C542
CI_IREQ#
0.1U
C533
R525
NC
R520
10K
CI_CD1# CI_CD2#
0.1U
C559
0.1U C532
C531
R521
10K
C1
1U
F
CI_VCC
R517
NC\10K
R516
10K
CI_INPACK#
E
1U
C551
CLOSE TO MT8295
10P
TS_SYNCO
R53833R
126
127
128
GPIO13
GPIO14
VCC33_1
D15
353739
33
343638
C530
TS_CKO
R54033R
TS_D ATAO
TS_VALIDO
R541
33R
33R R539
L511 120R
5V-TUNER-ON/OF
5V-TUNER-INPUT
CI_PDD3
CI_PDD5
CI_PDD4
CI_DV33
CI_TS_SYNCO
CI_TS_VALIDO
CI_TS_CKO
CI_TS_DATAO
118
119
120
115
116
117
121
122
124
123
125
GPIO10
GPIO12
GPIO11
CI_OEB
TS_CKO
VCC33_5
GND33_5
CE1#
TS_SYNCO
CE2#
TS_DATAO
A10
VS1#
CI_DATA0
TS_VALIDO
OE#
A11
A9
GND33_1
IORD#
IOWR#
A17
4144464850
43
4042454749515460565861
D
GND
RESET_N
T
HDMI_SEL
PWRDN_EN
Z501
Z502
CI_GPIO14
T
1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
30 31 32
GPIO0 GPIO1 GPIO2 GPIO3 VCC33 T0CLK_I_ T0SYNC_I_ T0VALID_I_ T0DATA0_I_ GND33 T0DATA1_I_ T0DATA2_I_ T0DATA3_I_ T0DATA4_I_ VCC18 T0DATA5_I_ T0DATA6_I_ T0DATA7_I_ GPIO4 GPIO5 GPIO6 GND18 CD1# D3 D11 D4 D12 D5 D13 D6 D14 D7
C
CI_GPIO0 CI_GPIO1
HDMIED_WP
HPDIN
CI_DV33 TS0INCLK TS0INSYNC TS0INVALID TS0I N DATA 0
GND TS0I N DATA 1 TS0I N DATA 2 TS0I N DATA 3 TS0I N DATA 4 CI_DV18
TS0I N DATA 5 TS0I N DATA 6
B
TS0I N DATA 7
YPBPR_SW_IN
GND CI_CD1#
CI_D3 CI_OUTDATA3
CI_D4 CI_OUTDATA4
CI_D5 CI_OUTDATA5
CI_D6 CI_OUTDATA6
CI_D7
F
E
D
C
B
MT8295
CI_IOWR##
CI_IORD##
CI_A11
GND
CI_OE##
CI_A9
CI_INSYNC
CI_CE2#
CI_DV33
CI_VS1#
CI_OUTDATA7
CI_CE1##
A
CI_A10
CI_DV33
CI_INDATA3
CI_INDATA4
GND
CI_INDATA1
CI_A14
CI_IREQ#
CI_INVALID
CI_INDATA7
CI_A7
CI_WE##
CI_INDATA5
CI_INDATA6
CI_A12
CI_INCLK
100R
R515
CI_INDATA2
CI_INDATA0
CI_A13
CI_A8
I_17950_025.eps
8
467
3 21
A
070508
Page 32

SSB: Audio Amplifier

Circuit Diagrams and PWB Layouts
32TCM2.0E LA 7.
B06 B06
AUDIO AMPLIFIER
AL1O
SPEAK-OUTL
AR1O
SPEAK-OUTR
NC
0R
R622
R621
R617 NC
R618 0R
R624
100K
R623
100K
1
Y600
PGND
2
R620
2K2
2K2
R619
L-
GND
GND
L_OUT
U600 TDA7266
OUT1-
VCC1
OUT1+
1
3
2
1U
C612
C608
1U
2R7
R603
L600
L601
200R
C611
0.1U
200R
C610
4700P
C609
4700P
12V
IN1
4
NC1 5
2R7
1
MUTE
6
MUTE
R648
STBY 7
SS
2
L+
PGND
3
R+
S_GND
PW_GND
8
9
GND
16V
P600
4
IN2
12
0.1U
C615
VCC2
13
OUT2-
14
OUT2+
15
R_OUT
GND
GND
R-
R600
0R
Near the P502
R602
0R
R601
0R
Near the P502
PGND
PGND
NC2
10
NC3
11
C607
1000U
12V
R643
220R
R639
R641
4K7
4K7
B
BT3906
PGND
Q607
R640
16V
GND
BT3906
4K7
100U
C602
R642
1K
GND
AMP_MUTE
LL4148
D600
4K7
R625
D601
LL4148
HW_MUTE
R644
10K
BT3904
Q602
B
R630 10K
12V
C
E
GND
R632 10K
R627
R647
10K
10K
GND
R628 10K
22U
C606
16V
SS
NC
R631
MUTE
R659
100R
R629
100R
R656
100R
R626
100R
C600
3300P
GND GND
3300P
C601
0R/NC
E
C
B
E
Q608
C
L602
L603
R6360R/NC
R637
100U
600R
600R
16V
C616
HP_L
HP_R
R+
R_OUT
GND
EAR
1
P601
2
C614
C613
4700P/NC
3
9
8
7
6
L+ L_OUT
5 4
4700P/NC
GND
C617
100U16V
I_17950_026.eps
070508
Page 33
Circuit Diagrams and PWB Layouts

SSB: MT5335 Video Processor

8 76 543 21
33TCM2.0E LA 7.
B07 B07
MT5335 VIDEO PROCESSOR
DV33
10P
NC
60M
R211
X200
TXC
OXTALO
10P
C222
F
OSDA0 OSCL0
OSDA1 OSCL1
OPWM1
MTK_IC_RESET
AVDD33_XTAL
KEY
R200
E
R44
10K
DV33
R202
10K
D
HDMI_INT
B
E
BT3904
BL_DIM
OPWM2
OXTALO
OXTALI
AVC C_SRV
180K
PANEL_SLT SCART_FS_IN
PWRDET
AVD D33_REG C_XREG ORESET#
SW_UPDATE_CTL
R203
C
Q200
KEY_5335
MT5335PKU
10K
204 205
191 202 203 146 143 144 147 145
152 151 150 149 148
U203
63 62
88 87
72
OSDA0 OSCL0 OSDA1 OSCL1 OPWM0 OPWM1 OPWM2 VCXO XTALO XTALI AVD D33_SRV AVD D33_XTAL
ADIN4 ADIN3 ADIN2 ADIN1 ADIN0
AVD D33_REG C_XREG
OPWRSB
DV33
GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8
GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13
OPCTRL0 OPCTRL1 OPCTRL2 OPCTRL3 OPCTRL4 OPCTRL5ORESET_
R201
4K7
207 208 209 59 60 210 211 212 214 215 216
92 91 76 75 90 8971
CI_PDD3 CI_PDD4 CI_PDD5
CI_PDD6 CI_PDD7
CI_POWE#
CI_OEB CI_ALE
CI_CLE
MT5133_RESET
POWER_ON
LV DSVDD_EN
CI_INT
AMP_MUTE
BL_ON/OFF
EDID_PRT
R204
10K
C
DV33
B
10K
R205
E
CEC
DV33
R206
1K
C_XREG
PWRDET
10R
R207
LL4148
D200
4U7
C201
220U
16V
R208
220R
R210
47K
Adjust the power on timing
R209
B
1K
C
Q202
BT3904
E
ORESET#
OXTALI
C221
C203
L214
0.82UH
C223
F
1000P
E
D
Q201
BT3904
DV33
Z959
Z958
OSCL0
OSDA0
T
Z956
T
R216
R215
T
4K7
4K7
8
VCC
7
WC
6
SCL
5
SDA
T
Z957
M24C16MN
IIC ADDRESS "A0"
U205
E0/NC
E1/NC
E2/NC
VSS
1
2
3
Z960
T
4
0.1U
C247
DV33
C
R38
10K
R36
EDID_PRT
B
R37
10K
NC
R39
4K7
C
Q1
B
E
BT3904
R40
NC\0R
B
R214
10K
C
R217 33R
Q206
C124ET
E
DV33
DV33
L210
600R
L211
600R
1U
C204
1U
C206
AVCC_SRV
AVDD33_XTAL
0.1U
C224
0.1U
C225
C
B
DV33
L212
600R
1U
C205
AVD D33_REG
0.1U
C226
A
A
I_17950_027.eps
12345678
070508
Page 34
Circuit Diagrams and PWB Layouts

SSB: MT5335 Interface USB/HDMI

34TCM2.0E LA 7.
B08 B08
MT5335 INTERFACE - USB, HDMI
AV1 2
AV12
C228
1U
L215
600R
1U
C207
AVDD12_PLL
C249
0.01U
C250
0.1U
USB_VRT
USB_D­USB_D+ AVD D33_USB AVDD12_USB
68 65 66 67
69 157 158
U203
USB_VRT USB_DM USB_DP AVD D33_USB AVDD12_USB TP0 TN0
AVDD12_KADCPLL
AVDD12_TVDPLL
AVDD12_KHDMIPLL
AVDD12_KAPLL
AVDD12_SYSPLL
AVDD12_KDMPLL
AVDD12_DTDPLL
160 155 153 161 159 156 154
AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL AVDD12_PLL
AV33
GND
MT5335PKU
AV12
AV33
AV12
L216
600R
L217
600R
AVD D33_USB
1U
C208
AVDD12_USB
1U
C251
0.1U
C252
0.1U
GND
GND
USB_VRT
R218
5K1
SIFP SIFN
TS_VALIDO
TS_CKO
RX0_CB RX0_C RX0_0B RX0_0 RX0_1B RX0_1 RX0_2B RX0_2
164 166 167
194
79
80 81 82 83 84 85 86
U203
SIFP SIFN
AF
TUNER_CLK
MT5335PKU
U203
RX0_CB RX0_C RX0_0B RX0_0 RX0_1B RX0_1 RX0_2B RX0_2
MT5335PKU
AVDD25_SADC
AVSS25_SADC
RF_AGC
IF_AGCTUNER_DATA
EXT_RES
OPWR0_5V
AVD D33_HDMI
AVDD12_CVCC
163 165
193 192195
77 73
78 74
AVDD25_SADC
TS_ DATA O
TS_SYNCO
AVD D33_H AVDD12_CVCC
GND
HDMI_5V
HDMI_5V
AV25
AV33
AV1 2
AV25
AV33
AV12
C229
1U
C230
1U
L218
600R
L219
L220
600R
600R
1U C210
C211
1U
C212
1U
C213
AVDD25_SADC
AVD D33_H
AVDD12_CVCC
0.01U
C255
0.1U
0.1U
C253
C248
GND
C254
0.1U
GND
GND
GND
I_17950_028.eps
070508
Page 35

SSB: Interface LVDS TTL

Circuit Diagrams and PWB Layouts
35TCM2.0E LA 7.
B09 B09
INTERFACE LVDS TTL
A0N A0P A1N A1P
A2N
A2P
CK1N
CK1P A3N A3P
A4N
A4P
A5N A5P
A6N
A6P
CK2N
CK2P
A7N A7P
Footprint is ACM-2012
GND
AV33
AV33
MT5335PKU
GND
GND
R222
0R
R223
0R
L200
EXC24C
A0N
14
A0P
2
L201
EXC24C
A1N
14
A1P
2
L202
EXC24C
A2N
14
A2P
2
L203
EXC24C
14
CK1P
2
L204
EXC24C
A3N
14
A3P
2
L205
EXC24C
A4N
14
A4P
2
L206
EXC24C
A5N
14
A5P
2
L207
EXC24C
A6N
14
A6P
2
L208
CK2N
CK2P CLK22+
EXC24C
14
2
L209
EXC24C
A7N
14
A7P
2
3
3
3
3
3
3
3
3
3
3
AN00
AP00
AN11
AP11
AN22
AP22
CLK11-CK1N
CLK11+
AN33
AP33
AN44
AP44
AN55
AP55
AN66
AP66
CLK22-
AN77
AP77
C328
C329
C320
C321
C322
C323
C324
C325
C326
C327
C330
C331
C332
C333
C334
C335
C336
C337
C338
C339
10P
10P
GND
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
10P
GND
GND
GND
GND
GND
GND
GND
GND
U203
244
A0N
243
A0P
242
A2N
241
A2P
240
CK1N
239
CK1P
237
A3N
236
A3P
235
A4N
234
A4P
233
A5N
232
A5P
231
A6N
230
A6P
228
A7N
227
A7P
226
CK2N
225
CK2P
224
A8N
223
A8P
222
A9N
221
A9P
CLK11+
R2130R
0R
R212
PANEL_CTL1
PANEL_CTL2
GND
AP00
AP11
AP22
AP33
AP44
AP55
AP66
CLK22+
AP77
AVD D33_LVDSA AVD D33_LVDSB AVD D33_LVDSC
AVD D33_VPLL
TP2 TN2
220 229 238
217
218 219
AVD D33_LVDS AVD D33_LVDS AVD D33_LVDS
AVD D33_VPLL
CI_POCE1#
P202
39
37
35
33
31
29 30
27
25
23
21
19
17
15
13
11
9
7
5
3
40
AN00
38
AN11
36
AN22
34
32
CLK11-
AN33
28
26
24
22
AN44
20
AN55
18
AN66
16
CLK22-
14
AN77
12
10
8
6
4
12
VDD_PANEL
C260
0.1U
GND
12V
5V_OUTSIDE
+5V
R25NC
12V
35KEY_5V
PANEL_SLT
NC R26
L232
R232
NC
R26 FOR 19" 22" PANEL
R25 FOR OTHER +5V SUPPLY PANEL
NC/30R
P209
5
3
6
4
12
L233
NC/30R
LVD SVDD_EN
AV33
AV33
AV33
AV33
16V
GND
1U
1U
220U
C231
C220
C202
GND
L221
600R
L222
600R
4
6
R229 750R
LV DS OUT
C258
0.1U
B
GND
1U
C214
P204
C
E
C232
R219 10K
Q204
1U
12
3
5
R221
100K
C143ZT
AVD D33_LVDS
AVD D33_VPLL
R231 100K
1U
C209
Z210
T
C256
0.1U
120R
C257
0.1U
6K8
R230
R228
DV33
1
S1
2
S2
3
S3
G
DV33
GND
Q203
AO445 9
C259
0.1U
GND
R224 1K
R225 390R
R226 390R
R227
390R
8
D1
7
D2
6
D3
54
D4
C261
0.1U
Z212
T
VDD_PANEL
GND
GND
I_17950_029.eps
070508
Page 36

SSB: Flash Memory

Circuit Diagrams and PWB Layouts
5 4 3 2 1
36TCM2.0E LA 7.
B10 B10
D
C
B
FLASH MEMORY
R233
U0TX
U0RX
RS-232
10K
POCE0# POOE# PDD0 PDD1
CI_RB
CI_PDD2
R234
10K
252 251 250 249
245 248
MT5335PKU
OIRI_MT5335
AV33
GND
1
2
3
4
U203
POCE0_ POOE_ PDD0 PDD1
PAR B _ PDD2
BT3904
P201
Q3
R89
+5V
4K7
GND
C
E
U0RX
U0TX
OIRI
JTMS
JTRST_
JTCK
JTDO
JTDI
B
10K
95 94
93
253 1 256 255 254
R90
OIRI_MT5335
USB_D-
USB_D+
21
U0RX U0TX
JTMS
JTRST#
JTCK JTDO JTDI
OIRI
R87
EZJZ1V270RA
GND
1 2
+5V
0R
R2011
R2012
0R
R88
EZJZ1V270RA
GND
DV33
L223
600R
1U
C240
GND
R289
C007
0.1U
0R
10K
R245
POCE0#
PDD0
C006
100U
6V3
U202
116
HOLD# SCLK
2
VCC
3
NC
4
PO2
5
PO1
6
PO0
7
CS#
8
SO
WP#/ACC
PO6
PO5
PO4
PO3
GND
15
SI
14
13
12
11
10
9
POOE#
PDD1
DV33
R246
4K7
FRESET#
MX25L3205
GND
JTRST#
JTDI
JTMS
JTCK
JTDO
33R
R239
R270
10K
GND
DV33
6
7
8
R235
1K
1
2
3
45
TVTREF#1
JTAG_DBGRQ
JTAG_DBGACK
4
6
8
10
12
14
16
18
20
12
3
5
7
9
11
13
15
17
19
P203
R236
10K
R238
R237
10K
10K
1
2
3
4
DV33
P200
C262
0.1U
0.1U
C263
C264
0.1U C234
1U
1U
C235
GND
DV1 0
D
C
GND
B
DV33
R240
OPWM2
DV1 0
U203
14
VCCK
48
VCCK1
57
VCCK2
58
VCCK3
61
VCCK4
70
DVDD10
162
DVDD10_1
213
VCCK6
206
VCCK5
246
VCCK7
A
VCC2IO VCC2IO1 VCC2IO2 VCC2IO3 VCC2IO4 VCC2IO5 VCC2IO6 VCC2IO7 VCC2IO8 VCC2IO9
VCC3IO_3_2 VCC3IO_3_1
VCC3IO_3
E-PAD
10 12 16 18 27 30 52 54 55 56
64 197 247
257
DDRV_IC
DV33
GND
R244
4K7
Trap MODE
NORMAL MODE
ICE MODE
TRAP MODE
CORE RESET 1 US
AOBCK
AOLRCK
4K7
R241
4K7
R242
NC\4K7
GND
OPWM2 AOBLK AOLRCK
0
0
OPCTRL5
00
0
0
1
OPCTRL4
1
1U
C237
DDRV_IC
GND
1U
C238
GND
1U
C236
1U
C239
C265
C279
0.1U
0.1U
C266
0.1U
C278
0.1U C267
C277
0.1U
0.1U
C270
0.1U
C276
0.1U C269
0.1U
C275
0.1U C268
C274
0.1U
0.1U
C272
C273
0.1U
0.1U
C271
0.1U
A
MT5335PKU
I_17950_030.eps
12345
070508
Page 37

SSB: SDRAM

Circuit Diagrams and PWB Layouts
37TCM2.0E LA 7.
B11 B11
RDQS0 RDQM0 RDQ0 RDQ1 RDQ2 RDQ3 RDQ4 RDQ5 RDQ6 RDQ7 RDQS1 RDQM1 RDQ8 RDQ9 RDQ10 RDQ11 RDQ12 RDQ13 RDQ14 RDQ15
MEM_VREF RCS#
MT5335PKU
6V3
SDRAM
U203
11
RDQS0
13
RDQM0
9
RDQ0
8
RDQ1
7
RDQ2
6
RDQ3
5
RDQ4
4
RDQ5
3
RDQ6
2
RDQ7
17
RDQS1
15
RDQM1
19
RDQ8
20
RDQ9
21
RDQ10
22
RDQ11
23
RDQ12
24
RDQ13
25
RDQ14
26
RDQ15
53
RVREF 0
46
RCS_
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
MEM_WE#
MEM_CAS#
MEM_RAS#
MEM_CS#
MEM_BA0
MEM_BA1
MEM_ADDR10
MEM_ADDR0
MEM_ADDR1
MEM_ADDR2
MEM_ADDR3
+5V
C200
100U
GND
RA0 RA7
RWE_
RBA0
RA6
RBA1
RA5
RRAS_
RA8
RA10
RA4
RCAS_
RA12
RCKE
RA11
RA9 RA3 RA1 RA2
RCLK0_
RCLK0
R275
47R
1
2
3
45
R276
47R
1
2
3
45
R277
47R
1
2
3
45
R278
47R
1
2
3
45
R279
47R
1
2
3
45
U201
LD1117S
VIN
3
0.1U
C303
RA0
47
RA7
36
RWE#
40
RBA0
43
RA6
37
RBA1
44
RA5
38
RRAS#
42
RA8
35
RA10
45
RA4
39
RCAS#
41
RA12
32
RCKE
31
RA11
33
RA9
34
RA3
51
RA1
49
RA2
50
RCLK0#
28
RCLK0
29
8
7
6
RA12
RA11
RA9
RA8
8
7
6
RA7
RA6
RA5
RA4
RWE#
8
7
RCAS#
RRAS#
6
RCS#
8
7
RBA0
RBA1
6
RA10
8
7
6
RA0
RA1
RA2
RA3
4
4
GND/ADJ
OUT
1
2
R262
110R
R263
120R
GND
1.25 x (1+120/110) = 2.6V
RCKE
RCLK0
RCLK0#
22R
22R
22R
R258
R259
R260
MEM_DQ0 MEM_DQ1 MEM_DQ2 MEM_DQ3 MEM_DQ4 MEM_DQ5 MEM_DQ6 MEM_DQ7 MEM_DQ8 MEM_DQ9 MEM_DQ10 MEM_DQ11 MEM_DQ12 MEM_DQ13 MEM_DQ14 MEM_DQ15
MEM_ADDR13
MEM_CLKEN
MEM_CLK0
R261
100R
MEM_CLK0#
DDRV_IC
GND
10 11 13 54 56 57 59 60 62 63 65
14 17 19 25
43 50 53
18
33
15 55 61
34 48 66
12 52 58 64
2 4 5 7
8
1
3
9
6
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
NC NC1 NC2 NC3
NC4 NC5 NC6
VDD VDD1 VDD2 VDDQ VDDQ1 VDDQ2 VDDQ3 VDDQ4
VSS VSS2 VSS1 VSSQ1 VSSQ2 VSSQ VSSQ3 VSSQ4
32M*16DDR
U204
A10/AP
VREF
LDQS
UDQS
CKE
RAS CAS
LDM UDM
MEM_VREF
49
MEM_ADDR0
29
A0
30 31 32 35 36 37 38 39
40 28 41 42
45 46 44
24 23 22 21
16 51
20 47
26 27
L224
600R
MEM_ADDR1 MEM_ADDR2 MEM_ADDR3 MEM_ADDR4 MEM_ADDR5 MEM_ADDR6 MEM_ADDR7 MEM_ADDR8 MEM_ADDR9
MEM_ADDR10 MEM_ADDR11 MEM_ADDR12
MEM_CLK0
MEM_CLK0# MEM_CLKEN
MEM_CS#
MEM_RAS# MEM_CAS#
MEM_WE#
MEM_DQS0 MEM_DQS1
MEM_DQM0 MEM_DQM1
MEM_BA0 MEM_BA1
R265
0R
R264
R266
RDQ0
RDQ1
RDQ2
RDQ3
RDQ4
RDQ5
RDQ6
RDQ7
RDQS0
RDQM0
RDQM1
RDQS1
RDQ11
RDQ10
RDQ9
RDQ8
R271
47R
1
2
3
45
R272
47R
1
2
3
45
R273
47R
1
3 6
47R
47R
47R
47R
R248
R249
R250
R251
8
7
6
8
7
6
MEM_DQS0
MEM_DQM0
MEM_DQM1
MEM_DQS1
8
72
54
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ11
MEM_DQ10
MEM_DQ9
MEM_DQ8
R287
75R
1
2
3
8
7
6
45
R286
75R
1
2
3
8
7
6
45
R254
75R
R255
75R
R256
75R
R257
75R
R285
75R
1
2
3
8
7
6
45
DDRV
GND
L225
R267
600R
100K
MEM_VREF
0.1U
C306
GND
0.1U
R274
47R
MEM_DQ15
RDQ15
RDQ14
C305
C304
0.1U
RDQ13
RDQ12
1
2
3
45
8
7
MEM_DQ14
MEM_DQ13
6
MEM_DQ12
R288
75R
1
2
3
8
7
6
45
47U
6V3 C217
NC3
NC2
NC1
REFENVCNTL
RT9199
GND
VOUT
U200
VIN
1
2
36
L226
600R
4
0R
8
7
5
0R
220U
R268
100K
C314
16V
R269
1K
GND
A1 A2 A3 A4 A5 A6 A7 A8 A9
A11 A12
CLK CLK
CS
WE
BA0 BA1
+5V
+1V3D
+1V3D
R280
MEM_CS#
MEM_RAS#
MEM_CAS#
MEM_WE#
DDRV
DDRV
C349 IS CLOSE TO PIN33 OF DDR
L213
600R
16V
DDRV_IC
6V3
C349
220U
GND
MEM_VREF
100U
C315
0.1U
0.1U
0.1U
0.1U
C280
C282
C281
0.1U
0.1U C284
C283
0.1U
C285
0.1U
C287
C286
+1V3D
MEM_ADDR10
MEM_BA1
MEM_BA0
MEM_ADDR7
MEM_ADDR6
MEM_ADDR5
MEM_ADDR4
MEM_CLKEN
4U7
0.1U
C302
C215
C300
+1V3D
0.1U
GND
1U
0.1U
C301
C216
C296
0.1U C297
0.1U C299
0.1U
0.1U
C298
GND
MEM_ADDR12
MEM_ADDR11
MEM_ADDR9
MEM_ADDR8
MEM_ADDR13
MEM_ADDR3
MEM_ADDR2
1U
0.1U
0.1U
C294
C292
0.1U
C295
C316
0.1U
0.1U C288
C293
0.1U
C291
C290
0.1U
0.1U
C289
MEM_ADDR1
MEM_ADDR0
75R
1
2
3
8
7
6
45
R281
75R
1
2
3
8
7
6
45
R282
75R
1
2
3
8
7
6
45
R252
75R
R283
75R
1
2
3
8
7
6
45
R253
75R
R284
75R
1
2
3
8
7
6
45
GND
I_17950_031.eps
+1V3D
070508
Page 38
Circuit Diagrams and PWB Layouts

SSB: MT5335 Interface VGA

38TCM2.0E LA 7.
A
B12 B12
MT5335 INTERFACE - VGA
U203
VGA_ L VGA_ R YPBPR_L YPBPR_R AIN2_L AIN2_R
SCT_L SCT_R
AVD D33_AADC GND VIMD_AADC REFP_AADC GND
MT5335PKU
AV33
AV33
A
4U7
C219
L227
600R
177
AIN0_L
176
AIN0_R
175
AIN1_L
174
AIN1_R
173
AIN2_L
172
AIN2_R
171
AIN3_L
170
AIN3_R
169
AVD D33_AADC
181
AVSS33_AADC
179
VMID_AADC
180
REFP_AADC
178
REFN_AADC
C241
1U
AVDD33_KADAC0 AVDD33_KADAC1
AVSS33_KADAC0 AVSS33_KADAC1
AVDD33_AADC
GND
ASPDIF
AOMCLK
AOLRC K
AOBCK
AOSDATA0
ADAC_VCM
AVDD33_DIG
0.1U
C307
AL1
AR1
AL2
AR2
201 198
AOLRC K
199 200
A0SDATA0
196 186 185 189 187
AVDD33_ADAC0
190
AVDD33_ADAC1
182
GND
188
GND
184
ADAC_VCM
183
AVDD33_DIG
168
ASPDIF
AOMCLK
AL1O
AR1O
AL2O
AR2O
AV33
AV33
600R
L231
600R
L234
AOBCK
1U
C245
AVD D33_ADAC1
GND
C311
0.1U
1U
C246
ADAC_VCM
0.1U
C313
A
GND
AV33
AV33
AV33
AV33
L228
600R
L229
600R
C242
C243
1U
1U
REFP_AADC
GND
AVDD33_ADAC0
GND
GND
C308
0.1U
C309
GND
0.1U
GND
AV33
AV33
L230
600R
1U
C244
AVD D33_DIG
GND
C310
GND
0.1U
GND
GND
4U7
C218
GND
GND
VIMD_AADC
C312
0.1U
GND
A
I_17950_032.eps
070508
Page 39
Circuit Diagrams and PWB Layouts
39TCM2.0E LA 7.

SSB: D/A Converter

A
B13 B13
DIGITAL-ANALOG-CONVERTER
AL1O
AR1O
C900
C901
1U
R900
1U
R902
100K
GND
100K
GND
R901
470R
R903
470R
2200P
C925
2200P
C926
10K
R905
10K
R904
C929
GNDGND
GND
C930
NC
NC
5K1
33K
R907
33K
R906
R909
OPAVREF
OPAVREF
R910
5K1
C928
GND
C927
100P
100P
C902
47U
6V3
3
2
1IN+
2IN-
6
1IN-
2OUT
7
1
1OUT
VCC+
8
U1
1U
C912
C903
47U
GND
6V3
4
VCC-
RC4558
2IN+
5
L16
600R
10R
10R
R908
SPEAK-OUTL
AV9 V
R913
SPEAK-OUTR
GND
A
A
DAC
DV33
DV33
C9013
0.1U
R902733R
R902833R
R9029
R9020 10K
1
2
3
4
5
6
7
U907
LRCLK
DIN
BCLK
ENABLE
VMID
ROUT
AGND
WM8501
MCLK
FORMAT
DEEMPH
DVD D
DGND
LOUT
AVDD
C9018
0.1U
R9030
33R
14
13
12
11
10
9
8
AOMCL K
DACVL
ADCVA
0.1U
1U
C9016
C9014
1U
R9021
DACVL
C9017
10K
10K R9023
10K/NC
R9024
10K
R9025
NC/33K
R9022
0
R9017
0
R9018
L900
L901
600R
600R
C913
1000P1000P
GND
SCT1_AUL_OUT
SCT1_AUR_OUT
AV9V OPAVREF
R914
10K
R915
10K
GND
C910
GND
1U
OPAVREF
1U
C911
GND
R9019 47K
DV33
C9012
0.1U
AOLRCK
A0SDATA0
AOBCK
33R
C9015
1U
+5V
L930
30R
ADCVA
ADCVA
1U
C9008
C9010
0.1U
DV33
1U
C9009
L931
30R
DACVL
C9011
1U
A
R9026
NC/33K
C914
GND
I_17950_033.eps
070508
Page 40

SSB: HDMI Switch

Circuit Diagrams and PWB Layouts
40TCM2.0E LA 7.
B14 B14
HDMI SWITCH
P901
NC1
HPD
RX2+
RX2-
RX0+
RX0-
GND1
RX1+
GND3
DDCDA
VCC
GND1
NC1
DDCDA
HPD
RX1-
RXC+
RXC-
NC2
P903
RX1+
RX1-
GND3
RXC+
RXC-
NC2
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
CEC-IN
14
15
16
17
18
19
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
RX2+
RX2-
GND2
RX0+
RX0-
GND4
DDCCLK
GND5
GND2
GND4
DDCCLK
GND5
R42 NC\0R
HDMI1_SCL
HDMI1_SDA
+5V_HDMI1
CEC
+5V_HDMI0
1 2
3
4 5 6 7
8
9 10 11 12 13 14 15 16 17 18 19 20
DV33
DV33-HDMI
L9
600R
AV18-HDMI
R31
750R
C38
0.1U
0.1U
1U
C42
C39
GND
RX0_2
RX0_2B
RX0_1
RX0_1B
RX0_0
RX0_0B
RX0_C RX0_CB
NC\4K7
0.1U
C43
R15 4K7
DV33
GND
RESET_N
OSDA0
OSCL0
R54
4K7
R16 NC\4K7
R11
4K7
R18 R19
HDMI_SEL
100R 100R
R17
100R
R20
HPDIN
100R
OSDA1
OSCL1
HDMI_5V
0R
CEC-IN
1
R72
EZJZ1V270RA
2
GND
CI_DV18 AV18-HDMI
L11
600R
0.1U
0.1U
C12
C11
R45
CEC
DV33-HDMI
D5V0S1
D104
D105
10P
10P
C134
D5V0S1
D5V0S1
D106
D107
C133
D5V0S1
10P
10P
C136
C135
GND
CI_DV18
0.1U
0.1U
0.1U
C13
C14
0.1U
C15
C16
1U
C19
0.1U
C17
DV18-HDMI
L10
600R
0.1U
0.1U
C21
C20
1U
0.1U
C23
C22
R12
NC\4K7
R14 4K7
R13 4K7
GND
DV33
R32
R33
100R
NC\100R
R34
NC\100R
R35
R52 4K7
R55
4K7
C
Q2
B
BT3904
E
GND
100R
R53
D108
GND
134
2
D3V3L4
5
DV18-HDMI
R21
4K7
GND
R59
4K7
60 59 58 57 56 55 54
NC\0RR41
53 52 51 50 49 48 47 46 45 44 43 42 41
DV33
AGND7 RXC2+ RXC2­AVCC18D HPD2 AVCC33C CEC-A CEC-D RPWR1 DSCL1 DSDA1 AVDD18B R1X2+ R1X2­AGND6 R1X1+ R1X1­AVCC33B R1X0+ R1X0-
R30
GND
NC\4K7
63
6261656468
AVCC 33D
R2X0+
R2X0-
R2X1-
R1XC+
R1XC-
AGND5
37
39
38
40
4K7
R51
R2X1+
AVCC18C
36
HPD1
AGND8
35
66
R2X2-
I2CSEL/INT
34
67
R2X2+
DGND1
33
69
AVDD 18C
DSDA2
U904
SII9185
RPWR0
DVCC 18A
32
31
70
72
71
DSCL2
DVCC 18B
RPWR2
AVDD18A
DSCL0
DSDA0
29
30
DGND2
R0X2+
27
RSVDL
R0X2-
26
75
767473
HPDIN
AGND4
78
77
TSCL
TSDA
TPWR/I2CADDR
R0X1+
R0X1-
AVCC 33A
23
79
AGND9
R0X0+
2221252428
80
TX2+
AGND1
TX1+
AVCC 18A
TX0+
AGND2
TXC+
TXC-
EXTSWING
RESET#
LSDA LSCL
HPD0
AVCC 18B
R0XC-
R0XC+
AGND3
R0X0-
TX2-
TX1-
TX0-
GND
HDMI0_SCL
HDMI0_SDA
R58
4K7
+5V_HDMI0
+5V_HDMI1
GND
D109
T
T
U905
1
A0
0.1U
C40
2
Z907
GND
A1
3
A2
4
GND
134
5
D3V3L4
2
T
AT24C02
VCC
SCL
SDA
8
R56 4K7
7
WP
6
5
R50
R49
47K
47K
HDMI0_SCL
HDMI0_SDA
T
T
Z906
Z905
T
Z908
Z904
0.1U
U906
1
VCC
A0
C41
2
A1
3
SCL
A2
4
SDA
GND
AT24C02
GND
Z903
8
R57
R48
R47
4K7
47K
7
WP
6
5
47K
HDMI1_SCL
HDMI1_SDA
T
T
Z901
Z902
GND
I_17950_034.eps
070508
Page 41

SSB: I/O Scart

Circuit Diagrams and PWB Layouts
41TCM2.0E LA 7.
B15 B15
IO - SCART
P1
SCT1_AUR_OUT
1
SCT1_AUL_OUT
2
3
SCT1_B_IN
4
5
SCT1_G_IN
6
7
SCT1_R_IN
8
9
SCT1_AV_OUT
SCT1_AV_IN
SCT1_AUR_IN
SCT1_AUL_IN
SCT1_FS_IN
STC1_FB_IN
12
13
14
15
16
17
18
19
20
10
21
11
1 2
R63
EZJZ1V270RA
T
21
Z921
T
T
R64
Z927
Z925
Z926
T
Z924
T
T
Z923
T
Z919
T
Z918
T
Z922
EZJZ1V270RA
T
T
Z920
Z928
SCT1_AV_IN
SCT1_G_IN
21
GND
SCT1_B_IN
21
GND
SCT1_R_IN
21
GND
Nearly Connector
L903
30R
GND
L904
30R
R60
GND
EZJZ1V270RA
L905
30R
R61
GND
EZJZ1V270RA
L906
30R
R62
EZJZ1V270RA
R968 75R
R971 75R
R975 75R
R976 75R
47P
C967
C970
16P
C973
16P
C976
16P
68R
100R
68R
100R
R977
68R
R978
100R
R969
R972
R973
R974
R970
100R
Nearly 5335
C968
0.047U
C969
1U
C971
0.01U
C972
0.01U
C974
0.01U
C975
0.01U
C977
0.01U
C978
0.047U
SY0
GND_SV
Y0P
Y0N
PB0P
PBR0N
PR0P
SC0
STC1_FB_IN
SCT1_FS_IN
L907
30R
R65
EZJZ1V270RA
21
L908
30R
21
R66
EZJZ1V270RA
GND GND
R963
SOY0
0R
GND
R960 75R
33K
R961
GND
SCART_FS_IN
R962 10K
C979
470P
C980
470P
SCT1_AUR_OUT
21
SCT1_AUR_IN
SCT1_AUL_IN
SCT1_AUL_OUT
R67
EZJZ1V270RA
GND
21
R68
EZJZ1V270RA
NEARLY MT5335
C965
C966
1U
1U
SCT_R
SCT_L
I_17950_035.eps
070508
C964
10K
10K
R964
R965
R966 10K
R967 10K
L1
30R
L2
30R
C963
470P
GND
470P
Page 42
Circuit Diagrams and PWB Layouts

SSB: I/O Side AV, S-Video, Audio

42TCM2.0E LA 7.
B16 B16
CVBS_OUT
D2SA
P902
P902
WHITE
RED
YELLOW
IO - SIDE AV, SVIDEO, AUDIO
AV_ 5V
0R
NC
R918
R919
R9003
47U
10K
C001
C004
6V3
R9002 10K
9
Z975
7
5
T
T
6
8
Z974
GND
Z980Z981
TT
4
3
L926
L927
30R
30R
2
1
0.01U
R920
1K
1U
C003
GND
C9004
470P
L925
B
10R
C
E
470R
R9001
470P
BC847C
Q815
C9003
75R
10K
10K
R9004
R9010
R9009
SCT1_AV_OUT
47P
GND
R70
EZJZ1V270RA
21
R69
EZJZ1V270RA
21
R9012 10K
C002
R924
0R
Nearly Connector
L915
30R
GND
L916
30R
C9001
C9002
R9011 10K
GND
1U
1U
R947 75R
R949 75R
Q906
BC847C
AIN2_L
AIN2_R
47P
47P
GND
C958
C960
CVBS0
Close to MT5382p
R945
100R
C953
0.047U
T
Z917
CVBS1
SY0 SC0 SY1 SC1
D2SA
CVBS2
132 130 129 128 127 126 125
136
U203
CVBS0 CVBS1 CVBS2
SY0 SC0 SY1 SC1
D2SA
DVDD25_VADC DVSS25_VADC
GND_TUNER
GD_CVBS
GND_SV
AVDD25_VADC AVSS25_VADC
AVDD25_REF AVSS25_REF AVDD25_VFE AVSS25_VFE
139 140 133 131 124
141 142 137 138 135 134
DVDD25_VADC GND
GND_CVBS GND_SV
AVDD25_VADC GND AVDD25_REF GND AVDD25_VFE GND
C920
1U
CI_GPIO14
R921
C
E
4K7
B
R944
MT5335PKU
4K7
AV25
Nearly 5335
C959
R946
R948
0.047U
C961
0.047U
100R
100R
SY1
SC1
AV2 5
AV25
AV25
AV2 5
AV2 5
L911
600R
L912
600R
L913
600R
C916
1U
C917
1U
C918
1U
DVDD25_VADC
AVDD25_VADC
AVD D25 _RE F
C954
0.1U
GND
C955
0.1U
GND
C956
0.1U
AV2 5
AV25
L914
600R
1U
C919
AVD D25 _VF E
GND
C957
0.1U
GND
GND
R71
21
EZJZ1V270RA
GND_TUNER
Z978
GND
T
Z976
T
GND
L928
30R
R9014 75R
C9007
47P
R9013
100R
C9006
0.047U
C915
1U
CVBS2
GND_CVBS
I_17950_036.eps
070508
Page 43
Circuit Diagrams and PWB Layouts

SSB: MT5335 Interface YPbPr & VGA

43TCM2.0E LA 7.
B17 B17
MT5335 INTERFACE - YPBPR, VGA
Nearly Connector
P907
1
2
3
4
5
6
7
10
9
8
EZJZ1V270RA
YPBPR_L_IN
Y_IN
YPBPR_R_IN
PB_IN
PR_IN
VGA_R_IN
VGA_L_IN
R74
GND
EZJZ1V270RA
L4
Y_IN
30R
R982 75R
C731
16P
GND
L5
PB_IN
30R
R985 75R
C727
16P
R77
EZJZ1V270RA
21
21
21
R75
21
R76
EZJZ1V270RA
PR_IN
GND
L6
30R
R988 75R
C724
16P
WHITE
GREEN
RED
BLUE
RED
Nearly 5335
R984
0R
R981
68R
R983
100R
R986
68R
R987
100R
R989
68R
C728
4700P
C730
0.01U
C729
0.01U
C726
0.01U
C725
0.01U
C723
0.01U
SOY1
Y1P
Y1N
PB1P
PBR1N
PR1P
U203
SOY0 Y0P Y0N PB0P PBR0N PR0P
SOY1
Y1P Y1N
PB1P
PBR1N
PR1P
Z939
T
Z940
T
107 108 109 114 115 116 118 119 120 121 122 123
112 111
SOY0 Y0P Y0N PB0P PBR0N PR0P SOY1 Y1P Y1N PB1P PBR1N PR1P
TN1 TP1
DVDD12_VGA
AVSS12_RGBADC
AVDD12_RGBADC
AVSS12_RGBFE
AVDD12_RGBFE
VSYNC
HSYNC
SOG
117
DVDD12_VGA
113
GND
110
AVDD12_RGBADC
105
GND
101
AVDD12_RGBFE
RP
104
RP
RN
BP
BN GP GN
106 98 99 102 103 96 97 100
RN BP BN GP GN
VSYNC
HSYNC
SOG
MT5335PKU
AV12
AV12
L909
600R
1U
C987
DVDD12_VGA
C988
0.1U
AV12
AV12
L910
600R
AVDD12_RGBADC
GND
BLACK
P904
C990
0.1U
GND
C989
1U
AV12
AV12
L3
600R
AVD D12 _RG BFE
C991
1U
GND
C992
0.1U
GND
Z929
T
C732
2
SPDIF_OUT
0.1U
1
R980 100R
21
R73
C993
33P
EZJZ1V270RA
GND
R979
100R
ASPDIF
YPBPR_L_IN
YPBPR_R_IN
C722
10K
10K
R990
R991
R992 10K
L8
30R
L7
30R
C719
470P
470P
R993 10K
C721
C720
1U
YPBPR_L
1U
YPBPR_R
GND
I_17950_037.eps
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Page 44

SSB: I/O VGA

Circuit Diagrams and PWB Layouts
44TCM2.0E LA 7.
B18 B18
P908
IO - VGA
16
5
15
10
14
13
12
11
17
VGASCL_IN
4
9
3
8
2
7
1
6
W/P_CTR
VSYNC_IN
BLUE
HSYNC_IN
GREEN
VGASDA_IN
RED
GND
Z945
T
Z941
T
Z942
T
EZJZ1V270RA
R84
GND
T
Z943
21
T
Z944
T
21
R85
Z946
Z948
T
T
Z947
21
T
Z955
R716
0R
3
12
D913 BAV70
C005
ESD_0402
GND
EZJZ1V270RA
R86
W/P
VGA_PLUGPWR
+5V
GREEN
BLUE
RED
L918
L919
L920
Nearly Connector
30R
GND
30R
30R
GND
GND
R996 75R
R999 75R
R702 75R
C715
16P
C711
16P
C708
16P
5VSB
Nearly 5335
R998
0R
R719
33R
R997
100R
R720
33R
R701
100R
R721
33R
R703
100R
C712
4700P
C714
C713
C710
0.01U
C709
0.01U
C707
0.01U
C706
0.01U
0.01U
0.01U
SOG
GP
BN
RP
RN
GN
BP
GND
C996
0.1U
VGA_PLUGPWR
U903
1
A0
2
A1
3
A2
4
GND
AT24C02
VCC
WP
SCL
SDA
VGA_PLUGPWR
8
W/P
7
VGASCL
6
VGASDA
5
R715 10K
Z972
T
Z973
T
Z971
T
Z970
T
HSYNC_IN
VSYNC_IN
VGA_R_IN
VGA_L_IN
21
1 2
L921
30R
R82
EZJZ1V270RA
L922
30R
R83
EZJZ1V270RA
22K
R718R717
22K
Z949
T
Z950
T
HSYNC
VSYNC
L924
L923
30R
30R
GND
10P
10P
C705
C704
EZJZ1V270RA
C999
470P
C703
470P
10K
10K
R704
R705
R706 10K
C702
C701
R707 10K
5VSB
5VSB
5VSB
R708 10K
16P
R710 10K
16P
C998
C997
SW_UPDATE_CTL
R726
0R/NC
U0TX
E
VGASCL_IN
R712 100R
C143ZT
Q903
C
B
SW_UPDATE_CTL1
R725 10K
5VSB
B
5VSB
C
C143ZT
E
GND
R714 10K
Q905
VGASDA_IN
R713 100R
C
Q904
C143ZT
B
U0RX
E
1U
VGA_R
1U
VGA_L
GND
EZJZ1V270RA
EZJZ1V270RA
VGASCL_IN
R80
21
GND
VGASDA_IN
R81
21
R711
100R
R709
100R
VGASCL
VGASDA
GND
I_17950_038.eps
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Page 45

SSB: LVDS Receiver

Circuit Diagrams and PWB Layouts
45TCM2.0E LA 7.
B19 B19
LVD S RECEIVER
DV33A
40
30
20
10
4
2
VDD_PANEL
P205
39
3738
3536
3334
3132
29
2728
2526
2324
2122
19
1718
1516
1314
1112
9
78
56
3
1
GND
C2010
NC\TTL\0.1U
R0
R2
R4
R6
G0
G2
G4
G6
B0
B2
B4
B6
D_VSYNC
PANEL_CTL2
CLK
GND
DV33A
NC\TTL\0.1U
L929
NC\TTL\600R
C2001
NC\TTL\0.1U
GND
DV33A_LVDS_RECEIVER
C2202
C2004
NC\TTL\0.1U
NC\TTL\0.1U
C2006
NC\TTL\0.1U
C2007
NC\TTL\0.1U
T_HSYNC
T_VSYNC
CLK11-
CLK11+
T_B5
T_DE
T_R6
AN00 AP00 AN11 AP11
AN22 AP22
AN33 AP33
PWRDN
T_CLK
T_R0
C2015
DV33A_LVDS_RECEIVER
U207
1
RXOUT22
2
RXOUT23
3
RXOUT24
4
GND1
5
RXOUT25
6
RXOUT26
7
RXOUT27
8
LVD SGND1
9
RXIN0-
10
RXIN0+
11
RXIN1-
12
RXIN1+
13
LVD SVCC1
14
LVD SGND2
15
RXIN2-
16
RXIN2+
17
RXCLKIN-
18
RXCLKIN+
19
RXIN3-
20
RXIN3+
21
LVD SGND3
22
PLLGND1
23
PLLVCC1
24
PLLGND2
25
PWRDWN
26
RXCLKOUT
27
RXOUT0
28
V386
VCC4 RXOUT21 RXOUT20 RXOUT19
GND5 RXOUT18 RXOUT17 RXOUT16
VCC3 RXOUT15 RXOUT14 RXOUT13
GND4 RXOUT12 RXOUT11 RXOUT10
VCC2
RXOUT9 RXOUT8 RXOUT7
GND3
RXOUT6 RXOUT5 RXOUT4 RXOUT3
VCC1
RXOUT2 RXOUT1GND2
R293
T_R7
T_R6
T_R5
T_R4
T_R3
T_R2
T_R1
T_R0
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30
29
T_B4 T_B3
T_B2
T_B1 T_B7 T_B6
T_B0 T_G5 T_G4
T_G3 T_G7 T_G6
T_G2 T_G1
T_G0
T_R5 T_R7 T_R4 T_R3
T_R2 T_R1
T_G7
T_G6
T_G5
T_G4
T_G3
T_G2
T_G1
T_G0
GND
T_B0
NC\TTL\33R
1
2
3
45
R294
NC\TTL\33R
1
2
3
45
R295
NC\TTL\33R
1
2
3
45
R296
NC\TTL\33R
1
2
3
45
R298
NC\TTL\33R
1
T_B7
T_B6
2
T_B5
3
T_B4
45
R299
T_B3
T_B2
T_B1
NC\TTL\33R
1
2
3
45
8
R7
R6
7
R5
6
R4
R1
R3
8
R3
7
R2
6
R1
R0
8
G7
7
G6
G5
6
G4
R5
R7
G1
G3
G5
G7
B1
B3
8
G3
G2
7
6
G1
G0
8
B7
B6
7
B5
6
B5
B7
D_HSYNC
DE
B4
8
B3
B2
7
B1
6
B0
AN00
AN11
AN22
CLK11-
AN33
R23
100R
R24
100R
R2003
100R
R2004
100R
100R
R2005
AP00
AP11
AP22
CLK11+
AP33
PWRDN_EN
DV33A
B
DV33A
C
C143ZT
E
GND
Q5
R291 NC\TTL\10K
PWRDN
T_CLK
T_DE
T_VSYNC
T_HSYNC
L239
120R
R290
NC\TTL\33R
1
2
3
45
NC\TTL\33R
R292
8
7
6
CLK
DE
D_VSYNC
D_HSYNC
C2011
NC\TTL\16P
GND
I_17950_039.eps
070508
Page 46
Circuit Diagrams and PWB Layouts

Layout Small Signal Board (Top Side)

46TCM2.0E LA 7.
I_17950_040.eps
070508
Page 47
Circuit Diagrams and PWB Layouts

Layout Small Signal Board (Bottom Side)

47TCM2.0E LA 7.
I_17950_041.eps
080508
Page 48
Circuit Diagrams and PWB Layouts
s
4
48TCM2.0E LA 7.

Keyboard Control Panel

KEYBOARD CONTROL
E E
Personal Notes:
P601
4
3
2
GND
1
5VIN
5VSB
KEY
0
R701
0.1U
C601

Layout Keyboard Control Panel (Top Side)

1K
1K5
2K7
4K3
7K5
R601
390R
R602
R603
R604
R605
R606
vol-
vol+
menu
ch-
ch+
POWER
K606
1 24
1 24
1 24
1 24
1 24
1 24
3
K605
3
K604
3
K603
3
K602
3
K601
3
I_17930_031.eps
250408
I_17930_032.eps
220408
E_06532_012.ep
13100
Page 49

Inverter Panel

1
INVERTER
I I
D
C
B
A
O/S 1
O/S 2
O/S 3
O/S 4
O/S 5
O/S 6
Circuit Diagrams and PWB Layouts
2
CN1
1 2
3
4 5 6
R24
NC
D1/NC
BAW56K
D2/NC
BAW56K
D3/NC
BAW56K
R2 0
R4
5.6K
R12 100
F1
5A
R61 510K
510K
DTC143
R23
R63
Q1
2N7002
R17 100(1206)
Q4 DTA143
C14 105
16
R20
15
100K
14
13
12
R21
11
22
10
R22
22
0
FB
R25 1K
C52 105
C55 105
R27 100
Q5 DTA143
Q6
D6
1N4148
R29 NC
C1
C3
220uF/25V
220uF/25V
C4
104
C5
R5
105
47K
R6
270K
C6
105
O/S
C8
C7
R7 20K
C9 331
C11
103
R11 3K
R15 100K
R1 300K
R3 100K
R8
NC
681
33kR916k
C10
NC
Q2
2N7002
R13
C12
NC
104
R10 1M
R14 1M
Q3
2222
C13
105
U1
1
2
3
4
5
6
7
8 9
R26
NC
D4
BAV99
B
A
D5 1N4148
C34
R16 1M\NC
105
A K
IC-Vcc
ZD1
8.2V
R19 100K
3
IC-Vcc
R31 NC
C15
R18
103
100K
R56 2K
R57
4.7K
U1B
LM393
U1A
C54 105
LM393
O/S
D26
1N4148
R28
3K
R62
3K
D25
1N4148
ZD2
4.3V
R30 560
A K
R33 NC
ZD3
4.3V
R32 560
A K
DTA143
R60
Q10
VCC / 8.2V
R58
10K
1K
R59
30K
Q7 2907
Q8 2907
D7
2222
D8
2222
49TCM2.0E LA 7.
54
D9
R34 22K
C16
223
R35 150
R36
22K
C17
223
R37 150
22K
C18
223
R39
10K
R64
Q11
C56 104
2222
150
R40 22K
C19
223
R41 150
BAW56K
R42 10
R43 10
D10 1 N4148
D11
BAW56K
R44 10
R45
10
D12 1 N4148
D13
R38
BAW56K
R46
10
R47 10
D14 1 N4148
D15
BAW56K
10
R48
R49
10
D16 1 N4148
6
C25
C21
225(1206)
5
D2
6
D2
7
D1
8
D1
5
6
D2
7
D1
8
D1
C24
225(1206)
5
6
D2
7
D1
8
D1
5
6
D2
7
D1
8
D1
C20
225(1206)
U2
4
G2
3
S2
2
G1
1
3
2
1
S1
U3
G24D2
S2
G1
S1
C22
105
C23 105
225(1206)
U4
G24D2
3
S2
2
G1
1
3
2
1
S1
U5
G24D2
S2
G1
S1
C26 105
C27 105
7
T1
4
1
T2
4
1
T3
4
1
T4
4 7
1
T5
4 7
1
T6
4 7
1
8
R50
CN2
1 2
O/S 1
820
CN3
1 2
3
4 5
CON5
B
D
C
D23
BAV99
D
7
C28
10pF
6
C36
NC
C29
10pF
C37
471
BAV99
D17
FB
C39
C38
471
NC
C35
222
7
6
C53 222
D21
BAV99
O/S2
R54
820
FB
7
C30 10pF
6
C40
222
C31
10pF
6
C49
222
D19
BAV99
C32
10pF
6
C46 222
C33 10pF
6
C43
222
C42
BAV99
D22
BAV99
D20
D18
471
BAV99
FB
C51 471
R52
820
C48
471
FB
C45
471
O/S 4
O/S 3
R51
820
D
R53 820
C
R55
820
FB
C41 NC
C50 NC
FB
C47 NC
C44
NC
CN4
O/S 5
CN5
1 2
O/S 6
D24
B
BAV99
1 2
3
4 5
CON5
D27
A
BAV99
C
B
A
123 456 87
I_17930_035.eps
220408
Page 50
Circuit Diagrams and PWB Layouts

Layout Inverter Panel (Top Side)

50TCM2.0E LA 7.

Layout Inverter Panel (Bottom Side)

I_17930_036.eps
220408
I_17930_037.eps
220408
Page 51

IR LED Panel

s
4
Circuit Diagrams and PWB Layouts
51TCM2.0E LA 7.
J J
P1
R6
100R
R9
GND
LED1
IR
+5V
R1
4K7
C3
47U
D3
5 4 3 2 1
LED2
4K7
6V3
R5
100R
C2
BT3904
C1
10U
R3
10U
1K
C
Q1
B
E
Q2
E
C
IR
VCC GND
B
BT3906
G1
4K7
3K3
R7
R4
IR & LED
Personal Notes:
R51
4K7
R52
4K7
R2
B
BT3904

Layout IR LED Panel (Top Side)

4K7
C
E
Q5
13
RW
D1
2
I_17930_033.eps
220408
I_17930_034.eps
220408
E_06532_012.ep
13100
Page 52
Personal Notes:
Circuit Diagrams and PWB Layouts
52TCM2.0E LA 7.
E_06532_013.eps
131004
Page 53

8. Alignments

Alignments
EN 53TCM2.0E LA 8.
Index of this chapter:

8.1 Electrical Alignments

8.2 Hardware Alignments

8.3 Software Alignments

Note:
The Service Modes are described in chapter 5. Menu navigation is done with the CURSOR UP, DOWN, LEFT or RIGHT keys of the remote control transmitter.
8.1 Electrical Alignments
Perform all electrical adjustments under the following conditions:
• Power supply voltage (depends on region): – AP-NTSC: 120 VAC or 230 VAC / 50 Hz (± 10%). – AP-PAL-multi: 120 - 230 VAC / 50 Hz (± 10%). – EU: 230 VAC / 50 Hz (± 10%). – LATAM-NTSC: 120 - 230 VAC / 50 Hz (± 10%). – US: 120 VAC / 60 Hz (± 10%).
• Connect the set to the mains via an isolation transformer with low internal resistance.
• Allow the set to warm up for approximately 60 minutes.
• Measure voltages and waveforms in relation to correct ground (e.g. measure audio signals in relation to AUDIO_GND). Caution: It is not allowed to use heatsinks as ground.
• Test probe: R
• Use an isolated trimmer/screwdriver to perform alignments.
> 10 MΩ, Ci < 20 pF.
i
Table 8-2 Alignment for 26" with a colour analyser
Cool (11000K) Normal (9000K) Warm (6500K)
x (70 IRE) 0.278 +/- 0.003 0.289 +/- 0.003 0.314 +/- 0.003
y (70 IRE) 0.278 +/- 0.003 0.291 +/- 0.003 0.319 +/- 0.003

8.3.2 Display Code

When after an SSB or display exchange, the display option code is not set properly; it will result in a TV with “no display” or strange resolution. Therefore, it is required to set this display option code after such a repair. To do so, press (slowly) the following key sequence on a standard RC transmitter: “062598” directly followed by “MENU” and “xxx”, where “xxx” is a 3 digit decimal value of the panel type: see column “Display code” in table below. When ready, the set will go to stand-by. After this, perform a cold start.
LCD Panel: Display Code:
AUO 19” 096
CMO 19” - M190Z1-L01 094
LG 20” - LC201V02-SDD1 093
AUO 22” 097
CMO 22” - M220Z1-L03 022
AUO 26” - T260XW03 V3 030
AUO 26” VM 098
CMO 26” 095
8.2 Hardware Alignments
Not applicable.
8.3 Software Alignments

8.3.1 White Balance Adjustment (VGA Mode)

Only VGA input requires colour temperature adjustment as all other inputs or relative ones. Both WARM and COOL colour coordinates are also relatives to NORMAL colour temperature mode ones. Equipment requirements: Colour analyser (e.g Minolta CA-
210).
Pre conditions:
• Picture Preset: Standard.
• Black Expand: Off.
• Tone: Normal.
• Dynamic Contrast: Off.
Colour Temp Alignment
Apply a 1366×768@50Hz signal with white pattern, set “brightness” at 100%, and “contrast” at 50%. Adjust the R, G, and B sub-gain for the screen centre. The 1931 CIE chromaticity (x, y) co-ordinates shall be:
Table 8-1 Alignment for 19", 20", and 22" with colour
analyser
Cool (9000K) Normal (8 000K) Warm (6500K)
x (70 IRE) 0.289 +/- 0.003 0.296 +/- 0.003 0.314 +/- 0.003
y (70 IRE) 0.291 +/- 0.003 0.299 +/- 0.003 0.319 +/- 0.003
Page 54
EN 54 TCM2.0E LA9.
Circuit Descriptions, Abbreviation List, and IC Data Sheets

9. Circuit Descriptions, Abbreviation List, and IC Data Sheets

Index of this chapter:

9.1 Introduction

9.2 Block Diagram

9.3 Abbreviation List
9.4 IC Data Sheets
9.1 Introduction
This chassis is a digital derivative from the TCM1.0E LA chassis and supports DVB-T reception. It uses the Mediatek MT5335 main chip. It processes the following input/output signals:
• Analog and digital RF signals (PAL B/G, D/K, I, SECAM B/ G, D/K, L/L’, DVB-T)
• SCART input signals (CVBS & RGB)
• CMP input signals (YPbPr)
• VGA input signals
• HDMI input signals, v1.2 compliant, with HDCP, audio included as EIA-861B standard
• S-Video input
• Headphone output
• SPDIF output.
9.2 Block Diagram
Notes:
•Only new circuits (circuits that are not published recently) are described.
• Figures can deviate slightly from the actual situation, due to different set executions.
The platform is also designed for the lowest power consumption in off/stand-by mode (<0.3W) to fulfil new Philips CE environment policy requirement. The MT5335 is surrounded by a tuner, a video demodulator, a HDMI interface, SDR and flash memory, an audio amplifier, and optionally a stand-by microprocessor (26"). For the smaller set versions also the inverter board is serviceable.
For the block diagram, refer also to chapter 6 “Block diagrams, Test Point Overviews, and Waveforms”.

Figure 9-1 Block diagram

I_17951_012.eps
060808
Page 55
Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 55TCM2.0E LA 9.

9.3 Abbreviation List

0/6/12 SCART switch control signal on A/V
board. 0 = loop through (AUX to TV), 6 = play 16 : 9 format, 12 = play 4 : 3
format 1080i 1080 visible lines, interlaced 1080p 1080 visible lines, progressive scan 2DNR Spatial (2D) Noise Reduction 3DNR Temporal (3D) Noise Reduction AARA Automatic Aspect Ratio Adaptation:
algorithm that adapts aspect ratio to
remove horizontal black bars; keeps
the original aspect ratio ACI Automatic Channel Installation:
algorithm that installs TV channels
directly from a cable network by
means of a predefined TXT page ADC Analogue to Digital Converter AFC Automatic Frequency Control: control
signal used to tune to the correct
frequency AGC Automatic Gain Control: algorithm that
controls the video input of the feature
box AM Amplitude Modulation ANR Automatic Noise Reduction: one of the
algorithms of Auto TV AP Asia Pacific AR Aspect Ratio: 4 by 3 or 16 by 9 ASF Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
bars without discarding video
information ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA ATV See Auto TV Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way AV External Audio Video AVC Audio Video Controller AVIP Audio Video Input Processor B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz BLR Board-Level Repair BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries B-TXT Blue TeleteXT C Centre channel (audio) CEC Consumer Electronics Control bus:
remote control bus on HDMI
connections CL Constant Level: audio output to
connect with an external amplifier CLR Component Level Repair COLUMBUS COlor LUMinance Baseband
Universal Sub-system ComPair Computer aided rePair CP Connected Planet / Copy Protection CSM Customer Service Mode CTI Color Transient Improvement:
manipulates steepness of chroma
transients CVBS Composite Video Blanking and
Synchronization DAC Digital to Analogue Converter DBE Dynamic Bass Enhancement: extra
low frequency amplification
DDC See “E-DDC” D/K Monochrome TV system. Sound
DFI Dynamic Frame Insertion DFU Directions For Use: owner's manual DMR Digital Media Reader: card reader DMSD Digital Multi Standard Decoding DNM Digital Natural Motion DNR Digital Noise Reduction: noise
DRAM Dynamic RAM DRM Digital Rights Management DSP Digital Signal Processing DST Dealer Service Tool: special remote
DTCP Digital Transmission Content
DVB-C Digital Video Broadcast - Cable DVB-T Digital Video Broadcast - Terrestrial DVD Digital Versatile Disc DVI(-d) Digital Visual Interface (d= digital only) E-DDC Enhanced Display Data Channel
EDID Extended Display Identification Data
EEPROM Electrically Erasable and
EMI Electro Magnetic Interference EPLD Erasable Programmable Logic Device EU Europe EXT EXTernal (source), entering the set by
FBL Fast BLanking: DC signal
FDS Full Dual Screen (same as FDW) FDW Full Dual Window (same as FDS) FLASH FLASH memory FM Field Memory or Frequency
FPGA Field-Programmable Gate Array FTV Flat TeleVision Gb/s Giga bits per second G-TXT Green TeleteXT H H_sync to the module HD High Definition HDD Hard Disk Drive HDCP High-bandwidth Digital Content
HDMI High Definition Multimedia Interface HP HeadPhone I Monochrome TV system. Sound
2
C Inter IC bus
I
2
I
D Inter IC Data bus
2
S Inter IC Sound bus
I IF Intermediate Frequency Interlaced Scan mode where two fields are used
carrier distance is 6.5 MHz
reduction feature of the set
control designed for service technicians
Protection; A protocol for protecting digital audio/video content that is traversing a high speed serial bus, such as IEEE-1394
(VESA standard for communication channel and display). Using E-DDC, the video source can read the EDID information form the display.
(VESA standard)
Programmable Read Only Memory
SCART or by cinches (jacks)
accompanying RGB signals
Modulation
Protection: A “key” encoded into the HDMI/DVI signal that prevents video data piracy. If a source is HDCP coded and connected via HDMI/DVI without the proper HDCP decoding, the picture is put into a “snow vision” mode or changed to a low resolution. For normal content distribution the source and the display device must be enabled for HDCP “software key” decoding.
carrier distance is 6.0 MHz
to form one frame. Each field contains
Page 56
EN 56 TCM2.0E LA9.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
half the number of the total amount of lines. The fields are written in “pairs”,
causing line flicker. IR Infra Red IRQ Interrupt Request ITU-656 The ITU Radio communication Sector
(ITU-R) is a standards body
subcommittee of the International
Telecommunication Union relating to
radio communication. ITU-656 (a.k.a.
SDI), is a digitized video format used
for broadcast grade video.
Uncompressed digital component or
digital composite signals can be used.
The SDI signal is self-synchronizing,
uses 8 bit or 10 bit data words, and has
a maximum data rate of 270 Mbit/s,
with a minimum bandwidth of 135
MHz. ITV Institutional TeleVision; TV sets for
hotels, hospitals etc. JOP Jaguar Output Processor LS Last Status; The settings last chosen
by the customer and read and stored
in RAM or in the NVM. They are called
at start-up of the set to configure it
according to the customer's
preferences LATAM Latin America LCD Liquid Crystal Display LED Light Emitting Diode L/L' Monochrome TV system. Sound
carrier distance is 6.5 MHz. L' is Band
I, L is all bands except for Band I LORE LOcal REgression approximation
noise reduction LPL LG.Philips LCD (supplier) LS Loudspeaker LVDS Low Voltage Differential Signalling Mbps Mega bits per second M/N Monochrome TV system. Sound
carrier distance is 4.5 MHz MIPS Microprocessor without Interlocked
Pipeline-Stages; A RISC-based
microprocessor MOP Matrix Output Processor MOSFET Metal Oxide Silicon Field Effect
Transistor, switching device MPEG Motion Pictures Experts Group MPIF Multi Platform InterFace MUTE MUTE Line NC Not Connected NICAM Near Instantaneous Compounded
Audio Multiplexing. This is a digital
sound system, mainly used in Europe. NTC Negative Temperature Coefficient,
non-linear resistor NTSC National Television Standard
Committee. Color system mainly used
in North America and Japan. Color
carrier NTSC M/N= 3.579545 MHz,
NTSC 4.43= 4.433619 MHz (this is a
VCR norm, it is not transmitted off-air) NVM Non-Volatile Memory: IC containing
TV related data such as alignments O/C Open Circuit OSD On Screen Display OTC On screen display Teletext and
Control; also called Artistic (SAA5800) P50 Project 50: communication protocol
between TV and peripherals PAL Phase Alternating Line. Color system
mainly used in West Europe (color
carrier= 4.433619 MHz) and South
America (color carrier PAL M=
3.575612 MHz and PAL N= 3.582056
MHz) PCB Printed Circuit Board (same as “PWB”) PCM Pulse Code Modulation PDP Plasma Display Panel PFC Power Factor Corrector (or Pre-
conditioner) PIP Picture In Picture PLL Phase Locked Loop. Used for e.g.
FST tuning systems. The customer
can give directly the desired frequency POR Power On Reset, signal to reset the uP Progressive Scan Scan mode where all scan lines are
displayed in one frame at the same
time, creating a double vertical
resolution. PTC Positive Temperature Coefficient,
non-linear resistor PWB Printed Wiring Board (same as “PCB”) PWM Pulse Width Modulation QRC Quasi Resonant Converter QTNR Quality Temporal Noise Reduction QVCP Quality Video Composition Processor RAM Random Access Memory RGB Red, Green, and Blue. The primary
color signals for TV. By mixing levels
of R, G, and B, all colors (Y/C) are
reproduced. RC Remote Control RC5 / RC6 Signal protocol from the remote
control receiver RESET RESET signal ROM Read Only Memory R-TXT Red TeleteXT SAM Service Alignment Mode S/C Short Circuit SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs SCL Serial Clock I SCL-F CLock Signal on Fast I SD Standard Definition SDA Serial Data I SDA-F DAta Signal on Fast I
2
C
2
C
2
C bus
2
C bus SDI Serial Digital Interface, see “ITU-656” SDRAM Synchronous DRAM SECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz SIF Sound Intermediate Frequency SMPS Switched Mode Power Supply SoC System on Chip SOG Sync On Green SOPS Self Oscillating Power Supply S/PDIF Sony Philips Digital InterFace SRAM Static RAM SRP Service Reference Protocol SSB Small Signal Board STBY STand-BY SVGA 800x600 (4:3) SVHS Super Video Home System SW Software SWAN Spatial temporal Weighted Averaging
Noise reduction SXGA 1280x1024 TFT Thin Film Transistor THD Total Harmonic Distortion TMDS Transmission Minimized Differential
Signalling TXT TeleteXT TXT-DW Dual Window with TeleteXT UI User Interface uP Microprocessor UXGA 1600x1200 (4:3)
Page 57
Circuit Descriptions, Abbreviation List, and IC Data Sheets
V V-sync to the module VCR Video Cassette Recorder VESA Video Electronics Standards
Association VGA 640x480 (4:3) VL Variable Level out: processed audio
output toward external amplifier VSB Vestigial Side Band; modulation
method WYSIWYR What You See Is What You Record:
record selection that follows main
picture and sound WXGA 1280x768 (15:9) XTAL Quartz crystal XGA 1024x768 (4:3) Y Luminance signal Y/C Luminance (Y) and Chrominance (C)
signal YPbPr Component video. Luminance and
scaled color difference signals (B-Y
and R-Y) YUV Component video
EN 57TCM2.0E LA 9.
Page 58
EN 58 TCM2.0E LA9.

9.4 IC Data Sheets

This section shows the internal block diagrams and pin layouts of ICs that are drawn as "black boxes" in the electrical diagrams (with the exception of "memory" and "logic" ICs).

9.4.1 Diagram B, MT5133

Block Diagram
Circuit Descriptions, Abbreviation List, and IC Data Sheets
Pin Configuration
Figure 9-2 Block diagram & pin configuration
I_17950_048.eps
080808
Page 59
Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.4.2 Diagram B, MT5335

Block Diagram
TS
In
CVBS/
YC Input
Component
Analog
Input
HDMI
Rx
Tuner
In
Audio Input
Panel
EN 59TCM2.0E LA 9.
16-bit DDR
ARM
BIM
Audio DSP
Audio I/F
Audio DAC
SPDIF, I

9.4.3 Diagram B, MT8295

2
TS
Demux
VADCx4
TV
Decoder
VDO-In
De-interlace
HDMI In
I/F
Audio
Demod
Audio In
JPEG,MPEG
2-D Graphic
Audio
ADC
Mix and Post
OSD
scaler
LVDS
Processing
DDR
DRAM
Controller
Vplane
scaler
DRAM Bus
IO Bus
CKGEN
JTAG
BScan
IrDA
PCR MS,SD,SM,xD
Serial IF
RTC
S
Figure 9-3 Block diagram
USB2.0
UART
Watchdog
Serial Flash Servo ADC
PWM
NAND Flash
I_17950_049.eps
090508
Block Diagram
Figure 9-4 Block diagram
I_17950_050.eps
090508
Page 60
EN 60 TCM2.0E LA9.

9.4.4 Diagram B, SIL9185

Block Diagram
Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.4.5 Diagram B, TDA9886

TAGC
TOP
14 (15)
VIF2
2 (31) 1 (30)
VIF1
SIF2
24 (27) 23 (26)
SIF1
SUPPLY SIF-AGC
V
P
(1) Not connected for TDA9885. Pin numbers for TDA9885HN and TDA9886HN in parenthesis.
C
VAGC(pos)
C
AGC(neg)
(1)
VAGC
C
BL
VIF-AGCTUNER AGC
VIF-PLL
SINGLE REFERENCE QSS MIXER
INTERCARRIER MIXER
AND AM DEMODULATOR
C
AGC
(6, 12, 13, 14, 17, 19, 25, 28, 29, 32) 13
n.c.AGND
VIF-PLL
VPLL
19 (21) )32( 12)61( 51)71( 61)8( 9
OUTPUT
PORTS
Figure 9-5 Block diagram
filter
RC VCO
I
22 (24)3 (1)
DIGITAL VCO CONTROL AFC DETECTOR
TDA9885 TDA9886
MAD
2
C-BUS TRANSCEIVER
11 (10)
sound intercarrier output
external reference signal
or 4 MHz crystal
REF AFC
FM-PLL DEMODULATOR
12 (11)18 (20)20 (22)
7 (5)
SIOMADSDASCL
DGND
and MAD select
SOUND CARRIER
TRAPS
4.5 to 6.5 MHz
AUDIO PROCESSING
AND SWITCHES
NARROW-BAND
H_17370_074.eps
(18) 17
4 (2)10 (9)
LLPMF2PO1PO
FM-PLL
filter
100807
CVBS
video output: 2 V (p-p) [1.1 V (p-p) without trap]
AUD
(7) 8
DEEM
(3) 5
AFD
(4) 6
I_17930_072.eps
audio output
de-emphasis
network
C
AF
250408
Figure 9-6 Block diagram
Page 61
Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.4.6 Diagram B, V386

EN 61TCM2.0E LA 9.
Block Diagram
RxIN0+
RxIN0-
RxIN1+
RxIN1-
RxIN2+
RxIN2-
RxIN3+
RxIN3-
RxCLKIN+
RxCLKIN-
PWRDWN
Pin Configuration
RxOUT22 RxOUT23 RxOUT24
GND RxOUT25 RxOUT26 RxOUT27
LVDS_GND
RxI N0-
RxI N0+
RxI N1-
RxI N1+ LVDS_VCC LVDS_GND
RxI N2-
RxI N2+
RxCLKI N-
RxCLKI N+
RxI N3-
RxI N3+ LVDS_GND
PLL_GND
PLL_VCC
PLL_GND
PWRDWN
RxCLKOUT
RxOUT0
GND
LVDS to TTL
De-serializer
PLL
V386
8
8
8
1 2 3 4 5 6 7 8
9 10 11 12
13 14
15 16 17 18 19
20
21
22
23
24
25
26
27
28 29
RED
GREEN
BLUE
HSYNC
VSYNC
DATA ENABLE
CONTROL
RxCLKOUT
56 55 54 53
52 51 50 49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30
RxOUT0..27
VCC RxOUT21 RxOUT20 RxOUT19 GND RxOUT18 RxOUT17 RxOUT16 VCC
RxOUT15 RxOUT14 RxOUT13 GND RxOUT12 RxOUT11 RxOUT10
VCC RxOUT9
RxOUT8 RxOUT7 GND RxOUT6
RxOUT5 RxOUT4 RxOUT3
VCC RxOUT2
RxOUT1
56-pin TSSOP
V386
I_17950_051.eps
Figure 9-7 Block diagram & pin configuration
090508
Page 62
EN 62 TCM2.0E LA9.

9.4.7 Diagram B, WM8501

Circuit Descriptions, Abbreviation List, and IC Data Sheets
Figure 9-8 Block diagram
I_17930_073.eps
250408
Page 63
Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.4.8 Diagram B, WT6702

Block Diagram
EN 63TCM2.0E LA 9.
Turbo 8031 MCU
8K bytes code
flash
Internal 256
bytes SRAM
32K Oscillator
RTC
RC
Oscillator
Key Pad ADC
Reset
Processor
Clock
Processor
Clock off &
Wake Up
Watchdog
timer
8051
UART,Timer0,
Timer1
1st SIIC
2nd SIIC
internal bus
3rd SIIC
HV DPMS
Detector Interrupt
Processor
IR Detector
PWM
4 IRQ
Processor
GPIO
Processor
Pin Configuration
VSS
NRST
32KOSCI
VSS
NRST
1 2 3 4
WT6702F_S161
5 6 7
1 2 3 4 5
WT6702F_S200
6 7 8 9 10 11
32KOSCO
32KOSCI
PWM1/GPIOC1 RXD/IRQ3/GPIOB7 TXD/IRQ2/GPIOB6
32KOSCO
PWM1/GPIOC1 RXD/IRQ3/GPIOB7 TXD/IRQ2/GPIOB6
HIN/GPIOB5 VIN/GPIOB4
IRQ1/P1.3/GPIOB3
16
VDD
15
GPIOA0/AD0
14
GPIOA3/AD3/IR
13
GPIOA6/SCL1
12
GPIOA7/SDA1
11
GPIOB0/SCL2
10
GPIOB1/SDA2
98
VDD_RTC
20
VDD
19
GPIOA0/AD0
18
GPIOA3/AD3/IR
17
GPIOA4/SCL3/P1.0
16
GPIOA5/SDA3/P1.1
15
GPIOA6/SCL1
14
GPIOA7/SDA1
13
GPIOB0/SCL2
12
GPIOB1/SDA2
NIV/4BOIPG5BOIPG/NIH
Package Type Package Outline
SOP 16 pin 150mil SOP 20 pin 300mil
SSOP 20 pin 150mil
SOP 24 pin 300mil
VSS
NRST
1 2 3 4 5 6 7 8 9 10 11 12
32KOSCO
32KOSCI
PWM1/GPIOC1
PWM0/GPIOC0 RXD/IRQ3/GPIOB7 TXD/IRQ2/GPIOB6
HIN/GPIOB5
VIN/GPIOB4 IRQ1/P1.3/GPIOB3 IRQ0/P1.2/GPIOB2
Figure 9-9 Block diagram & pin configuration
WT6702F_S240
24
VDD_RTC
23
VDD GPIOA0/AD0
22 21
GPIOA1/AD1
20
GPIOA2/AD2
19
GPIOA3/AD3/IR
18
GPIOA4/SCL3/P1.0
17
GPIOA5/SDA3/P1.1
16
GPIOA6/SCL1 GPIOA7/SDA1
15
GPIOB0/SCL2
14 13
GPIOB1/SDA2
I_17950_052.eps
090508
Page 64
EN 64 TCM2.0E LA9.

9.4.9 Diagram B, MX25L3205

Block Diagram
Circuit Descriptions, Abbreviation List, and IC Data Sheets
SI
CS#, ACC,
WP#,HOLD#
Address
Generator
Data
Register
Mode
Logic
SRAM
Buffer
X-Decoder
State
Machine
Memory Array
Y-Decoder
HV
Generator
additional 4Kb
Sense
Amplifier
Output
Buffer
SO
SCLK Clock Generator
Pin Configuration
HOLD#
VCC
NC PO2 PO1 PO0
CS#
SO/PO7
1 2
3
4 5 6 7
8
16 15 14 13 12 11 10
9
SCLK SI
PO6 PO5 PO4 PO3 GND WP#/ACC
16-PIN SOP (300 mil)
Figure 9-10 Block diagram & pin configuration
I_17950_053.eps
090508
Page 65
Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.4.10 Diagram B, TDA7266

Block Diagram
EN 65TCM2.0E LA 9.
V
CC
IN1
IN2
0.22μF
0.22μF
S-GND
PW-GND
4
7YB-TS
9
12
6ETUM
8
Vref
133
470μF 100nF
+
1
OUT1+
-
OUT1-
-
2
+
+
15
OUT2+
-
OUT2-
-
14
+
Pin Configuration
15 14 13 12 11 10
OUT2+ OUT2­VCC IN2 N.C.
N.C. 9 8 7 6 5 4 3 2 1
S-GND
PW-GND
ST-BY
MUTE
N.C.
IN1
V
CC
OUT1-
OUT1+
I_17950_054.eps
090508
Figure 9-11 Block diagram & pin configuration
Page 66
EN 66 TCM2.0E LA10.
Spare Parts List & CTN Overview

10. Spare Parts List & CTN Overview

For the latest spare part overview, please consult the Philips Service website.

Table 10-1 Sets described in this manual:

CTN Styling Published in:
19PFL5403/60 ME8 3122 785 17952
19PFL5403D/10 ME8 3122 785 17951
19PFL5403S/60 ME8 3122 785 17951
20HFL3330D/10 MG8 3122 785 17951
20PFL3403D/10 MG8 3122 785 17950
22PFL5403/60 ME8 3122 785 17952
22PFL5403D/10 ME8 3122 785 17951
22PFL5403S/60 ME8 3122 785 17952
26PFL3403D/10 MG8 3122 785 17951
26PFL5403/60 ME8 3122 785 17952
26PFL5403D/10 ME8 3122 785 17950
26PFL5403S/60 ME8 3122 785 17952

11. Revision List

Manual xxxx xxx xxxx.0
• First release.
Manual xxxx xxx xxxx.1
• All Chapters: Sets added (see table chapter 10).
• Frontpage: Styling ME8 added.
• Chapter 5: In SAM mode, item “Options” removed.
• Chapter 5: Error 11 removed from error code overview.
• Chapter 6: Wiring diagrams added.
• Chapter 8: Display option codes added.
• Chapter 9: Block diagram added.
• Chapter 10: CTN overview added.
Manual xxxx xxx xxxx.2
• All Chapters: Added Russian sets (xxPFLxxxx/60).
• Chapter 5: Some textual changes in ComPair section.
• Chapter 9: Abbreviation list updated.
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