For servicing CDR775, the set can divided into three parts.
1. The display board (partly) 1 002, the I/O board 1004, the
headphone board (partly) 1002, the IR board (partly) 1002, the ON/
OFF & Standby LED board (partly) 1002 and the CD-out board
(partly) 1002 have to be repaired at component level. The power
supply unit 1003 is available as spare part, but can also be repaired
at component level.
2. The CDR module (containing the CDR loader 81, CDR main board
1001 and loader bracket 82, 83) will be exchanged completely in
case of failure. This complete CDR module is available as spare
part. Defective modules have to be returned for central repair.
3. The CD module (containing the CD loader 131, CD main board
1005 and loader bracket 132) is a new module with VAL1250
loader assy but also a separate CDM and separate loader parts will
be available via service stock. The CD main board can be repaired
at component level.
Also available: Circuit Description " The Basics of Compact Disc
Recordable/Rewriteable". Service code number 4822 725 25242.
ContentsPage
1. Technical Specifications2
2. Warning and Servicing Hints4
3. User Instructions7
4. Mechanical Instructions19
Wiring Diagram CDR19
Wiring Diagram CD loader20
Exploded View CDR21
Exploded View CD loader22
Dismantling Instructions23
5. Electrical and Circuit Diagrams
Diagram PWB
Overall Blockdiagram24
Display Board2626
IR / On/Off &Standby LED Board2727
Headphone / CD-out Board2828
I/O Board2930
Power supply unit3132
CD-Mainboard 1A3337/38
CD-Mainboard 1B3437/38
CD-Mainboard 1C3537/38
CD-Mainboard 23637/38
Copyright reserved 1999 Philips Consumer Electronics B.V. Eindhoven, The
Netherlands. All rights reserved. No part of this publication may be reproduced,
stored in a retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Published by RH 9969 Service DPS HasseltPrinted in the NetherlandsSubject to modification5 3104 125 40030
Page 2
GB 2CDR7751.
Technical Specifications CDR775
1.Technical Specifications CDR775
1.1General
Mains voltage: all range version 84-
230V (/00, /01C, /06, /
13, /14)
: USA version 117V/
60Hz (/17)
Mains frequency: 50-60 Hz
Power consumption: 12W
DC output: +5V ± 10%, 50mA
max.
1.2Input/output
1.2.1Line output (CDR & CD)
Output level\: 2Vrms at 0dB
Output resistance: 200
Number and height of feet: 4x11mm foiled
Apparatus tray closed (WxDxH): 435x305x75mm
(without feet)
Weight without packaging: 3.2kg
Weight with packaging: 4.2kg
Ω
Page 4
GB 4CDR7752.
Warnings and Servicing Hints
2.Warnings and Servicing Hints
GB
WARNING
All ICs and many other semi-conductors are
susceptible to electrostatic discharges (ESD).
Careless handling during repair can reduce
life drastically.
When repairing, make sure that you are
connected with the same potential as the
mass of the set via a wrist wrap with
resistance.
Keep components and tools also at this
potential.
F
ATTENTION
Tous les IC et beaucoup d'autres semiconducteurs sont sensibles aux décharges
statiques (ESD).
Leur longévité pourrait être considérablement
écourtée par le fait qu'aucune précaution
n'est prise a leur manipulation.
Lors de réparations, s'assurer de bien être
relié au même potentiel que la masse de
l'appareil et enfiler le bracelet serti d'une
résistance de sécurité.
Veiller a ce que les composants ainsi que les
outils que l'on utilise soient également a ce
potentiel.
D
Alle IC und viele andere Halbleiter sind
empfindlich gegen elektrostatische
Entladungen (ESD).
Unsorgfältige Behandlung bei der Reparatur
kann die Lebensdauer drastisch vermindern.
Sorgen sie dafür, das Sie im Reparaturfall
über ein Pulsarmband mit Widerstand mit
dem Massepotential des Gerätes verbunden
sind.
Halten Sie Bauteile und Hilfsmittel ebenfalls
auf diesem Potential.
GB
Safety regulations require that the set be restored to its original condition
and that parts which are identical with those specified be used.
NL
Veiligheidsbepalingen vereisen, dat het apparaat in zijn oorspronkelijke
toestand wordt terug gebracht en dat onderdelen, identiek aan de
gespecifieerde worden toegepast.
F
Les normes de sécurité exigent que l'appareil soit remis a l'état d'origine et
que soient utilisées les pièces de rechange identiques à celles spécifiées.
WARNUNG
NL
WAARSCHUWING
Alle IC's en vele andere halfgeleiders zijn
gevoelig voor elektrostatische ontladingen
(ESD).
Onzorgvuldig behandelen tijdens reparatie
kan de levensduur drastisch doen
verminderen.
Zorg ervoor dat u tijdens reparatie via een
polsband met weerstand verbonden bent met
hetzelfde potentiaal als de massa van het
apparaat.
Houd componenten en hulpmiddelen ook op
ditzelfde potentiaal.
I
AVVERTIMENTO
Tutti IC e parecchi semi-conduttori sono
sensibili alle scariche statiche (ESD).
La loro longevita potrebbe essere fortemente
ridatta in caso di non osservazione della piu
grande cauzione alla loro manipolazione.
Durante le riparazioni occorre quindi essere
collegato allo stesso potenziale che quello
della massa dell'apparecchio tramite un
braccialetto a resistenza.
Assicurarsi che i componenti e anche gli
utensili con quali si lavora siano anche a
questo potenziale.
D
Bei jeder Reparatur sind die geltenden Sicherheitsvorschriften zu beachten.
Der Originalzustand des Gerats darf nicht verandert werden.
Fur Reparaturen sind Original-Ersatzteile zu verwenden.
I
Le norme di sicurezza esigono che l'apparecchio venga rimesso nelle
condizioni originali e che siano utilizzati pezzi di ricambiago idetici a quelli
specificati.
SHOCK, FIRE HAZARD SERVICE TEST:
CAUTION: After servicing this appliance and prior to returning to customer, measure the resistance between
either primary AC cord connector pins (with unit NOT connected to AC mains and its Power switch ON), and the
face or Front Panel of product and controls and chassis bottom,
Any resistance measurement less than 1 Megohms should cause unit to be repaired or corrected before AC
power is applied, and verified before return to user/customer.
Ref.UL Standard NO.1492.
NOTE ON SAFETY:
Symbol
: Fire or electrical shock hazard. Only original parts should be used to replace any part with symbol
Any other component substitution(other than original type), may increase risk or fire or electrical shock hazard.
“Pour votre sécurité, ces documents
doivent être utilisés par des
spécialistes agrées, seuls habilités à
réparer votre appareil en panne.”
CL 96532086_021.eps
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Page 5
Warnings and Servicing Hints
SERVICING HINTS
In the set, chip components have been applied. For disassembly and assembly check the figure below.
GB 5CDR7752.
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Page 6
GB 6CDR7752.
Warnings and Servicing Hints
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User instructions
3.User instructions
GB 7CDR7753.
Page 8
GB 8CDR7753.
User instructions
Page 9
User instructions
GB 9CDR7753.
Page 10
GB 10CDR7753.
User instructions
Page 11
User instructions
GB 11CDR7753.
Page 12
GB 12CDR7753.
User instructions
Page 13
User instructions
GB 13CDR7753.
Page 14
GB 14CDR7753.
User instructions
Page 15
User instructions
GB 15CDR7753.
Page 16
GB 16CDR7753.
User instructions
Page 17
User instructions
GB 17CDR7753.
Personal notes:
Page 18
GB 18CDR7753.
Personal notes:
User instructions
Page 19
Mechanical instructions
4.Mechanical instructions
Wiring diagram
WIRING DIAGRAM CDR775
8006
3104 157 1099
1000
114
8001
3104 157 1124
I/O BOARD
3104 128 0599
8002
3104 157 10962
CD OUT
3104 128 0590
17
1502
11
0205
1
GB 19CDR7754.
Pin 1 indicated by All Wires are 1/1, except flex 8001, 8005 and 8007
The purpose of the dealer mode is to prevent people taking out
the CD inside the player at exhibitions, showrooms etc.. This
mode disables the open/close function of the player.
The dealer mode can be switched on and off pressing keys
[OPEN/CLOSE] and [STOP] of the CDR player simultaneously
while switching on the unit. The dealer mode is stored in the
flash memory and can only be changed by executing the above
actions.
6.2Dealer diagnostics
DEALER DIAGNOSTICS
(status of player)
If power ON,
switch power OFF
Press <REWIND> + <FFWD>
simultaneously and switch
ON unit
6.2.2Requirements to perform the test
•Working keyboard to start up the test.
•Working local display to check the output messages.
Display blinks
“BUSY”
during test
NO
Set OK?
YES
Set displays
“
PASSED
To end test, switch OFF unit
6.2.1Description
The intention of the dealer diagnostics is to give an indication
of the CDR player status. An inexperienced, even nontechnical dealer will/can perform the test. Tests are executed
automatically without need for external tools or disassembly of
the unit. This test checks the CDR main board using the same
tests as the electrical service diagnostics program. Only the
result of the test, "PASSED" or "ERROR", will be shown on the
display. Pressing keys [F FWD] and [REWIND] simultaneously
while switching on the unit, starts the test. Switching off the unit
ends the test.
”
Figure 6-1
Set displays
“ERROR”
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Page 40
GB 40CDR7756.
6.3Electrical service diagnostics
ELECTRICAL SERVICE DIAGNOSTICS
(software versions, test for defective components)
If power ON,
switch power OFF
Load CD-DA disc (SBC444A)
Press <PLAY> + <F FWD>
simultaneously and switch ON unit
PLAYER
INFORMATION
Display :
"PLAYER ID"
"SW VERSION BACK END"
"SW VERSION CDR LOADER"
(CDR775
CDR MAIN
BOARD TEST
Display :
PASS OR FAIL
Display :
PASS OR FAIL
Display :
PASS OR FAIL
Display :
PASS OR FAIL
Display :
PASS OR FAIL
Display :
PASS OR FAIL
"SW VERSION CD LOADER"
"DTST1"
DRAM test (7702)
"DTST2"
FLASH CHECKSUM test (7702)
"DTST3"
FLASH ERASE test (7702)
"DTST4"
CODEC test (7702)
"DTST5"
CDR LOADER
COMMUNICATION test
"DTST6"
*
CD LOADER
COMMUNICATION test
* FOR CDR775 ONLY
)
ABORT TEST
ABORT TEST
ABORT TEST
ABORT TEST
ABORT TEST
Diagnostic Software
Press <F FWD>
Press <F FWD>
Press <F FWD>
Press <F FWD>
Press <F FWD>
ABORT TEST
Press <F FWD>
ABORT TEST
Press <F FWD>
LOADER TESTS
CDR LOADER TEST
CD-DA disc must be loaded
Display shows current disc time
Test OK?
YES
CD LOADER TEST *
CD-DA disc must be loaded
Display shows current disc time
Test OK?
YES
DISPLAY TEST
DISPLAY TEST
Display segments blink at f=1kHz
KEYBOARD &
RC TEST
KEYBOARD & RC TEST
Display shows name of pressed keys
Press <F FWD>
NO
Display :
or
or
* FOR CDR775 ONLY
NO
Display :
or
or
"BERR1"
"NO CDDA"
"NO DISC"
Press <F FWD>
"BERR2"
"NO CDDA"
"NO DISC"
Press <F FWD>
Tests OK?
YES
NO
"DERRn"
Display :
n = failed test
Display next
failed test
Figure 6-2
To end test, switch OFF unit
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Page 41
Diagnostic Software
FOCUS TEST
Display shows
“ BUSY”
Visual inspection
TRAY TEST
Visual inspection
Display shows
“ OPENED”
even if tray is blocked
<
OPEN
>
<
CLOSE
>
SLEDGE TEST
Visual inspection
<FWD><REWIND>
MECHANICAL SERVICE DIAGNOSTICS
(test for defective components)
Press <PLAY/PAUSE> + <STOP>
simultaneously and switch
ON unit
If power ON,
switch power OFF
To end test, switch OFF unit
Display shows
“ BUSY”
CL96532086_026.eps
080999
GB 41CDR7756.
6.3.1Description
The intention of the electrical service diagnostics is to show the
software versions present in the player and to direct the dealer
towards defective internal units. The units are : the CDR main
board, the CDR loader, the CD loader in case of a CDR775 and
the keyboard/display board. A sequence of tests is executed
automatically. Some of the tests can be aborted or skipped
without the result being taken into account. External tools or
disassembly of the unit is not necessary to get the diagnostic
information. Pressing keys [PLAY/PAUSE] and [F FWD]
simultaneously while switching on the unit, starts the test.
Switching off the unit ends the test.
6.3.2Requirements to perform the test
•Working keyboard to start up the test.
•Working local display to check the output messages.
•A CD-DA disc with a minimum of 3 tracks in all trays to
perform the disc test.
6.3.3Description of the tests
Player information
In this part of the test the following important information can be
checked without removing the cover :
•Recorder ID.
•SW-version back end of player.
•SW-version CDR loader.
•SW-version CD loader (only for CDR775).
CDR main board test
[F FWD] key. The message "DERRn" will be displayed with n
indicating the faulty test number.
If one of the tests is aborted with the [F FWD] key, no error
message will be displayed for this test. The flash data erase
test ("DTST3") can not be aborted !
The CDR main board test consists out of :
disc test is executed to check focus control, disc motor control,
radial control and jump grooves control. The disc test is
performed by audio play-back of 5 seconds at the beginning,
middle and end of the disc.
CDR loader test
During the test, the current disc time is shown. In case of an
error the message "BERR1" will be displayed and the [F FWD]
key must be pressed to continue with the following test.
Pressing the [F FWD] key also aborts this test.
CD loader test
For CDR775 only. During the test, the current disc time is
shown. In case of an error the message "BERR2" will be
displayed and the [F FWD] key must be pressed to continue
with the following test. Pressing the [F FWD] key also aborts
this test.
Display test
All segments will blink at a frequency of 1 Hz. Pressing the [F
FWD] key will start the next test because the user has to check
for himself if all segments work properly.
Keyboard and remote control tests
The test will give the user the ability to test every key without
executing the function assigned to it. Therefore, the user needs
to press every key on the keyboard and the remote control. The
display will show the name of the key being pressed. Pressing
more than one key at once will give an unpredictable result
except for the service combinations : [PLAY/PAUSE] + [STOP],
[PLAY/PAUSE] + [F FWD], [F FWD] + [REWIND], [ERASE] +
[RECORD], [PLAY/PAUSE] + [RECORD], [OPEN/CLOSE] +
[PROGRAM].
6.4Mechanical service diagnostics
DRAM test
Display : "DTST1". The DRAM used for buffer management is
tested by writing, reading and verifying test patterns.
Flash checksum test
Display : "DTST2". This test checks the checksum of the
player's SW stored in the flash.
Flash data erase
Display : "DTST3". During this test, all temporary information
(CDtxt) in the flash is erased.
CODEC (ADC/DAC) test
Display : "DTST4". This test checks the CODEC IC by writing,
reading and verifying test patterns. The test is not applicable for
CDR950.
CDR communication test
Display : "DTST5". The communication between the host
processor (DASP) and the CDR loader via the DSA-R-bus is
tested.
CD communication test
Display : "DTST6"). The communication between the host
processor (DASP) and the CD loader is tested. The test is only
applicable for CDR775.
Loader tests
These tests determine if the CDR loader and the CD loader in
case of a CDR775 work correctly. A CD-DA disc with a
minimum of 3 tracks needs to be inserted in both loaders. A
Figure 6-3
6.4.1Description
No external tools are required to perform this test. The cover
needs to be removed because the user has to check the
movements of the tray, focus and sledge visually. Pressing
keys [PLAY/PAUSE] and [STOP] simultaneously while
switching on the unit, starts the test. Switching off the unit ends
the test. In case of a CDR775, one can check the CD loader
mechanics in the same way by pressing the above key
combination on the CD player keys.
Page 42
GB 42CDR7756.
Diagnostic Software
6.4.2Requirements to perform the test
•Working keyboard to cycle through the tests and to start up
the test.
•Working local display to check the output messages.
6.4.3Description of the tests
Focus control test
The focussing lens is continuously moving up and down. The
display reads "BUSY".
Sledge control test
After pressing [F FWD] the sledge continuously moves up and
down. Pressing [REWIND] stops the sledge at the position it is
in and the focus control test resumes. The display reads
"BUSY".
Tray control test
This test starts from within the focus control test routine.
Pressing [OPEN/CLOSE] moves the tray in or out. In the tray
open position one can initiate focus and sledge tests by
pressing [F FWD]. One has to stop these tests pressing
[REWIND] before it is possible to close the tray again.
Depending on the action the display reads "OPEN",
"OPENED", "CLOSE" or "BUSY".
6.5DC-erase service mode
6.5.1Description
This test is initiated by pressing [ERASE] and [RECORD]
simultaneously while switching on the unit. The player will
erase a complete CD-RW disc (including PMA and ATIP lead
out area) at speed N=2. The display shows the countdown of
the remaining time required for the operation to complete. The
format is "ER mm:ss", where "mm" are the remaining minutes
and "ss" the remaining seconds. After completion the message
"PASSED" is shown, and the player has to be switched off and
on again to start up in normal operating mode. Switching off the
unit before completion of the test, leaves the disc in an
unpredictable state. In such case only a complete DC-erase
procedure can recover the CD-RW disc.
6.5.2Requirements to perform the test
•Functional CDR player.
•A CD-RW audio disc must be present in the tray.
DC ERASE SERVICE MODE
(erasement of complete CD-RW)
Load CD-RW disc
<ERASE> + <RECORD>
simultaneously and switch
mm
ss:remaining seconds
TOTAL
illuminated
when the erase function is
Press
ON unit
Display shows:
“
ER mm:ss
:remaining minutes
and
Display shows:
“
PASSED
completed
ERROR
“
if DC ERASE fails
REM
”
are also
”
”
To end test, switch OFF unit
CL96532086_027.eps
Figure 6-4
080999
Page 43
Faultfinding trees
7.Faultfinding trees
7.1CDR-Module
NO DISC LOADED
SWITCH ON POWER
GB 43CDR7757.
STBY LED?
YES
PRESS <DISPLAY>
DISPLAY?
YES
DISPLAY:
"INSERT DISC"
YES
NO
CHECK:
• MAINS, MAINS CABLE
• POWER SUPPLY (SEE FAULT FINDING GUIDE PSU)
⇒
WIRING
⇒
ON/OFF SWITCH
⇒
FUSES
⇒
NO
• DISPLAY (SEE FAULT FINDING GUIDE DISPLAY BOARD)
CHECK:
NO
• WIRING
• POWER SUPPLY VOLTAGES
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
VOLTAGES
⇒
WIRING
⇒
SUPPLY VOLTAGES
⇒
CLOCK SIGNAL 8MHz
⇒
CONTROL SIGNALS
⇒
KEYBOARD
⇒
STANDBY LED
⇒
ELECTRICAL SERVICE DIAGNOSTICS:
DISPLAY TEST, KEYBOARD TEST
"BERRn"
ERROR OCCURS
"DERRn"
PRESS
<OPEN/CLOSE>
TRAY?
YES
INSERT DISC
PRESS <OPEN/CLOSE>
CD-DA DISC
LOADED?
SEE CD-DA DISC
FAULT FINDING
CHECK:
• DISPLAY BOARD (SEE FAULT FINDING GUIDE DISPLAY BOARD)
⇒
NO
• MECHANICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF ERROR OCCURS
SEE CD-R DISC
FAULT FINDING
WIRING
⇒
SUPPLY VOLTAGES
⇒
CLOCK SIGNAL 8MHz
⇒
CONTROL SIGNALS
⇒
KEYBOARD
⇒
ELECTRICAL SERVICE DIAGNOSTICS:
DISPLAY TEST, KEYBOARD TEST
CD-R DISC
LOADED?
YESYES
NONO
CD-RW DISC
LOADED?
YES
SEE CD-RW DISC
FAULT FINDING
Figure 7-1
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GB 44CDR7757.
CD-DA DISC LOADED
DISC
DETECTION &
READING?
YES
DISPLAY:
“ CD”
&
T.O.C. INFO?
YES
Faultfinding trees
CHECK:
• WIRING
• POWER SUPPLY VOLTAGES
NO
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
"BERRn"
CHECK:
• DISC: DIRT, SCRATCHES, DAMAGED...
NO
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
"BERRn"
ERROR OCCURS
ERROR OCCURS
"DERRn"
"DERRn"
PRESS <PLAY>
ANALOG
AUDIO
OUT?
YES
DISTORTION?
NO
HEADPHONE?
YES
DIGITAL
AUDIO
OUT?
YES
CHECK:
AUDIO CONNECTIONS & CABLES
•
I/O BOARD
•
⇒
FLEX CONNECTION
⇒
+5V (pin 8 conn. 1000)
⇒
NO
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
CHECK:
YES
NO
NO
AUDIO CONNECTIONS & CABLES
•
I/O BOARD
•
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
CHECK:
WIRING OF HEADPHONE/IR BOARD
•
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
CHECK:
AUDIO CONNECTIONS & CABLES
•
I/O BOARD
•
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
KILL VOLTAGE (pin 7 conn. 1000):
-8V DURING PLAY
⇒
KILL TRANSISTORS 7006,7007,7008, 7009
PLAY AUDIO SIGNALS DISC TRACK 15:
⇒
SIGNAL OF 5.4 VPP ON PINS 1 AND 3 OF CONN.
1000
"BERRn"
⇒
⇒
"BERRn"
"BERRn"
⇒
⇒
⇒
"BERRn"
ERROR OCCURS
FLEX CONNECTION
+5V (pin 8 conn. 1000)
ERROR OCCURS
ERROR OCCURS
FLEX CONNECTION
+5V (pin 8 conn. 1000)
DIGITAL OUT TRANSFORMER 5450, IC7005
ERROR OCCURS
"DERRn"
"DERRn"
"DERRn"
"DERRn"
PLAY BACK OF CD-DA
DISCS OK
Figure 7-2
CL 96532076_017.eps
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Page 45
Faultfinding trees
CD-R DISC LOADED
DISC
DETECTION &
READING?
YES
DISPLAY:
“ CD R”
OPC INFO?
&
YES
CHECK:
NO
• WIRING
• POWER SUPPLY VOLTAGES
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
NO
"BERRn"
DISPLAY:
T.O.C. INFO?
YES
“ CD”
&
ERROR OCCURS
"DERRn"
CHECK:
NO
• DISC: DIRT, SCRATCHES, DAMAGED...
• ELECTRICAL SERVICE DIAGNOSTICS:
REPLACE CDR MODULE IF
OR
"BERRn"
ERROR OCCURS
GB 45CDR7757.
"DERRn"
CD-R DISC PARTIALLY
RECORDED OR EMPTY
START MANUAL
RECORDING FROM
ANALOG SOURCE
LEVEL
ADJUSTABLE?
YES
START RECORDING
FROM DIGITAL
SOURCE
DIGITAL IN?
OPTICAL IN?
YES
FINALISED CD-R DISC
LOADED
SEE CD-DA DISC
FAULT FINDING
CHECK:
AUDIO CONNECTIONS & CABLES
•
NO
• DISPLAY BOARD (SEE FAULT FINDING GUIDE DISPLAY BOARD)
⇒ TESTPOINTS 23, 24 : ANALOG OUTPUT?
⇒ POWER SUPPLY: PIN 8→12V
⇒ REPLACE OPAMP 7120
AUDIO?
YES
NO
DISTORTION?
NO
AUDIO
CD OUT PCB?
YES
PLAYBACK CD
MODULE OK
YES
NO
• DAC 7309
• OPAMP 7120
• FLEX TO CDR MAINBOARD
• FLEX TO CD OUT BOARD
• CHECK I/O BOARD, CD OUT BOARD
Figure 7-6
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Faultfinding Guide
8.Faultfinding Guide
GB 49CDR7758.
8.1Display Board
8.1.1Description of display board
General description
The display board has three major parts : the FTD (Fluorescent
Tube Display), the display controller TMP87C874F and the
keyboard. The display controller is controlled by the DASP
master processor on the CDR main board. The communication
protocol used is I2C. So all the information between DASP and
display controller goes via the SDA or I2C DATA and SCL or
I2C CLK lines. Communication is always initiated by the DASP
on the CDR main board. Unlike the previous generations of
CDR players, the interrupt generated by the display controller
at key-press or reception of remote control is not used. Instead,
the DASP polls the display controller for these events.
BLOCK DIAGRAM
TMP87C874F
64 63 62 61 60 59 58 57 56 55254 53
I/O PORT8 (VFT)
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O PORTD (VFT)I/O PORT9 (VFT)
VKK
I/O PORT0
3
1
DATA MEMORY
TIMER/COUNTER
8 BIT A/D
CONVERT.
651516
I/O PORT7 (VFT)
( RAM )
512X8 BIT
16 BIT
CLOCK/TIMING CONTROLLER
VSS1
RESETN
XOUT
XIN
79819
10
52
PROGR MEMORY
( ROM )
8kX8 BIT
C P U
INTERRUPT
CONTROLLER
( I/O PORT2 )
P22
P21
TEST1
P20
13
14121117 1820 21 22
Display controller TMP87C874F
TMP87C874F (IC7104) is a high speed and high performance
8-bit single chip microprocessor, containing 8-bit A/D
conversion inputs and a VFT (Vacuum Fluorescent Tube)
driver. In this application, its functions are :
•slave microprocessor.
•FTD driver.
•generates the square wave for the filament voltage
required for an AC FTD.
•generates the grid and segment scanning for the FTD.
•generates the scanning grid for the key matrix.
•input for remote control.
All the communication runs via the serial bus interface I2C. The
display controller uses an 8MHz resonator as clock driver.
41
42434445464748495051
I/O PORT6 (VFT)
I/O PORT5
I/O PORT4
2
SDA
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SCK0
PROGRAM
COUNTER
TIMER/COUNTER
INT0
INT1
8 BIT
I/O PORT1
VDD
VAREF
VASS
I C
PORT3
SCL
23 244
PIN DESCRIPTIONS
INT0external interrupt input 0
INT1external interrupt input 1
RESETNreset signal input, active low
SCLI2C-bus serial clock input/output
SDAI2C-bus serial data input/output
TESTtest pin, tied to low
VAREFanalog reference voltage input
VASSanalog reference ground
VDD+5V
VKKVFT driver power supply
VSSground
XIN, XOUTresonator connecting pins for high-frequency clock
Figure 8-1
CL 96532076_028.eps
290799
Page 50
GB 50CDR7758.
s
9
Faultfinding Guide
8.1.2Test instructions
Supply voltages
The display board receives several voltages via connector
1119 (and connector 1121 for CDR570/930).
•VFTD : -38V ±5% measured at pin 2 of conn. 1119.
•VDC1-VDC2 : 3V8
±10
% measured between pin 1 and 3 of
conn. 1119.
•+5V : +5V ±5% measured at pin 10 of conn. 1119 (pin 4 of
conn. 1121 for CDR770).
Voltages VFTD, VDC1 and VDC2 are produced in the power
supply unit and sent to the display board via the CDR main
board. The +5V voltage is produced on the CDR main board as
D5V.
Clock signal
As clock driver for the display controller, a resonator of 8 MHz
(1110) is used. The signal can be measured at pins 8 and 9 of
the display controller : 8 MHz ±5%.
Control signals
RESET
The reset signal comes via pin 4 of conn. 1119 from the DASP
master processor on the CDR main board (SYS_RESET). The
reset is low active. It should be kept low during power up for at
least 3 machine cycles with supply voltage in operating range
and a stable clock signal (1 machine cycle = 12 x 1/Fc (8 MHz)
sec.). During normal operation, the reset should be high (3V3).
The high signal is 3V3 because the DASP operates on 3V3.
I2C DATA/I2C CLK
These lines connect to the DASP master processor via
respectively pin 5 and pin 7 of conn. 1119 (pin 5 of conn. 1119
and pin 1 of conn. 1121 for CDR570/930). When there is no
communication, they should have the high level (+5V). The
oscillogram below gives an indication of how these signals
should look like.
Grid lines
Level and timing of all grid lines, G1-->G15, can be checked
either at the FTD itself or at the display controller. Grid lines
G13, G14 and G15 each have an extra current amplifier in line
: T7203 for G13, T7204 for G14 and T7100 for G15. A typical
grid line signal shows in the oscillogram below.
PM3392A
+4V
0V
38V
CH1!10.0 V= MTB1.00ms ch1+
Figure 8-3 ‘Gridline’
Segment lines
Level and timing of all segment lines, P1-->P21 (P1-->P20 for
CDR770), can be checked either at the FTD itself or at the
display controller. The data on these segment lines however,
depends on the characters displayed. The oscillogram below
shows a segment line with data. A segment line without data
maintains a -38V level.
CL 96532076_024.ep
29079
PM3392A
+5V
I2C DATA
0V
+5V
I2C CLK
0V
CH1!2.00 V=
CH2 2 V= MTB10.0ms ch1+
CL 96532076_025.eps
Figure 8-2 ‘I2C signals’
FTD drive lines
Filament voltage
Should measure 3.8V ±10% (=VDC1-VDC2) between pins 1-23 and pins 45-46-47 (pins 1-2 and pins 48-49 for CDR770) of
the FTD (1113).
290799
PM3392A
+5V
0V
-38V
CH1!10.0 V= MTB1.00ms ch1+
CL 96532076_027.eps
Figure 8-4 ‘Segment line’
Key matrix lines
The lines connected to pins 34, 35, 36 and 37 of the display
controller act as matrix scanners. Without a key pressed, they
maintain a low level. As soon as a key is pressed, the scanning
line connected to that key puts out a scanning signal, which
should look like the oscillogram below. This scanning signal
goes via the pressed key to I/O port 4 of the display controller
(pins 28 to 33). The display controller can now determine which
key has been pressed. Without a key pressed, pins 28 to 33 of
the display controller maintain a high level (+5V).
290799
Page 51
Faultfinding Guide
PM3392A
CH1!2.00 V= MTB20.0ms ch1+
1
+5V
0V
CL 96532076_021.eps
290799
PM3392A
+5V
0V
CH1!2.00 V= MTB5.00ms ch1+
CL 96532076_026.eps
Figure 8-5 ‘Key matrix scan line’
Easy jog knob
Rotary operation
The easy jog knob (1050) incorporates a whole heap of user
control possibilities in just one knob. Without the knob being
operated, pin 1 and 3 of the knob (and thus pin 16 and 17 of the
display controller), maintain the +5V level. Turning the knob
clockwise briefly connects pin 1 to GND followed by pin 3.
290799
GB 51CDR7758.
The pulses created this way arrive at pin 16 and 17 of the
display controller. The first pulse to arrive tells the controller the
direction of the rotation. Counting the pulses reveals the
amount of rotation. Combining and decoding this information,
the display controller will execute the appropriate task.
Push button operation
This button connects to the key matrix lines and thus the
operation is identical to the ordinary keys. Without being
pressed, pin 4 of the easy jog maintains the low level, pin 5 the
high level. When pressed the scanning signal goes through the
closed contact of pins 4 and 5, and can be checked at both
pins.
IR receiver - remote control
In the CDR570/930 the IR receiver TSOP1736 (6101) is
mounted on the display board. In the CDR770 that same IR
receiver (6200) is mounted on a small board together with the
headphone socket. In the CDR775 the IR receiver (6200) is
mounted on its own small board. In all versions the IR receiver
connects to the display controller. The signal coming from the
receiver can be checked at pin 22 of the display controller. This
signal is normally high (+5V). When the remote control is being
operated, pulses mixed in with the +5V can be measured. The
oscillogram gives an indication of how the signal looks like with
the RC being operated.
PM3392
Pin1
Pin3
CH1 5.00 V=
CH2 5.00 V= MTB20.0ms- 1.92dv ch2-
CL 96532076_023.eps
290799
Figure 8-6 ‘Turn clockwise’
Turning the knob anti-clockwise briefly connects pin 3 to GND
followed by pin 1.
PM3392
Pin1
Pin3
Figure 8-8 ‘IR receiver signal’
Figure 8-7 ‘Turn anti-clockwise’
CH1 5.00 V=
CH2 5.00 V= MTB20.0ms- 1.92dv ch2-
CL 96532076_022.eps
290799
Page 52
GB 52CDR7758.
8.1.3Display board troubleshooting guide
SWITCH POWER ON,
EXIT STAND BY
MODE
Faultfinding Guide
CHECK :
DISPLAY?
YES
KEY
FUNCTIONS?
YES
NO
NO
• SUPPLY VOLTAGES
⇒ -38V ±5% at conn. 1119-2
⇒ 3V8 ± 10% between conn. 1119-1 and 1119-3
⇒ +5V ± 5 % at conn. 1119-10 (1121-4 for CDR570/930)
• CLOCK SIGNAL
⇒ 8Mhz at pins 8, 9 of IC7104
• CONTROL SIGNALS
⇒ RESETN 3V3 (high) at conn.1119-4 after start up
⇒ I2C DATA at conn. 1119-5
⇒ I2C CLK at conn. 1119-7 (1121-1 for CDR570/930)
• FTD DRIVE LINES
⇒ Filament voltage 3V8 ± 10% between pins 1-2-3 and
pins 45-46-47 (pins 1-2 and pins 48-49 for CDR
570/930) of the FTD (1113)
⇒ Grid lines (see test instructions)
⇒ Segment lines (see test instructions)
• ELECTRICAL SERVICE DIAGNOSTICS - Local display test
CHECK:
• KEY MATRIX LINES (see test instructions)
• ELECTRICAL SERVICE DIAGNOSTICS – Keyboard test
• EASY JOG KNOB (see test instructions)
REMOTE
CONTROL?
YES
DISPLAY BOARD
OK
NO
CHECK:
• IR RECEIVER signal at pin 22 of IC7104 (see test instructions)
• ELECTRICAL SERVICE DIAGNOSTICS – Remote control test
Figure 8-9 ‘Display board troubleshooting’
CL 96532076_020.eps
290799
Page 53
Faultfinding Guide
Rref
R Frequency Standby
Voltage feedback Input
Error Amp Output
R Power Standby
Soft-Start/Dmax/
Voltage Mode
Sync Input
Overvoltage Protection (OVP)
Current Sense Input
Demag. Detection
Foldback Input
107
CT
89
6
5
11
12
Output
Gnd
VC
VCC
3
4
2
14
13
15
116
CL 96532076_030.eps
290799
GB 53CDR7758.
8.2Power Supply Unit 20PS317
8.2.1Description of PSU 20PS317
MOSFET 7125 is used as a power switch controlled by the
controller IC7110. When the switch is closed, energy is
transferred from mains to the transformer. This energy is
supplied to the load when the switch is opened. Through
control of the switch-on time, the energy transferred in each
Rectifier
6129
Demagnet.
S
RQ
latch
Overvoltage
6102
Mgmt
Buffer
Mgmt
MAINS
7110
Current
Sense
Input
2.5V
Error
Amplifier
Voltage
Feedback
Lightning
Protection
+
-
OSC.
Output
Sense
+
Soft-Start
Control
EMI
FILTER
Supply Init
Vc
Out
Gnd
2121
7125
6132
Rsense
7
9
cycle is regulated so that the output voltages are independent
of load or input voltage variations. The controlling device
MC44603 is an integrated pulse width modulator. A clock
signal initiates power pulses at a fixed frequency. The
termination of each output pulse occurs when a feedback
signal of the inductor current reaches a threshold set by the
error signal. In this way the error signal actually controls the
peak inductor current on cycle-by-cycle basis.
17
15
11
13
10
14
16
18
6210/6211
6230/6232
6240
6250
6220
2250
2220
2210
2230
7249
2240
7251
6201
7252
7221
5131
2
5
7200
+5V
+12V
-8V
VFTD
VDC2
VDC1
Description of controller MC44603
The MC44603 is an enhanced high performance controller that
is specifically designed for off-line and DC-to-DC converter
applications. This device has the unique ability of automatically
changing operating modes if the converter output is
overloaded, unloaded or shorted. The MC44603 has several
distinguishing features when compared to conventional SMPS
controllers. These features consist of a foldback facility for
overload protection, a standby mode when the converter output
is slightly loaded, a demagnetization detection for reduced
switching stresses on transistor and diodes, and a high current
totem pole output ideally suited for driving a power MOSFET. It
can also be used for driving a bipolar transistor in low power
converters. It is optimised to operate in discontinuous mode but
can also operate in continuous mode. Its advanced design
allows use in current mode or voltage mode control
applications.
REGULATION
Figure 8-10 ‘Blockdiagram PSU 20PS317’
7201
Pin connections
Figure 8-11
GND
GND
CL 96532076_029.eps
290799
Page 54
GB 54CDR7758.
Pin function description
Faultfinding Guide
PinNameDescription
1VCCThis pin is the positive supply of the IC. The operating voltage range after start-up is 9.0 to 14.5 V.
2VCThe output high state (VOH) is set by the voltage applied to this pin.
3OutputPeak currents up to 750 mA can be sourced or sunk, suitable for driving either MOSFET or bipolar transistors.
4GndThe groundpin is a single return, typically connected back to the power source.
5Foldback InputThe foldback function provides overload protection.
6Overvoltage
Protection
7Current Sense
When the overvoltage protection pin receives a voltage greater than 2.5V, the device is disabled and requires a
complete restart sequence.
A voltage proportional to the current flowing into the power switch is connected to this input.
Input
8Demagnetisation
Detection
A voltage delivered by an auxiliary transformer winding provides to the demagnetisation pin an indication of the
magnetisation state of the flyback transformer. A zero voltage detection corresponds to complete core
saturation.
9Synchronisation
Input
The synchronisation input pin can be activated with either a negative pulse going from a level between 0.7V and
3.7V to Gnd or a positive pulse going from a level between 0.7V and 3.7V up to a level higher than 3.7V. The
oscillator runs free when Pin 9 is connected to Gnd.
10C
T
The normal mode oscillator frequency is programmed by the capacitor CT choice together with the Rref
resistance value. CT, connected between Pin 10 and Gnd, generates the oscillator sawtooth.
11Soft-
Start/Dmax/Volta
A capacitor, resistor or a voltage source connected to this pin limits the switching duty-cycle. This pin can be
used as a voltage mode control input. By connecting Pin 11 to Ground, the MC44603 can be shut down.
ge-Mode
12RP StandbyA voltage level applied to the RP Standby pin determines the output power level at which the oscillator will turn
into the reduced frequency mode of operation (i.e. standby mode). An internal hysteresis comparator allows to
return in the normal mode at a higher output power level.
13E/A OutThe error amplifier output is made available for loop compensation.
14Voltage
Feedback
This is the inverting input of the Error Amplifier. It can be connected to the switching power supply output
through an optical (or other) feedback loop.
15RF StandbyThe reduced frequency or standby frequency programming is made by the RF Standby resistance choice.
16Rref
Rref sets the internal reference current. The internal reference current ranges from 100µA to 500µA. This
requires that 5.0kΩ ≤ Rref ≤ 25kΩ.
CL 96532076_031.eps
290799
Figure 8-12
Page 55
Faultfinding Guide
1mA
Vo
0
OUTPUT
t4
short
Icc
0V
17mA
14.5V
7.5V
t1
Vcc
p.a.v.
t2t3
10V
CL 96532076_035.eps
290799
Block diagram of MC44603
GB 55CDR7758.
16
VrefIref
DEMAGNETISATION
8
9
10
15
12
14
13
DETECT
SYNC INPUT
CT
RF STANDBY
RP STANDBY
VOLTAGE
FEEDBACK
E/A OUT
DEMAGNETISATION
MANAGEMENT
Iref
OSCILLATOR
Vstby
STANDBY
(REDUCED FREQUENCY)
2.5V
ERROR
AMP
FOLDBACK
FOLDBACK
INPUT
5711
VS8 OUT
CURRENT SENSE
INPUT
VOSC PROT
CURRENT
SENSE
VOSC
REFERENCE
BLOCK
=1
Operating description of MC44603
The input voltage Vcc (pin 1) is monitored by a comparator with
hysteresis, enabling the circuit at 14.5V and disabling the
circuit below 7.5V. The error amplifier compares a voltage Vfb
(pin 14) related to the output voltage of the power supply, with
an internal 2.5V reference. The current sense comparator
compares the output of the error amplifier with the switch
current Isense (pin 7) of the power supply. The output of the
current sense comparator resets a latch, which is set every
cycle by the oscillator. The output stage is a totem pole,
capable of driving a MOSFET directly.
Vref
enable
1Set
LATCH
1Reset
THERMAL
SHUTDOWN
Figure 8-13
SUPPLY
INITIALISATION BLOCK
C
Iref
Dmax &
SOFT-START
CONTROL
SOFT-START
& DMAX
UVL01
Vref
UVL01
BUFFER
Vref
OVER
VOLTAGE
MANAGEMENT
CL 96532076_032.eps
1
VC
2
OUT
3
GND
4
Voc
OVER
VOLTAGE
PROTECT
6
290799
Start up sequence of PSU 20PS317
t1: Charging the capacitors at Vcc
C2129 will be charged via R3123 and R3134, C2133 and
C2111 via R3129. The output is switched off during t1.
t2: Charging of output capacitors
When the input voltage of the IC exceeds 14.5V, the circuit is
enabled and starts to produce output pulses. The current
consumption of the circuit increases to about 17mA, depending
on the external loads of the IC. At first, the capacitors at the Vcc
pin will discharge because the primary auxiliary voltage,
coming from winding 7-9 is below the Vcc voltage. At some
moment during t2, the primary auxiliary voltage reaches the
same level as Vcc. This primary auxiliary voltage now
determines the Vcc voltage.
t3: Regulation
The output voltage of the power supply is in regulation.
t4: Overload
When the output is shorted, the supply voltage of the circuit will
decrease and after some time drop below the lower threshold
voltage. At that moment, the output will be disabled and the
process of charging the Vcc capacitors starts again. If the
output is still shorted at the next t2 phase, the complete startand stop sequence will repeat. The power supply goes in a
hiccup mode.
Figure 8-14 ‘Start-up sequence’
Regulation of PSU 20PS317
Figure 8-14 shows the most relevant signals during the
regulation phase of the power supply.
The oscillator voltage ramps up and down between V1 and V2.
The voltage at the current sense terminal is compared every
cycle with the output of the error amplifier Vcomp. The output
Page 56
GB 56CDR7758.
Faultfinding Guide
is switched off when the current sense level exceeds the level
at the output of the error amplifier.
TimeON phase : A drain current will flow from the positive
supply at pin 2 of the transformer through the transformer's
primary winding, the MOSFET and Rsense to ground. As the
positive voltage at pin 2 of the transformer is constant, the
current will increase linearly and create a ramp dependent on
the mains voltage and the inductance of the primary winding. A
certain amount of energy is stored in the transformer in the form
of a magnetic field. The polarity of the voltages at the
secondary windings is opposite to the primary winding so that
the diodes are non-conducting in this phase.
TimeDIODE phase : When the MOSFET is switched off,
energy is no longer supplied to the transformer. The inductance
of the tranformer now tries to maintain the current which has
been flowing through it at a constant level. The polarity of the
voltage from the transformer therefore reverses. This results in
a current flow through the transformer's secondary winding via
the now conducting diodes, electrolytic capacitors and the load.
This current is also ramp shaped but decreasing.
TimeDEAD phase : when the stored energy has been supplied
to the load, the current in the secondary windings stops flowing.
At this point, the drain voltage of the MOSFET will drop to the
voltage of C2121 with a ringing caused by the drain-source
capacitance with the primary inductance.
The oscillator will start a next cycle which consists of the above
described three phases. The time of the different phases
depends on the mains voltage and the load.
TimeDEAD is maximum with an input of 400VDC and a
minimum load. It will be zero with an input of 100VDC and an
overload.
PM3394B
ch1
1
ch3
T
ch2
3
2
ch1 : Drain voltage
ch2 : Drain current
ch3 : Gate voltage
PM3394B
ch1
ch3
1
T
CH1 2
CH2
CH3 2 V~ ALT MTB5.00us- 0.90dv ch1-
CH1 1
CH3 50mV~ ALT MTB5.00us- 0.90dv ch1-
V2
Vosc
V1
0
Vcomp
Vsense
Vgate
Vdrain
Idrain
Idiodes
TonTdiode Tdead
CL 96532076_034.eps
290799
3
ch1 : Drain voltage
ch2 : Oscillator voltage
CH1 1
CH3 20mV~ ALT MTB5.00us- 0.90dv ch1-
ch1
ch3
PM3394B
1
T
3
ch1 : Drain voltage
ch3 : Sense voltage
CL 96532076_033.eps
290799
Figure 8-15 ‘Regulation’
Figure 8-16 ‘Oscillograms’
Page 57
Faultfinding Guide
GB 57CDR7758.
Circuit description of PSU 20PS317
Input circuit
The input circuit consists of a lightning protection circuit and an
EMI filter.
The lightning protection comprises R3120, gasarrestor 1125
and R3124. The EMI filter is formed by C2120, L5120, C2125
and C2126. It prevents inflow of noise into the mains.
Primary rectifier/smoothing
The AC input is rectified by rectifier bridge 6102 and smoothed
into C2121. The voltage over C2121 is approximately 300V. It
can vary from 100V to 390V.
Start up circuit and Vcc supply
This circuit is formed by R3123, R3134, C2129, D6129, R3129,
R3111, C2133 and C2111.
When the power plug is connected to the mains voltage, the
stabilised voltage over D6129 (24V) will charge C2133 via
R3129. When the voltage reaches 14.5V across C2111, the
control circuit of IC7110 is turned on and the regulation starts.
During regulation, Vcc of IC7110 will be supplied by the
rectified voltage from winding 7-9 via L5132, D6132 and
C2133.
Control circuit
The control circuit exists of IC7110, C2102, C2104, C2107,
C2109, C2110, R3102, R3103, R3104, R3107, R3108, R3109
and R3110. C2102 and R3110 define the frequency of the
oscillator.
Demagnetisation
The auxiliary winding (7-9) voltage is used to detect magnetic
saturation of the transformer core and connected via R3101 to
pin 8 of IC7110. During the demagnetisation phase, the output
will be disabled.
Overvoltage protection circuit
This circuit consist of D6114, C2114, R3115 and R3116.
When the regulation circuit is interrupted due to an error in the
control loop, the regulated output voltage will increase
(overvoltage). This overvoltage is sensed at the auxiliary
winding 7-9.
When an overvoltage longer than 2.0 (s is detected, the output
is disabled until VCC is removed and then re-applied. The
power supply will come in a hiccup mode as long as the error
in the control loop is present.
Secondary rectifier/smoothing circuit
There are 5 rectifier/smoothing circuits on the secondary side.
Each voltage depends on the number of windings of the
transformer.
The -8V supply is regulated by voltage regulator 7249.
On/off circuit
In off mode pin 1 and pin 2 of connector 0206 are connected.
The high voltage (-8V, +12V) over opto coupler 7200 forces this
one to conduct. IC7110 is switched off and thus the output
supply voltages.
Power switch circuit
This circuit comprises MOSFET 7125, Rsense 3126, 3127 and
3128, R3125 , C2127, L5125, R3112 and R3113. R3125 is a
pull-down resistor to remove static charges from the gate of the
MOSFET.
Regulation circuit
The regulation circuit comprises opto-coupler 7200 which
isolates the error signal from the control IC on the primary side
and a reference component 7201. The TL431(7201) can be
represented by two components:
a very stable and accurate reference diode
a high gain amplifier
K
R
2.5V
A
CL 96532076_036.eps
Figure 8-17 ‘TL 431’
290799
TL431 will conduct from cathode to anode when the reference
is higher than the internal reference voltage of about 2.5V. If the
reference voltage is lower, the cathode current is almost zero.
The cathode current flows through the LED of the opto-coupler.
The collector current of the opto-coupler flows through R3106,
producing an error voltage, connected to voltage feedback pin
14 of IC7110.
The CD main board is built around the compact disc
mechanism VAM1250 and a loader 1250. The CDM delivers
diode signals and an unequalised high frequency signal. These
signals are necessary inputs for the decoder CD10. Based on
these signals the decoder will control the disc. The decoder is
able to control the sledge, focus motor, radial motor and turn
table. When everything is "locked", the decoder delivers a
digital output according to IEC958 standard, subcode to the
microprocessor and I2S for reproducing analog audio signals
by means of a D/A converter.
The microprocessor controls the CD10 and is slave of the
master processor on the CDR main board in the CDR775. Both
processors communicate via a DSA connection (data, strobe
and acknowledge).
Page 59
Faultfinding Guide
23
19
18
21
20
EFM
DEMODULATOR
MICROCONTROLLER
INTERFACE
CONTROL
PART
V
ref
GENERATOR
V
RIN
ADC
PRE-
PROCESSING
CONTROL
FUNCTION
OUTPUT
STAGES
R1
R2
12
D1 D2 D3 D4
SCL
SDA
FRONT
END
HFIN
HFREF
ISLICE
I
ref
13
7
40
39
2
1
3
6
TEST
TEST1
25
TEST2
31
TEST3
44
TIMING
SELPLL
24
CRIN
16
CROUT
15
CL16
26
CL11/4
49
8910
V
SSA1
V
SSA2
V
DDA1
V
DDA2
V
SSD1VSSD3
V
SSD2
V
DDD1(P)VDDD2(C)
4 14 5 17 33 50 585257
RA
FO
SL
54
55
56
LDON
64
DIGITAL
PLL
SRAM
RAM
ADDRESSER
SUBCODE
PROCESSOR
SBSY
48
SFSY
47
SUB
46
RCK
45
STATUS
43
DECODER
MICRO-
CONTROLLER
INTERFACE
RESET
38
VERSATILE PINS
INTERFACE
KILL
BITSTREAM
DAC
RP
RN
22
LP
LN
V
pos
V
neg
36
SDI
35
WCLI
37
SCLI
SERIAL
DATA
(LOOPBACK)
INTERFACE
30
EF
27
DATA
28
WCLK
29
SCLK
SERIAL
DATA
INTERFACE
PEAK
DETECT
EBU
INTERFACE
AUDIO
PROCESSOR
ERROR
CORRECTOR
FLAGS
MOTOR
CONTROL
51
DOBM
53
CFLG
MOTO1
59
MOTO2
60
V1
V2/V3V4 V5KILL
63 34 61 6232
SILD
42
RAB
41
11
CL96532086_051.eps
080999
CDM VAM1250
Trigenta
HF ampl.
Diode signals
Radial, focus
Motor, sledge
CD10
SERVO
DECODER
Figure 8-19
8.3.1Supply Voltages
Description
The CD main board receives +5V and +12V from the CDR main
board via respectively pin 16 and pin 15 of connector 1208. The
+5V is split up into +5VHF and +5V. The +5VHF is used mainly
for the diode currents and the HF-amplifier. The +5V is used for
the digital part of the board. On the board a +3V3 is made from
the +5V for the decoder CD10 and an A3V3 for the DAC
UDA1320. The +12V is split up into A12V for the audio output
stage and +12V for the power drivers of the CDM.
Measurements
Connect following supplies to next pins :
•+5V + 5% to pin 16 of connector 1208.
•+12V + 5% to pin 15 of connector 1208.
•Ground reference to pin 17 of connector 1208.
Loader assy
PROCESSOR
UDA1320
DAC
DSA
IIS, DOBM
ANA OUT
CL96532086_048.eps
080999
•Connect on pin 2 of position 1208 a clock signal of 8.4672
MHz ( 100ppm minimum rise time of 50ns and at TTL level
(0V and +5V).
•Keep microprocessor 7202 in reset by forcing pin 7 at
position 1208 to +5V.
•Release the reset. Now, the processor will reset the CD10
for at least 75µs.
•The output clock CL11 should be available now at pin 42 of
the CD10.
Check the following frequencies :
PointFrequency
Position 7000 pin 16
Position 7202 pins 14,15
Position 7309 pin 6
Position 7309 pin 1
Position 7309 pin2
8.4672 MHz ± 100ppm
12MHz ± 5%
11.2896 MHz ± 100ppm
2.1168 MHz ± 100ppm
44.1kHz ± 100ppm
Figure 8-21
8.3.3CD10 Decoder/Servo SAA7324 (7000)
Description
The CD10 is a single chip combining the functions of a CD
decoder, digital servo and bitstream DAC. The decoder/servo
part is based on the CD7. The decoding part supports a full
audio specification and can operate at single speed (n=1) and
double speed (n=2).
Block Diagram
GB 59CDR7758.
CL96532086_050.eps
080999
Keep microprocessor 7202 in reset by forcing pin 7 of
connector 1208 to +5V. Check the following voltages :
PointVoltage
Position 1000 pins 1,3
Position 7000 pins 5,17,21,57
Position 7005 pin 14
Position 7020 pins 25
Position 7020 pins 26,27,28
Position 7021 pin 5
Position 7022 pin 5
Position 7025 pin 16
Position 7202 pin 38
Position 7309 pins 4,13
Position 7120 pin 8
The microprocessor has its own Xtal or resonator of 12MHz.
The CD10 needs a clock of 8.4672MHz + 100ppm. This speed
also relates to the disc speed. To avoid locking problems
between the two drives in the CDR775, both drives run on the
same clock. Therefore the CD main board gets the clock for the
decoder from the CDR main board via pin 2 of connector 1208.
The DAC needs a system clock to drive its internal digital filters
and to clock the I2S signals from the decoder. In our case this
is 11.2896MHz (CL11) generated by the CD10.
Measurements
•Connect the power supply as described above in "1.1.1.
Supply Voltages".
080999
Figure 8-22
Page 60
GB 60CDR7758.
Pin Configuration
Faultfinding Guide
HFREF
HFIN
ISLICE
V
SSA1
V
DDA1
V
V
SSA2
CROUT
CRIN
SSD3
DDD2(C)
SL
V
V5
V1
LDON
62
63
64
1
2
3
4
5
I
6
ref
7
RIN
D1
8
D2
9
D3
10
D4
11
R1
12
R2
13
14
15
16
171819202122232425262728293031
LP
LN
VDDA2
MOTO1
V4
MOTO2
60
61
pos
neg
V
V
V
56
57
58
59
SAA7324
RP
RN
SELPLL
TEST1
FO
55
CL16
DDD1(P)
RA
CFLG
V
52
53
54
DATA
SCLK
WCLK
Figure 8-23
8.3.4TDA7073A Power Drivers (7021, 7022)
Description
The TDA7073A is a dual power driver circuit for servo systems
with a single supply. In this configuration it is used to drive the
sledge, tray, focus and radial.
Measurements
Keep microprocessor 7202 in reset by forcing pin 7 of
connector 1208 to +5V. Connect the power supply as
described above in "1.1.1. Supply Voltages". Check the
following voltages :
This component is a 3 phase, full wave pseudo linear driving
system with inbuilt Hall Bias circuit and 3 phase parallel output.
Measurements
Keep processor 7202 in reset by forcing pin 7 of connector
1208 to +5V. The outputs 9, 10, 11 of connector 1006 are 0V.
Pin 21 of the motor driver 7020 is 2.5V ( 10%.
Pin 22 of the motor driver 7020 is 2.5V ( 10%.
Pin 23 of the motor driver 7020 is 0V.
Pin 19 of the motor driver 7020 is 5V ( 10%.
Put the processor out of reset to continue the measurement.
Check MOT1 at pin 59 of CD10. The duty cycle of the output
should be 50%. Check wave form at pin 11 of 7005-D :
amplitude 5V + 5% duty cycle 50%.
The motor driver 7020 can be measured dynamically by
connecting a hall motor to the application panel. Apply a pulse
of 1V 10Hz and 15% duty cycle to pin 22 (Ec) as input value
with reference to pin 21 (Ecr=2.5V). Measure the output signals
on the driver. This will give as response a square wave on pin
17 and pin 18. When a positive voltage is applied, the square
wave on pin 17 will go ahead of the square wave on pin 18.
All signals will have a value as shown in the truth table. Check
the following output signals :
The tray control consists of a TDA7073A power driver (7021)
controlled by the processor 7202 via pin 19 TRAYIN and pin 20
TRAYOUT. If pin 20 is low and pin 19 high, the TRAY+ signal
at pin 16 of 7021 is forced to +8V and the TRAY- signal at pin
13 of 7021 to GND : the tray will open. If pin 20 is high and pin
19 low, TRAY+ becomes GND and TRAY- becomes +8V : the
tray will close. If pin 19 and 20 of the processor have the same
value, TRAY+ and TRAY- will have the same value as well : the
tray stops moving.
Measurements
Keep procesor 7202 in reset by forcing pin 7 of connector 1208
to +5V. Connect a load of 15Ω, 7W between pin 3 and 4 of
connector 1002. Check the voltage over the load with TRAY+
(pin 3) as positive reference. Check also the levels of pins 19
and 20 of the processor.
U TRAY+,TRAY- = <100mV
Pin 20 = +5V
Pin 19 = +5V
Force pin 20 of the processor to ground, and check the
voltages.
U TRAY+,TRAY- = -6.5V( 10%
Pin 20 = +0V
Pin 19 = +5V
Force pin 19 of the processor to ground as well and check the
levels again.
U TRAY+,TRAY- = <100mV
Pin 20 = +0V
Pin 19 = +0V
Release pin 20 of the processor and check the levels.
U TRAY+,TRAY- = 6.5V( 10%
Pin 20 = +5V
Pin 19 = +0V
Release pin 19 of the processor and check the levels again:
U TRAY+,TRAY- = <100mV
Pin 20 = +5V
Pin 19 = +5V
Figure 8-27
Page 62
GB 62CDR7758.
Faultfinding Guide
8.3.7HF Path
Description
The pre-amplified HF-signal is presented to both n=1 and n=2
amplifier circuits. The mux/demux switches via software and
micro processor controlled S1 and S2 lines between either one
of the amplified n=1 or n=2 signals. The signal will then follow
n-dependant filtering
+5VHF
PRE AMP
HF
3173
430R
F157
3191
430R
n=1 AMP
3174
430R
2143
330p
2
n=2 AMP
3192
430R
2164
180p
2140
HFGND
2162
HFGND
180p
100p
+5VHF
3188
3203
2K7
7009
BFS20
2K7
HFGND
3169
7023
BFS20
3180
HFGND
2K7
2K7
HFGND
DUAL 4 CHANNEL
MUX/DEMUX
+5VHF
HFGND
2141
2n2
2146
1n5
16
7
8
1
5
2
4
12
14
15
11
74HCT4052D
VCC
VEE
GND
0
1
2
3
+5VHF
HFGND
390p
2149
680p
2130
100n
HF
47u
22n
2160
HFGND
HFGND
HF
7010
BC848B
HFGND
1K
3196
BC858B
4x
2161
7007
HFGND
another amplification and filtering circuit. The filtering again is
controlled by the S1 and S2 lines, dependant on whether the
disc starts up (speed n=1, S1 and S2 Low), disc plays at speed
n=1 (S1 Low, S2 High) or disc plays at speed n=2 (S1 and S2
High).
7025
0
3
3189
10
0
9
1
6
G4
HFGND
3
22n
HFGND
HF
13
F313
390R
F156
9
22n
2137
HFGND
HFIN
3178
2138
1K
S1
S2
HFGND
HFGND
2142
22n
F310
2150
47n
3
7000
SAA7324
F309
1
HFREF
2145
2
3181
22K
F159
3
4
5
HFIN
ISLICE
VSSA1
VDDA1
47p
HF
3193
180R
10K
3205
CL96532086_057.eps
FRONT
END
080999
DC Settings
Set the power and reset connections as described above in
"1.1.1. Supply Voltages". Check the following voltages :
ForcePinLocationMeasure
Emitter70062.4 ± 10%
S1 and S2 “HIGH”Collector70101.9 ± 10%
S1 and S2 “LOW”Collector70101.9 ± 10%
S1 and S2 “HIGH”1370251.6 ± 10%
S1 and S2 “LOW”1370251.6 ± 10%
S1 and S2 “HIGH”370253.2 ± 10%
S1 and S2 “LOW”370253.2 ± 10%
CL96532086_058.eps
Figure 8-29
Figure 8-28
080999
Page 63
Faultfinding Guide
MSBMSB
LEFT SAMPLERIGHT SAMPLE
WS
CLK
DATA
CL96532086_061.eps
080999
GB 63CDR7758.
Transfer Characteristics
Set the power and reset connections as described above in
"1.1.1. Supply Voltages". Connect a function generator via a
serial resistor of 1k5 to pin 4 of connector 1000. Use the
Set the power and reset connections as described above in
"1.1.1. Supply Voltages". Connect a function generator via a
serial resistor of 1k5 to pin 4 of connector 1000. Use the
function generator as a sine wave generator with output level
of 1Vtt. Check this AC value with an AC mV-meter connected
to the input (pin 2) of the CD10 (7000) :
AC
Pin 2 at 7000
CL96532086_059.eps
080999
function generator as a sine wave generator with output level
of 500 kHz, 1Vtt. Check this AC value with an AC mV-meter :
CL96532086_060.eps
080999
8.3.8Audio Part - DAC
Description
The DAC used, is the UDA1320 bit stream, continuous
calibration. I2S signals from various formats can be entered at
pins 1,2 and 3. If these signals are in phase with the delivered
system clock at pin 6, the DAC will reproduce analog output
signals at pins 14 and 16. 0dB level is 0.85Vrms. These analog
signals are at 1.65Vdc level.
The DAC has features which can be checked on the input pins.
Mute will switch off the analog signals. De-emphasis is not
used, since this is done in the decoder. Attenuation of -12dB is
not used because this is also done in the decoder.
I2S
I2S is a kind of digital audio format, consisting out of 3 lines :
CLOCK, WORDSELECT and DATA.
WORD-SELECT
Word select (WS) indicates whether the data-sample is from
the left or the right audio-channel. It has the same frequency as
the sample rate of the digital audio signal. This can be 32, 44.1
or 48kHz. Normal polarity is low for a left sample and high for a
right sample. So within the low state of the WS-line the data bits
for the left channel are transferred, and within the high state the
data bits of the right channel are transferred.
Figure 8-31
signal is in phase with the WS-signal. Transition of the WS
always happens on a falling edge of the CLK.
DATA
DATA contains all data-bits. Data bits are set by the
transmitting device, and read by the receiving device. The
position of the DATA-bits within the WS-signal is very
important. There are several formats for this. In our case we
always use Philips I2S format, no Japanese or Sony format.
The number of data-bits per channel depends on the used
devices.
Timing of the I2S-bus, in case of Philips I2S is shown in the
next figure :
Figure 8-32
CLOCK
The CLOCK signal (CLK) indicates when DataTips must be
set, and when DataTips must be read. The frequency depends
on the speed of the I2S-bus, but is always a factor of the
frequency of the WS-signal. It can be 48x, 64x, 96, 128x... .In
our case it is 48x the sample rate frequency = 2.1168MHz. The
Page 64
GB 64CDR7758.
Measurements
Faultfinding Guide
IIS
22
DACAMPLIFIER
CLK11
25
NMUTE
Keep processor 7202 in reset by forcing pin 7 of connector
1208 to +5V. This puts the processor outputs in tristate. Check
the reset at pin 4 of processor 7202 to make sure that the
processor is in reset.
Now, force port 0-4 pin 33 at 7202 to 0V to set the decoder
outputs (SCLK, WCLK, DATA, and CL11).
Check the MUTE pin 11 at 7309 : this pin should be low.
Connect via an I2S generator I2S-signals to the DAC :
Pin 1 at 7309: SLCK.
Pin 2 at 7309: WCLK.
Pin 3 at 7309: DATA.
Connect also the SYSCLK pin 6 at position 7309 to a clock
signal of 11.2896 MHz ( 100ppm.
Generate an I2S signal equivalent with a sine wave of 1kHz at
0dB for both left and right channels.
Check if 0.8 VRMS at pins 14 and 16 at location 7209 with a
DC of 1.65VDC.
Check if 1.7 VRMS ( 2 dB at connector pins 1and 3 at location
1209.
Force MUTE Pin 11 at 7309 high.
Measure again at pins 1 and 3 at location 1209 : both signals
should be at -90 dB.
Figure 8-33
1200 - 17
1200 - 19
CL96532086_062.eps
080999
Page 65
List of Abbreviations
9.List of Abbreviations
SIGNAL NAMESIGNAL FLOWFUNCTION AND DESCRIPTION
+12Vmain supply voltage from PSU+12V supply voltage from PSU
+12VAsupply voltage+12V supply voltage for Audio part
+5Vmain supply voltage from PSU+5V supply voltage from PSU
+5VAsupply voltage+5V supply voltage for Audio part
+9SRVPWRIC7558 ->- IC7240PoWeR supply for SeRVo driver IC
12VPWRsupply voltage+12V supply voltage for servo part
-8Vmain supply voltage from PSU-8V supply voltage from PSU
-8VAsupply voltage-8V supply voltage for Audio part
A(1:20)IC7701 -> R3818,R3819, R3820, R3821,
R3897 -> IC7703
A(10:20)IC7701 -> R3819, R3820, R3821 ->
IC7702
A1IC7010 -> IC7270amplitude of the “land” reflection relative to the average EFM, voltage
A1LF, A2LFCONN1000 -> IC7010satellite photo diodes A1, A2 current output
A2IC7010 -> IC7270amplitude of the “pit” reflection relative to the average EFM, voltage
A-8Vsupply voltage-8V supply voltage for servo part
AEGERAnalog Error signal GEnerator for Recordable
AINTONIC7008 -> IC7010Alpha INTegrator ON (to AEGER)
ALEIC7270 -> R3213 -> IC7209,
IC7300IC7270 -> R3230
ALPHA0IC7270 -> IC7010analog voltage mode output from OPC D/A converter
ALSIC7008 -> IC7010Alpha Loop Switch (to AEGER)
ASTROBEIC7008 -> IC7010Alpha STROBE (to AEGER)
ATIPAbsolute Time In Pre-groove (sync signal)
ATIPSYNCIC7300 -> IC7270ATIP SYNC signal
ATTIC7270 -> R3717, R3722IC7270 ->
IC7701
B1LF, B2LFCONN1000 -> IC7010satellite photo diodes B1, B2 current output
BCLKIC7701 -> R3898A -> IC7300I2S1 BitCLocK from DASP to CDR60 (playback and record)
BE_RESETIC7701 -> R3261 -> IC7270IC7701 ->
R3716
BIASCIC7008 -> R3056BIAS Current switch CDRW output
BKPTCONN1819, R3907 -> IC7701JTAG mode select / debug mode BreaKPoinT
C1LF, .. , C4LFCONN1000 -> IC7010Central photo diodes C1, C2, C3, C4 current output
CAGAINR3016,R3115 -> IC7010set-point laser power on disc, current input
CAHFCONN1000 -> C2374Central Aperture (central photo diodes) High Frequency current
CAS0IC7701 -> IC7702Column Address Strobe DRAM for upper byte
CAS1IC7701 -> IC7702Column Address Strobe DRAM for lower byte
CDRIC7008 -> IC7355CDR strategy detected output (active high)
CDR60CFLGIC7300 -> R3382B -> CONN1812serial output of error corrector status information of the CDR60-
CDR60CL1IC7300 -> R3382C -> CONN1812output of CLock signal for testing system clock of IC CDR60 at test
CDR60CSIC7270 -> R3235B -> R3702, IC7300CDR60 Chip Select, active high
CDR60INTIC7300 -> IC7270CDR60 INTerrupt line, active low
CDR60LWRTIC7300 -> R3048CDR60 Laser WRiTe control output
ATTenuation request from MACE2 to audio DAC, active low; means
that the output can be attenuated in case of search activities
Basic Engine RESET, active high
output (C1+C2+C3+C4)
coupled EFM signal), voltage output, OPC input
decoder, to be measured at test connector
connector
Page 66
GB 66CDR7759.
List of Abbreviations
CDR60MEAS1IC7300 -> R3382A -> CONN1812serial output of information about jitter, PLL frequency and
CDR60PLLIC7270 -> R3305 -> IC7300CDR60 clock multiplier enable, active high
CDRWIC7355D -> IC7355CIC7355D ->
CONN1000
CLK_OUTIC7701 -> R3771 -> CONN1819system CLocK OUT
CLK_SYSIC7701 -> R3727, R3731oscillator output
COS-CONN1220 -> IC7225BHall feedback signal from sledge motor
COS+CONN1220 -> IC7225BHall feedback signal from sledge motor
CSFLASHIC7701 -> IC7703Chip Select for FLASH or boot device
CSRAMIC7270 -> R3235A -> R3703, IC7802Chip Select SRAM, active low
D(16:31)IC7701 <-> R3822, R3823, R3824,
R3825 <-> IC7703, IC7702
D3V3supply voltage+3,3V supply voltage for Digital part
D5Vsupply voltage+5V supply voltage for Digital part
D5VSsupply voltage+5V supply voltage for Servo part
DALPHAIC7010 -> R3037ALPHA error signal for laser power control
DASPDigital Audio Signal Processor
DATAIIC7701 -> R3898C -> IC7300I2S1 DATA In from DASP to CDR60 (recording)
DATAOIC7300 -> R3314 -> IC7701I2S1 DATA Out from CDR60 to DASP (playback)
DEEMPIC7270 -> R3719, R3724IC7270 ->
IC7701
DELTAPIC7016 -> R3126DELTA Power current source drive signal from XDAC
DIG_OUT_CIC7701 -> R3706 -> C2707, CONN1400Common DIGital OUTput (consumer)
DISPLAY_INTF934 -> R3812, IC7701DISPLAY INTerrupt
DMONIC7270 -> R3324power save at stop, active low
DOBM_CDCONN1708, C2731 -> R3757 -> R3903 -
> IC7701
DOBM_CDRIC7300 -> R3382D -> C2379, IC7701Digital Output (EBU output) from CDR60 to DASP
DRAM_RWIC7701 -> IC7702Read/Write strobe for DRAM
DSA_ACK_CDIC7701 <-> R3830 <-> R3831 <->
DSCLKCONN1819, R3908 -> IC7701reset in / Debug Serial CLocK in
DSICONN1819, R3909 -> IC7701JTAG reset in / Debug Serial clock In
EFMEight to Fourteen Modulation = modulation method used for CD
EFMCLKIC7300 -> IC7008EFM CLocK output
EFMDATAIC7300 -> IC7008EFM DATA output
EFMTIM3EFM TIMing generator
EPONIC7008 -> R3010IC7008 -> C2010Erase Power ON
EPONOIC7008 -> R3107Erase Power ON Open drain output
EPONRCR3004 -> CONN1000Erase Power ON (after RC circuit)
asymmetry of bit recovery block in CDR60, to be measured at test
connector
inverted CDR-strategy-detected signal
Databus bit 16 to 31 between DASP, flash ROM and DRAM
DE-EMphasis control for audio DAC from MACE2, active high;
means that de-emphasis is needed in digital filter
Digital Output (EBU output) from CD player in CDR775 to DASP
Data/Strobe/Acknowledge serial communication between DASP and
CD-player in CDR775
Data/Strobe/Acknowledge serial communication between MACE2
and DASP for CDR; acknowledge input for MACE2 is strobe output
for DASP
Data/Strobe/Acknowledge serial communication between DASP and
CD-player in CDR775
Data/Strobe/Acknowledge serial communication between MACE2
and DASP for CDR
Data/Strobe/Acknowledge serial communication between DASP and
CD-player in CDR775
Data/Strobe/Acknowledge serial communication between MACE2
and DASP for CDR (strobe output for MACE2 is acknowledge input
for DASP)
storage, also the actual raw CD signal as written or read on or from
the CD disc
Page 67
List of Abbreviations
ERASECIC7008 -> R3087ERASE Current switch CDRW output
ERONIC7008 -> IC 7010ERror ON (to AEGER)
EXT_DIG_IN1CONN1400 -> IC7701EXTernal DIGital INput 1
EXT_DIG_IN2CONN1702, C2767, C2721 -> R3701 -
F_RWIC7701 -> IC7708BRead/Write strobe for Flash ROM
FENIC7010 -> IC7270Focus Error Normalized current output
FOC-IC7240 -> CONN1000FOCus actuator drive signal negative connection
FOC+IC7240 -> CONN1000FOCus actuator drive signal positive connection
FS30VD6500 -> CONN1000Forward Sense diode 30V power supply
FSACONN1000 -> T7119, T7120Forward Sense photo diode current output
FSCLRIC7008 -> IC7126Forward Sense signals CLeaR switch
FSOFIC7008 -> R3052Forward Sense photo diode sampling OFf
FSONIC7008 -> R3051Forward Sense photo diode sampling ON
FSRR3040 -> IC7270Forward Sense signal while Reading for read control loop
FSRSIC7008 -> IC7126DForward Sense photo diode Read Sampling
FSWR3050 -> IC7270Forward Sense signal while Writing for write control loop
FSWSIC7008 -> IC7126CForward Sense photo diode Write Sampling
FWENIC7270 -> IC7208, R3806Flash EPROM Write ENable
HALL_U,
I2CLR3248B -> IC7207, R3247CI2C CLock line
I2CSCLIC7207 -> IC7008IC7207 ->
I2CSDAIC7207 <-> IC7008IC7207 <->
I2DAR3248A <-> IC7270,R3247DI2C DAta line
I2S_BCLK_AIIC7701 -> R3814 -> IC7406I2S4 Bit CLocK for CODEC (ADC for CDR950) Analog Input (record
I2S_BCLK_AOIC7701 -> R3894A -> IC7406I2S2 Bit CLocK for CODEC (DAC for CDR950) Analog Output
I2S_BCLK_CDCONN1708, C2739 -> R3834 -> IC7701I2S3 Bit CLocK from CD player (record n=2) (CDR775 only)
I2S_BCLK_MICCONN1708, C2739 -> R3834 -> IC7701I2S3 Bit CLocK from MICrophone (CDR950 only)
I2S_DATA_AIIC7406 -> IC7701I2S4 DATA from CODEC (ADC for CDR950) Analog Input (record
I2S_DATA_AOIC7701 -> R3894C -> IC7406I2S2 DATA for CODEC (DAC for CDR950) Analog Output
I2S_DATA_CDCONN1708, C2738 -> R3836 -> IC7701I2S3 DATA from CD player (record n=2) (CDR775 only)
I2S_DATA_MICCONN1708, C2738 -> R3836 -> IC7701I2S3 DATA from MICrophone (CDR950 only)
I2S_WS_AIIC7701 -> R3743 -> IC7406I2S4 Word CLocK for CODEC (ADC for CDR950) Analog Input
I2S_WS_AOIC7701 -> R3894B -> IC7406I2S2 Word CLocK for CODEC (DAC for CDR950) Analog Output
I2S_WS_CDCONN1708, C2740 -> R3833 -> IC7701I2S3 Word CLocK from CD player (record n=2) (CDR775 only)
I2S_WS_MICCONN1708, C2740 -> R3833 -> IC7701I2S3 Word CLocK from MICrophone (CDR950 only)
I2S1_MSIC7270 -> R3910, IC7701I2S1 Master-Slave interrupt from MACE2
IET7121 -> CONN1000laser Erase drive current signal
>IC7701
> IC7701
IC7330 -> IC7300, CONN1812HALL feedback signals from turn table motor via hall motor driver
F934IC7701, R3711 -> IC7801
R3714 <-> F934IC7701, R3712 <->
IC7801
IC7010IC7207 -> R3248B
IC7010IC7207 <-> R3248A
EXTernal DIGital INput 2 (CDR950 only)
Flash READY detection, this line is forced low as long as the flash is
busy with erase or program algorithm
I2C CLocK line used for display slave processor and digital potmeter
I2C DATA line used for display slave processor and digital potmeter
I2C Serial CLock line
I2C Serial DAta line
from analog source)
from analog source)
(record from analog source)
GB 67CDR7759.
Page 68
GB 68CDR7759.
List of Abbreviations
INT_COPY_ANAIC7701 -> R3721 -> IC7401IC7701 ->
R3721 -> R3410
IRT7135 -> CONN1000T7135 ->
R3056T7135 -> IC7008
IWT7122 -> CONN1000T7122 -> D6003laser Write drive current signal
KEY_PRESSEDIC7706B -> R3816 -> IC7701KEY PRESSED interrupt
KILLT7560, T7561, R3560 -> CONN1400,
R3424, R3428
KILL_OUTIC7701 -> R3532disables the KILL activity from the PSU; 1 = no kill,0 = kill active
L12Vsupply voltage+12V supply voltage for servo/Laser part
L3_CLKIC7701 -> R3725 -> IC7406L3 interface CLocK line / control CODEC (not for CDR950)
L3_DATAIC7701 <-> R3728 <-> IC7406L3 interface DATA line with CODEC (not for CDR950)
L3_MODEIC7701 -> R3735 -> IC7406L3 interface MODE line selects data or address transfer mode for
L5Vsupply voltage+5V supply voltage for servo/Laser part
L-5Vsupply voltage-5V supply voltage for servo/Laser part
LASCKIC7270 <-> R3248DClocK line DAC LASer control
LASDACCKR3248D <-> IC7016ClocK line DAC LASer control
LASDACDIR3248C <-> IC7016Data line DAC LASer control
LASDACLDR3212 <-> IC7016LoaD line DAC LASer control
LASDDIC7270 <-> R3248CData line DAC LASer control
LASLDIC7270 <-> R3238 <-> R3212IC7270 <->
R3232
LEFTCONN1708, C2743 -> IC7401C,
IC7407C
LLPIC7270 -> IC7300Laser Low Power (active high), switches the laser from write to read
LWRTR3048 -> IC7008Laser WRiTe control input
MA(16:17)IC7270 <-> IC7208bank switch higher address lines
MA(8:15)IC7270 <-> IC7802 <-> IC7208address bus high byte
MACE2Mini All Cd Engine (minus decoder + OPC + PCS + extra RAM)
MAD(0:7)IC7270 <-> IC7209 <-> IC7802 <->
IC7208 <-> IC7300
MIRNIC7010 -> IC7270MIRror Normalized (disc reflection) current output
MOTO1IC7300 -> IC7355Aturn table MOTOr control output
MRDNIC7270 -> R3276 -> R3242A, IC7802,
IC7300
MUTEIC7270 -> R3718, R3723IC7270 ->
IC7701
MWRNIC7270 -> R3280 -> R3242B, IC7802,
IC7300
NMUTEIC7701 -> R3726, IC7406MUTE output, low active
OFFTRACKIC7270 -> IC7300OFFTRACK detection flag
OPCOptimum Power Calibration
P12VKILLsupply voltage+12V supply voltage for KILL-circuit
PCSPosition Control Sledge
PCSCOSIC7225B, C2229 -> IC7270, CONN1812Position Control Sledge COS feedback signal
PCSSINIC7225A, C2227 -> IC7270, CONN1812Position Control Sledge SIN feedback signal
PDARPhoto Diode Amplifier Recordable
PERASER3036, R3031, R3030, R3029, R3028,
R3027, R3020 -> IC7002C, R3043,
T7113
POWER_UPIC7270 -> R3243C,R3556, R3538standby pin, high level activates essential powers necessary for full
PPNIC7010 -> IC7050CPush-Pull signal, Normalized, balanced, voltage output
select INTernal COPY ANAlog (in case of copy protected disc or track
on CD drive) (CDR775 only)
laser Read drive current signal
KILL signal from power supply part to audio outputs
CODEC (not for CDR950)
LoaD line DAC LASer control
audio output LEFT channel from CD-player in CDR775
power whenever the device tends to go offtrack
bi-directional data bus / address bus low byte
Master ReaD, read strobe for external peripherals, active low
MUTE control from MACE2 to DASP, active low
Master WRite, write strobe for external peripherals, active low
laser Power switch for ERASE
function; overrules HI_POWER setting
Page 69
List of Abbreviations
PRCOARSEIC7016 -> R3057drive signal from Power Read COARSE DAC for read current source
PRFINEIC7016 -> R3058drive signal from Power Read FINE DAC for read current source
PROF_EBUIC7701 -> CONN1820PROFessional digital output (CDR950 only)
PSENnIC7270 -> R3260 -> IC7208IC7270 ->
PWR3081 -> IC7008Write Power signal to OPC input of MACE2
PWBIC7001C -> IC7016drive signal to XDAC<->s for write and erase current sources and
PWDIC7016 -> IC7002BIC7016 -> IC7002Cdrive signal from XDAC for write and erase current sources
PWMAXIC7016 -> R3073PW MAXimum signal from DAC used for determining set point for
PWMINIC7016 -> R3072PW MINimum signal from DAC used for determining set point for
PWRITER3035, R3026, R3025, R3024, R3023,
RAD-IC7240 -> CONN1000Radial actuator drive signal negative connection
RAD+IC7240 -> CONN1000Radial actuator drive signal positive connection
RAS0IC7701 -> IC7702Row Address Strobe DRAM
RCKIC7300 -> R3319 -> IC7701EIAJ subcode clock from CDR60 to DASP (CD text interface)
RDGAIN1IC7008 -> R3054forward sense ReaD GAIN switch 1
RDGAIN2IC7008 -> C2027forward sense ReaD GAIN switch 2
RDGAIN3IC7008 -> C2060forward sense ReaD GAIN switch 3
REIC7010 -> IC7215ARadial Error signal for fast track counting, voltage output
RECORDINGIC7008 -> IC7010IC7008 ->
RENIC7010 -> IC7270Radial Error Normalized current output
RIGHTCONN1708, C2742 -> IC7401A, IC7407Aaudio output RIGHT channel from CD-player in CDR775
RXD_TOOLCONN1818 -> IC7701Receive of UART for test TOOL
S1V65Referenve Voltage1.65V delivered by IC7215B for Servo part
S2V9Reference Voltage2.9V delivered by IC7010 for Servo part
SEL_HP_OUTIC7701 -> R3720 -> IC7407SELect HeadPhone OUTput in DJ-mode (for CDR775 only)
SFSYIC7701 -> R3756 -> IC7300EIAJ subcode synchronisation from DASP to CDR60 (CD text
SIN-CONN1220 -> IC7225AHall feedback signal from sledge motor
SIN+CONN1220 -> IC7225AHall feedback signal from sledge motor
SL-IC7240 -> R3265 -> CONN1220SLedge motor drive signal negative connection
SL+IC7240 -> CONN1220SLedge motor drive signal positive connection
SRSTNIC7270 -> R3243B, IC7300Slave ReSeT out (CDR60 reset), active low
STANDBYIC7270 -> R3807 -> R3887 -> IC7701STANDBY pin, high level activates essential powers necessary for
SUBIC7701 -> R3710 -> IC7300EIAJ subcode data from DASP to CDR60 (CD text interface)
SYS_CLK_11WIC7701 -> R3732 -> IC740611.2896 MHz SYStem CLocK for AD/DA datapath
SYS_CLK_16WIC7701 -> R3894D-> IC7706A16.9344 MHz SYStem CLocK for producing SYS_CLK_BE
SYS_CLK_8WIC7706A -> R3815 -> CONN1708SYstem CLocK CD player (8.4672 MHz) (CDR775 only)
SYS_CLK_BEIC7706A -> R3826 -> IC7270SYstem CLocK Basic Engine (8.4672 MHz)
SYS_RESETIC7701 -> R3758 -> CONNF934IC7701 -
TCKCONN1819 -> R3906, IC7701JTAG ClocK signal
TDSOIC7701 -> CONN1819JTAG Serial Data Out / debug data out
TERMBIC7270 <-> CONN1818UART connection with MACE
TLNIC7010 -> IC7270Track Loss Normalized current output
TR-IC7240 -> CONN1200TRay motor drive signal negative connection
TR+IC7240 -> CONN1200TRay motor drive signal positive connection
GB 69CDR7759.
Program Store ENable; external ROM output enable line, active low
R3231
VCAGAIN
laser power during writing
laser power during writing
laser Power switch for WRITE
R3022, R3021 -> IC7002B, R3044,
T7124
SYStem RESET to display assy (and CD player for CDR775)
> R3770 -> T7707 -> CONN1708
Page 70
GB 70CDR7759.
TRACE99_RXDCONN1818 -> R3838, IC7701TRACE99 test tool receive data
TRACE99_TXDIC7701 -> CONN1818TRACE99 test tool transmit data
TRAYINIC7270 -> IC7240move TRAY IN line, active low
TRAYOUTIC7270 -> IC7240move TRAY OUT line, active low
List of Abbreviations
TRAYSWCONN1200 -> R3747CONN1200 ->
R3748
TRAYSWFR3748, C2214 -> IC7270Filtered TRAY SWitch signal, low is completely out or in
TXD_TOOLIC7701 -> CONN1818Transmit of UART for test TOOL
U+, U-, V+, V-,
W+, WUCOIL, VCOIL,
WCOIL
VCAGAINIC7016 -> IC7005Aset-point laser power on disc, voltage output
VDC1CONN1500 -> CONNF934supply voltage for display assy
VDC2CONN1500 -> CONNF934supply voltage for display assy
VFOIC7270 -> R3295 -> R3244FOcus actuator drive output
VFTDCONN1500 -> CONNF934Voltage Fluorescent Tube Display (display assy)
VRAIC7270 -> R3297 -> R3254RAdial actuator drive output
VSLIC7270 -> R3299 -> IC7240SLedge actuator drive output
WCLKIC7701 -> R3898B -> IC7300I2S1 WordCLocK from DASP to CDR60 (playback and record)
WOBBLEIC7050C -> IC7300analog WOBBLE signal of pre-groove detected by PPN-signal
WPONIC7008 -> R3009IC7008 -> C2009Write Power ON
WPONOIC7008 -> R3106Write Power ON Open drain output
WPONRCR3003 -> CONN1000Write Power ON (after RC circuit)
XDACmultiplying DAC
CONN1330 -> IC7330hall feedback signals from turn table motor to hall motor driver
IC7330 -> CONN1330drive signals for turn table motor
TRAY SWitch signal from loader assy
Page 71
Spare parts list
10. Spare parts list
GB 71CDR77510.
Mechanical Parts List 775
Cabinet Parts
3104 129 52531 COMPLETE CDR775
0001 3104 127 08720 FRONT ASSY COMPLETE
0003 3104 127 08710 KEY UNIT MIDDLE ASSY
00094822 410 11962 POWER BUTTON BLACK
00144822 459 10887 WORDMARK PLATE
00154822 454 13339 CDRW LOGO PLATE,
0051 3104 124 05700 EASY JOG KNOB CDR775
00524822 492 51374 SPRING (RING)
0053 3104 124 05620 TRANSPARENT FRAME