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CBTV4010 |
INTEGRATED CIRCUITS |
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CBTV4010
10-bit DDR SDRAM mux/bus switch
Product data |
2002 Feb 19 |
File under Integrated Circuits Ð ICL03
P s
on o s
Philips Semiconductors |
Product data |
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10-bit DDR SDRAM mux/bus switch |
CBTV4010 |
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FEATURES
•Enable signal is SSTL_2 compatible
•Optimized for use in Double Data Rate (DDR) SDRAM applications
•Designed to be used with 400 Mbps/200 MHz DDR data bus
•Switch on resistance is designed to eliminate the need for series resistor to DDR SDRAM
•20 W on resistance
•Internal 100 W pull-down resistors
•Low differential skew
•Matched rise/fall slew rate
•Low cross-talk data-data/data-DQM
•Independent DIMM control lines
•Latch-up protection exceeds 500 mA per JESD78
•ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
DESCRIPTION
This 10-bit bus switch is designed for 2.3 V to 2.7 V VCC operation and SSTL_2 select input levels.
Each Host port pin is multiplexed to one of four DIMM port pins. When the S pin is low the corresponding 10-bit bus switch is turned on. The on-state connects the Host port to the DIMM port through a 20 W nominal series resistance. When the S pin is high the switch is open and a high-impedance state exists between the two ports. The
DIMM port is terminated with a 100 W resistor to ground when the S pin is high. The design is intended to have only one DIMM port active at any time.
The part incorporates a very low cross-talk design. It has a very low skew between outputs (< 50 ps) and low skew (< 50 ps) for rising and falling edges. The part has optional performance in DDR data bus applications.
Each switch has been optimized for connection to 1 or 2-bank
DIMMs.
The low internal RC time constant of the switch (20 W × 7 pF) allows data transfer to be made with minimal propagation delay.
The CBTV4010 is characterized for operation from 0 to +85 °C.
QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
TYPICAL |
UNIT |
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Tamb = 25 |
°C; GND = 0 V |
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tPLH |
Propagation delay |
CL = 7 pF; VCC = 2.5 V |
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140 |
ps |
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tPHL |
An to Yn |
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CIN |
Input capacitance ± control pins |
VI = 0 V or VCC |
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1.8 |
pF |
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CON |
Channel on capacitance |
Vin = 1.5 V |
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7 |
pF |
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ICCZ |
Total supply current |
VCC = 2.5 V |
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500 |
mA |
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ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
ORDER CODE |
DWG NUMBER |
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TFBGA64 (Thin Fine Pitch BGA) |
0 to +85 °C |
CBTV4010EE |
SOT746-1 |
2002 Feb 19 |
2 |
853-2315 27756 |
Philips Semiconductors |
Product data |
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10-bit DDR SDRAM mux/bus switch |
CBTV4010 |
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64-BALL BGA CONFIGURATION
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1 |
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2 |
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3 |
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4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
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A |
VDD |
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S1 |
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NC |
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1DP0 |
2DP0 |
3DP0 |
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2DP1 |
3DP1 |
0DP2 |
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VDD |
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GND |
0DP0 |
HP0 |
0DP1 |
1DP1 |
HP1 |
GND |
1DP2 |
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B |
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S2 |
S0 |
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C |
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NC |
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HP2 |
2DP2 |
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S3 |
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D |
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GND |
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3DP2 |
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E |
2DP9 |
3DP9 |
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0DP3 |
1DP3 |
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F |
1DP9 |
HP9 |
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HP3 |
2DP3 |
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G |
0DP9 |
3DP8 |
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GND |
3DP3 |
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H |
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2DP8 |
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0DP4 |
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J |
1DP8 |
HP8 |
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HP4 |
1DP4 |
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K |
0DP8 |
GND |
HP7 |
0DP7 |
3DP6 |
HP6 |
GND |
3DP5 |
HP5 |
3DP4 |
2DP4 |
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L |
3DP7 |
2DP7 |
1DP7 |
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2DP6 |
1DP6 |
0DP6 |
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2DP5 |
1DP5 |
0DP5 |
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NOTE: BLANK SPACE INDICATES NO BALL |
SA00589 |
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PIN DESCRIPTION
PIN NUMBER |
SYMBOL |
NAME AND FUNCTION |
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B6, B9, C10, F2, |
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F10, J2, J10, K3, |
HP0±HP9 |
Host ports |
K6, K9 |
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A2, B1, B3, C2 |
S0±S3 |
Select |
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A5, A6, A7, A9, |
0DP0±3DP3 |
DIMM ports |
A10, A11, B5, B7, |
0DP1±3DP1 |
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B8, B11, C11, D10, |
0DP2±3DP2 |
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E1, E2, E10, E11, |
0DP3±3DP3 |
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F1, F11, G1, G2, |
0DP4±3DP4 |
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G11, H2, H10, J1, |
0DP5±3DP5 |
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J11, K1, K4, K5, |
0DP6±3DP6 |
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K8, K10, K11, L1, |
0DP7±3DP7 |
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L2, L3, L5, L6, L7, |
0DP8±3DP8 |
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L9, L10, L11 |
0DP9±3DP9 |
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B10, D2, G10, K2, |
GND |
Ground |
K7, |
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A1, B2 |
VDD |
Positive supply voltage |
FUNCTION TABLE
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INPUT |
FUNCTION |
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S |
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L |
Host port = DIMM port |
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H |
Host port = Disconnect |
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DIMM port = 100 Ω to GND |
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H |
= |
High voltage level |
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L |
= |
Low voltage level |
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2002 Feb 19 |
3 |
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