Philips CBTV4010 Technical data

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INTEGRATED CIRCUITS

CBTV4010

10-bit DDR SDRAM mux/bus switch

Product data File under Integrated Circuits — ICL03

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2002 Feb 19

Philips Semiconductors Product data

CBTV401010-bit DDR SDRAM mux/bus switch

FEA TURES

• Enable signal is SSTL_2 compatible

• Optimized for use in Double Data Rate (DDR) SDRAM

applications

• Designed to be used with 400 Mbps/200 MHz DDR data bus

• Switch on resistance is designed to eliminate the need for series

resistor to DDR SDRAM

• 20 Ω on resistance

• Internal 100 Ω pull-down resistors

• Low differential skew

• Matched rise/fall slew rate

• Low cross-talk data-data/data-DQM

• Independent DIMM control lines

• Latch-up protection exceeds 500 mA per JESD78

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

QUICK REFERENCE DATA

SYMBOL PARAMETER

PLH

PHL

C C I

CCZ

Propagation delay An to Yn

Input capacitance – control pins VI = 0 V or V Channel on capacitance Vin = 1.5 V 7 pF Total supply current VCC = 2.5 V 500 µA

CL = 7 pF; VCC = 2.5 V 140 ps

DESCRIPTION

This 10-bit bus switch is designed for 2.3 V to 2.7 V VCC operation and SSTL_2 select input levels.

Each Host port pin is multiplexed to one of four DIMM port pins. When the S pin is low the corresponding 10-bit bus switch is turned on. The on-state connects the Host port to the DIMM port through a 20 Ω nominal series resistance. When the S pin is high the switch is open and a high-impedance state exists between the two ports. The DIMM port is terminated with a 100 Ω resistor to ground when the S pin is high. The design is intended to have only one DIMM port active at any time.

The part incorporates a very low cross-talk design. It has a very low skew between outputs (< 50 ps) and low skew (< 50 ps) for rising and falling edges. The part has optional performance in DDR data bus applications.

Each switch has been optimized for connection to 1 or 2-bank DIMMs.

The low internal RC time constant of the switch (20 Ω × 7 pF) allows data transfer to be made with minimal propagation delay.

The CBTV4010 is characterized for operation from 0 to +85 °C.

CONDITIONS

= 25 °C; GND = 0 V

amb

TYPICAL UNIT

1.8 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER

TFBGA64 (Thin Fine Pitch BGA) 0 to +85 °C CBTV4010EE SOT746-1

2002 Feb 19 853-2315 27756

Philips Semiconductors Product data

CBTV401010-bit DDR SDRAM mux/bus switch

64-BALL BGA CONFIGURA TION

1 234 5 6 78 91011

GND

3DP9

HP9 3DP8 2DP8

HP8

GND

2DP7 1DP7

HP7 3DP6

C D

2DP9

1DP9

0DP9

G H

1DP8

0DP8

3DP7

1DP0

2DP0

0DP0

GND HP0

0DP7

2DP6

HP6 GND HP5

1DP6 0DP6

1DP1

2DP1 3DP1

HP2

3DP2 0DP3

HP3

GND

0DP4

HP4

3DP4

2DP5

1DP5

3DP0 0DP1 HP1 GND

3DP5

0DP2 1DP2 2DP2

1DP3 2DP3 3DP3

1DP4 2DP4 0DP5

NOTE: BLANK SPACE INDICATES NO BALL

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

B6, B9, C10, F2, F10, J2, J10, K3,

HP0–HP9 Host ports

K6, K9

A2, B1, B3, C2 S0–S3 Select

A5, A6, A7, A9,

A10, A11, B5, B7,

B8, B11, C11, D10,

E1, E2, E10, E11,

F1, F11, G1, G2,

G11, H2, H10, J1,

J11, K1, K4, K5,

K8, K10, K11, L1,

L2, L3, L5, L6, L7,

L9, L10, L11

B10, D2, G10, K2,

0DP0–3DP3 0DP1–3DP1 0DP2–3DP2 0DP3–3DP3 0DP4–3DP4 0DP5–3DP5 0DP6–3DP6 0DP7–3DP7 0DP8–3DP8 0DP9–3DP9

GND Ground

DIMM ports

K7,

A1, B2 V

Positive supply voltage

FUNCTION TABLE

INPUT

L Host port = DIMM port

H = High voltage level L = Low voltage level

FUNCTION

Host port = Disconnect

DIMM port = 100 Ω to GND

SA00589

2002 Feb 19

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