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CBTD3384 |
INTEGRATED CIRCUITS |
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CBTD3384
10-bit level shifting bus switch with 5-bit output enables
Product data
Supersedes data of 2000 Aug 30 2001 Dec 20 File under Integrated Circuits Ð ICL03
P s
on o s
Philips Semiconductors |
Product data |
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10-bit level shifting bus switch |
CBTD3384 |
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with 5-bit output enables |
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FEATURES
•5 Ω switch connection between two ports
•TTL compatible control input and output levels
•Designed to be used in 5 V to 3.3 V level shifting applications
•Latch-up protection exceeds 500 mA per JESD78
•ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-C101
DESCRIPTION
The CBTD3384 provides ten bits of high-speed TTL-compatible level shifting bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The gate voltage of the enabled switch is lowered by a diode to allow convenient level shifting between 5 V and 3.3 V levels on either side of the CBTD3384.
The CBTD3384 device is organized as two 5-bit bus switches with separate output-enable (OE) inputs. When OE is low, the switch is
on and port A is connected to B. When OE is high, the switch is open and high-impedance state exists between the two ports.
The CBTD3384 is characterized for operation from ±40 to +85 °C.
PIN CONFIGURATION
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1OE |
1 |
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24 |
Vcc |
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1B1 |
2 |
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23 |
2B5 |
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1A1 |
3 |
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22 |
2A5 |
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1A2 |
4 |
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21 |
2A4 |
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1B2 |
5 |
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20 |
2B4 |
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1B3 |
6 |
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19 |
2B3 |
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1A3 |
7 |
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18 |
2A3 |
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1A4 |
8 |
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17 |
2A2 |
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1B4 |
9 |
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16 |
2B2 |
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1B5 |
10 |
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15 |
2B1 |
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1A5 |
11 |
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14 |
2A1 |
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GND |
12 |
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13 |
2OE |
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SA00502
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PIN DESCRIPTION |
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PIN NUMBER |
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SYMBOL |
NAME AND FUNCTION |
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1, 13 |
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Output enables |
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1OE, |
2OE |
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3, 4, 7, 8, 11 |
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1A1±1A5 |
Inputs |
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14, 17, 18, 21, 22 |
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2A1±2A5 |
Inputs |
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2, 5, 6, 9, 10 |
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1B1±1B5 |
Outputs |
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15, 16, 19, 20, 23 |
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2B1±2B5 |
Outputs |
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12 |
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GND |
Ground (0V) |
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24 |
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VCC |
Positive supply voltage |
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QUICK REFERENCE DATA |
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SYMBOL |
PARAMETER |
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CONDITIONS |
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TYPICAL |
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UNIT |
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Tamb = 25 °C; GND = 0 V |
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tPLH |
Propagation delay |
CL = 50 pF; VCC = 5 V |
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250 |
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ps |
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tPHL |
An to Yn |
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CIN |
Input capacitance |
VI = 0 V or VCC |
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3 |
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pF |
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COUT |
Output capacitance |
Outputs disabled; VO = 0 V or VCC |
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6 |
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pF |
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ICCZ |
Total supply current |
Outputs disabled; VCC = 5.5 V |
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0.2 |
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μA |
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ORDERING INFORMATION
PACKAGES |
TEMPERATURE RANGE |
ORDER CODE |
DWG NUMBER |
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24-Pin Plastic SO |
±40 to +85 °C |
CBTD3384D |
SOT137-1 |
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24-Pin Plastic SSOP |
±40 to +85 °C |
CBTD3384DB |
SOT340-1 |
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24-Pin Plastic SSOP (QSOP) |
±40 to +85 °C |
CBTD3384DK |
SOT556-1 |
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24-Pin Plastic TSSOP |
±40 to +85 °C |
CBTD3384PW |
SOT355-1 |
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Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2001 Dec 20 |
2 |
853-2215 27501 |
Philips Semiconductors |
Product data |
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10-bit level shifting bus switch
CBTD3384
with 5-bit output enables
LOGIC SYMBOL
1A1 |
3 |
2 |
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1B1 |
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1A5 |
11 |
10 |
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1B5 |
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1OE |
1 |
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2A1 |
14 |
15 |
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2B1 |
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2A5 |
22 |
23 |
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2B5 |
13
2OE
SA00544
FUNCTION TABLE
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INPUTS |
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OUTPUTS |
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1A, 1B |
2A, 2B |
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1OE |
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2OE |
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L |
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L |
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1A = 1B |
2A= 2B |
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L |
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H |
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1A = 1B |
Z |
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H |
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L |
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Z |
2A = 2B |
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H |
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H |
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Z |
Z |
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H |
= |
High voltage level |
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L |
= |
Low voltage level |
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Z |
= |
High impedance ªoff º state |
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ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL |
PARAMETER |
CONDITIONS |
RATING |
UNIT |
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VCC |
DC supply voltage |
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±0.5 to +7.0 |
V |
IIK |
DC input diode current |
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±50 |
mA |
VI |
DC input voltage3 |
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±1.2 to +7.0 |
V |
ISW |
DC output diode current |
VO < 0 |
±128 |
mA |
Tstg |
Storage temperature range |
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±65 to +150 |
°C |
NOTES:
1.Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2.The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL |
PARAMETER |
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LIMITS |
UNIT |
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Min |
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Max |
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VCC |
DC supply voltage |
4.5 |
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5.5 |
V |
VIH |
High-level input voltage |
2.0 |
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Ð |
V |
VIL |
Low-level Input voltage |
Ð |
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0.8 |
V |
Tamb |
Operating free-air temperature range |
±40 |
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+85 |
°C |
2001 Dec 20 |
3 |
Philips Semiconductors |
Product data |
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10-bit level shifting bus switch
CBTD3384
with 5-bit output enables
DC ELECTRICAL CHARACTERISTICS
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LIMITS |
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SYMBOL |
PARAMETER |
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TEST CONDITIONS |
Tamb = ±40 °C to +85 °C |
UNIT |
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Min |
Typ1 |
Max |
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VIK |
Input clamp voltage |
VCC = 4.5 |
V; II = ±18 mA |
Ð |
Ð |
±1.2 |
V |
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VOH |
Output high pass voltage |
See Figure 1 |
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Ð |
Ð |
Ð |
V |
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II |
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Input leakage current |
VCC = 5.5 |
V; VI = GND or 5.5 V |
Ð |
Ð |
±1 |
μA |
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I |
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Quiescent supply current2 |
VCC = |
5.5 |
V; IO = 0, VI = VCC or GND; |
Ð |
Ð |
1.5 |
mA |
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CC |
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1OE=2OE=GND |
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ICC |
Additional supply current per |
VCC = 5.5 |
V, one input at 3.4 V, other inputs at |
Ð |
Ð |
2.5 |
mA |
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input pin2 |
V |
CC |
or GND |
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CI |
Control pins |
VI= 3 V or 0 |
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Ð |
3.2 |
Ð |
pF |
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CI(OFF) |
Port off capacitance |
VO = 3 V or 0, |
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= VCC |
Ð |
6 |
Ð |
pF |
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OE |
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VCC = 4.5 V; VI = 0 V; II = 64 mA |
Ð |
5 |
7 |
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r |
on |
3 |
On-resistance |
V |
CC |
= 4.5 |
V; V |
I |
= 0 V; I |
I |
= 30 mA |
Ð |
5 |
7 |
Ω |
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VCC = 4.5 |
V; VI = 2.4 V; II = ±15 mA |
Ð |
17 |
50 |
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NOTES:
1.All typical values are at VCC = 5 V, Tamb = 25 °C
2.This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND
3.Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals.
AC CHARACTERISTICS
GND = 0 V; tR = tF = 2.5 nS; CL = 50 pF
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LIMITS |
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UNIT |
SYMBOL |
PARAMETER DESCRIPTION |
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±40 °C to +85 °C |
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VCC = 5 V ± 0.5 V |
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Min |
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Mean |
Max |
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t |
Propagation delay1 |
Ð |
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Ð |
250 |
ps |
pd |
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tPZH |
Output enable time to High level |
2.3 |
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4.3 |
7.0 |
ns |
tPHZ |
Output disable time from High level |
1.7 |
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2.4 |
5.3 |
ns |
tPZL |
Output enable time to Low level |
2.3 |
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4.9 |
7.5 |
ns |
tPLZ |
Output disable time from Low level |
1.7 |
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4.2 |
5.3 |
ns |
NOTE:
1.This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
2001 Dec 20 |
4 |
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