Philips CBTD3384 Technical data
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INTEGRATED CIRCUITS
CBTD3384
10-bit level shifting bus switch
with 5-bit output enables
Product data
Supersedes data of 2000 Aug 30
File under Integrated Circuits — ICL03
2001 Dec 20
Philips Semiconductors Product data
10-bit level shifting bus switch
with 5-bit output enables
FEA TURES
•5 Ω switch connection between two ports
•TTL compatible control input and output levels
•Designed to be used in 5 V to 3.3 V level shifting applications
•Latch-up protection exceeds 500 mA per JESD78
•ESD protection exceeds 2000 V HBM per JESD22-A114, and
1000 V CDM per JESD22-C101
DESCRIPTION
The CBTD3384 provides ten bits of high-speed TTL-compatible
level shifting bus switching. The low on-state resistance of the
switch allows connections to be made with minimal propagation
delay. The gate voltage of the enabled switch is lowered by a diode
to allow convenient level shifting between 5 V and 3.3 V levels on
either side of the CBTD3384.
The CBTD3384 device is organized as two 5-bit bus switches with
separate output-enable (OE
on and port A is connected to B. When OE
open and high-impedance state exists between the two ports.
The CBTD3384 is characterized for operation from –40 to +85 °C.
) inputs. When OE is low, the switch is
is high, the switch is
PIN CONFIGURATION
1OE
1
2
1B1
3
1A1
4
1A2
5
1B2
6
1B3
7
1A3
8
1A4
9
1B4
10
1B5
11
1A5
12
GND
CBTD3384
24
Vcc
23
2B5
22
2A5
21
2A4
20
2B4
19
2B3
18
2A3
17
2A2
16
2B2
15
2B1
14
2A1
2OE
13
SA00502
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1, 13 1OE, 2OE Output enables
3, 4, 7, 8, 11 1A1–1A5 Inputs
14, 17, 18, 21, 22 2A1–2A5 Inputs
2, 5, 6, 9, 10 1B1–1B5 Outputs
15, 16, 19, 20, 23 2B1–2B5 Outputs
12 GND Ground (0V)
24 V
CC
Positive supply voltage
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay
An to Yn
Input capacitance VI = 0 V or V
Output capacitance Outputs disabled; VO = 0 V or V
Total supply current Outputs disabled; VCC = 5.5 V 0.2 µA
CL = 50 pF; VCC = 5 V 250 ps
CONDITIONS
T
= 25 °C; GND = 0 V
amb
CC
CC
TYPICAL UNIT
3 pF
6 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER
24-Pin Plastic SO –40 to +85 °C CBTD3384D SOT137-1
24-Pin Plastic SSOP –40 to +85 °C CBTD3384DB SOT340-1
24-Pin Plastic SSOP (QSOP) –40 to +85 °C CBTD3384DK SOT556-1
24-Pin Plastic TSSOP –40 to +85 °C CBTD3384PW SOT355-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2001 Dec 20 853-2215 27501
2
Philips Semiconductors Product data
SYMBOL
PARAMETER
UNIT
10-bit level shifting bus switch
with 5-bit output enables
LOGIC SYMBOL
1A1
1A5
1OE
2A1
2A5
2OE
3
11
1
14
22
13
2
1B1
10
1B5
15
2B1
23
2B5
SA00544
CBTD3384
FUNCTION TABLE
INPUTS OUTPUTS
1OE 2OE 1A, 1B 2A, 2B
L L 1A = 1B 2A= 2B
L H 1A = 1B Z
H L Z 2A = 2B
H H Z Z
H = High voltage level
L = Low voltage level
Z = High impedance “off” state
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
I
SW
T
stg
DC supply voltage –0.5 to +7.0 V
DC input diode current –50 mA
DC input voltage
DC output diode current VO < 0 ±128 mA
Storage temperature range –65 to +150 °C
PARAMETER CONDITIONS RATING UNIT
3
1, 2
–1.2 to +7.0 V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
Min Max
V
T
CC
V
V
amb
DC supply voltage 4.5 5.5 V
High-level input voltage 2.0 — V
IH
Low-level Input voltage — 0.8 V
IL
Operating free-air temperature range –40 +85 °C
2001 Dec 20
3
Philips Semiconductors Product data
3
10-bit level shifting bus switch
with 5-bit output enables
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS T
V
∆I
C
V
OH
I
I
CC
C
I(OFF)
Input clamp voltage VCC = 4.5 V; II = –18 mA — — –1.2 V
IK
Output high pass voltage See Figure 1 — — — V
Input leakage current VCC = 5.5 V; VI = GND or 5.5 V — — ±1 µA
I
VCC = 5.5 V; IO = 0, VI = VCC or GND;
Quiescent supply current
Additional supply current per
CC
input pin
Control pins VI= 3 V or 0 — 3.2 — pF
I
2
Port off capacitance VO = 3 V or 0, OE = V
2
1OE=2OE=GND
VCC = 5.5 V, one input at 3.4 V, other inputs at
VCC or GND
CC
VCC = 4.5 V; VI = 0 V; II = 64 mA — 5 7
r
on
On-resistance
VCC = 4.5 V; VI = 0 V; II = 30 mA — 5 7
VCC = 4.5 V; VI = 2.4 V; II = –15 mA — 17 50
NOTES:
1. All typical values are at V
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
= 5 V, T
CC
amb
= 25 °C
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
= –40 °C to +85 °C UNIT
amb
Min Typ
— — 1.5 mA
— — 2.5 mA
— 6 — pF
or GND
CC
CBTD3384
1
Max
Ω
AC CHARACTERISTICS
GND = 0 V; t
SYMBOL PARAMETER DESCRIPTION
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
= tF = 2.5 nS; CL = 50 pF
R
t
t
t
t
t
pd
PZH
PHZ
PZL
PLZ
Propagation delay
Output enable time to High level 2.3 4.3 7.0 ns
Output disable time from High level 1.7 2.4 5.3 ns
Output enable time to Low level 2.3 4.9 7.5 ns
Output disable time from Low level 1.7 4.2 5.3 ns
LIMITS
–40 °C to +85 °C
V
= 5 V ± 0.5 V
CC
UNIT
Min Mean Max
1
— — 250 ps
2001 Dec 20
4
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