Philips buk9775-55_2 Datasheet

Philips Semiconductors Product specification

TrenchMOS transistor BUK9775-55
Logic level FET

GENERAL DESCRIPTION QUICK REFERENCE DATA

N-channel enhancement mode logic SYMBOL PARAMETER MAX. UNIT
level field-effectpowertransistorina
plastic full-pack envelope using V
’trench’ technology. The device I
featuresverylow on-stateresistance P
and has integral zener diodes giving T
ESD protection up to 2kV. It is R

DS

D

tot
j

DS(ON)

intended for use in automotive and resistance VGS = 5 V
general purpose switching
applications.

PINNING - SOT186A PIN CONFIGURATION SYMBOL

Drain-source voltage 55 V
Drain current (DC) 11.7 A
Total power dissipation 19 W
Junction temperature 150 ˚C
Drain-source on-state 75 mΩ

PIN DESCRIPTION

case

d

1 gate
2 drain
3 source

case isolated

123

g

s

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V
V
±V
I

D

I

D

I

DM

P
T

DS
DGR

tot
stg

GS

, T

j

Drain-source voltage - - 55 V
Drain-gate voltage RGS = 20 kΩ -55V
Gate-source voltage - - 10 V
Drain current (DC) Tmb = 25 ˚C - 11.7 A
Drain current (DC) Tmb = 100 ˚C - 7.4 A
Drain current (pulse peak value) Tmb = 25 ˚C - 47 A
Total power dissipation Tmb = 25 ˚C - 19 W
Storage & operating temperature - - 55 150 ˚C

ESD LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

C

Electrostatic discharge capacitor Human body model - 2 kV
voltage, all pins (100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

R

th j-mb

R

th j-a

April 1998 1 Rev 1.000

Thermal resistance junction to with heatsink compound - 6.5 K/W
heatsink
Thermal resistance junction to in free air 55 - K/W
ambient

Philips Semiconductors Product specification

TrenchMOS transistor BUK9775-55

Logic level FET

STATIC CHARACTERISTICS

Tj= 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

(BR)DSS

V

GS(TO)

I

DSS

I

GSS

±V
R

DS(ON)

(BR)GSS

Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 55 - - V
voltage Tj = -55˚C 50 - - V
Gate threshold voltage VDS = VGS; ID = 1 mA 1 1.5 2 V

Tj = 150˚C 0.6 - - V

Tj = -55˚C - - 2.3 V

Zero gate voltage drain current VDS = 55 V; VGS = 0 V; - 0.05 10 µA

Tj = 150˚C - - 100 µA

Gate source leakage current VGS = ±5 V; VDS = 0 V - 0.02 1 µA

Tj = 150˚C - 5 µA
Gate-source breakdown IG = ±1 mA; 10 - - V
voltage
Drain-source on-state VGS = 5 V; ID = 7 A - 58 75 mΩ
resistance Tj = 150˚C - - 139 mΩ

DYNAMIC CHARACTERISTICS

Tmb = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

g
C

C
C

t
t
t
t

L

fs

iss
oss
rss

d on
r
d off
f

d

Forward transconductance VDS = 25 V; ID = 10 A 5 10 - S
Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 500 650 pF

Output capacitance - 110 135 pF
Feedback capacitance - 60 85 pF

Turn-on delay time VDD = 30 V; ID = 10 A; - 10 15 ns
Turn-on rise time VGS = 5 V; RG = 10 Ω - 4770ns
Turn-off delay time Resistive load - 28 40 ns
Turn-off fall time - 33 45 ns

Internal drain inductance Measured from drain lead 6 mm - 4.5 - nH

from package to centre of die

L

s

Internal source inductance Measured from source lead 6 mm - 7.5 - nH

from package to source bond pad

ISOLATION LIMITING VALUE AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

ISOL

C

ISOL

R.M.S isolation voltage from all f = 50-60Hz; sinusoidal waveform; - - 2500 V
three terminals to external R.H.≤65% clean & dustfree
heatsink

Capacitance from T2 to f = 1 MHZ - 10 - pF
external heatsink

April 1998 2 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9775-55

Logic level FET

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS

Tj = 25˚C unless otherwise specified

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

I

DR

I

DRM

V

SD

t

rr

Q

rr

AVALANCHE LIMITING VALUE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

W

DSS

Continuous reverse drain - - 11.7 A
current
Pulsed reverse drain current - - 47 A
Diode forward voltage IF = 11.7 A; VGS = 0 V - 0.95 1.2 V

Reverse recovery time IF = 11.7 A; -dIF/dt = 100 A/µs; - 32 - ns
Reverse recovery charge VGS = -10 V; VR = 30 V - 0.12 - µC

Drain-source non-repetitive ID = 10 A; VDD ≤ 25 V; - - 30 mJ
unclamped inductive turn-off VGS = 5 V; RGS = 50 Ω; Tmb = 25 ˚C
energy

April 1998 3 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9775-55
Logic level FET

PD%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Normalised Power Derating

Tmb / C

Fig.1. Normalised power dissipation.

PD% = 100⋅PD/P

ID%

120
110
100

90
80
70
60
50
40
30
20
10

0

0 20 40 60 80 100 120 140

Tmb / C

= f(Tmb)

D 25 ˚C

Normalised Current Derating

Fig.2. Normalised continuous drain current.

ID% = 100⋅ID/I

= f(Tmb); conditions: VGS ≥ 5 V

D 25 ˚C

Zth/ (K/W)

10

0.5

0.2

1

0.1

0.05

p

0.02

0

0.1

0.01

1.0E-06 0.0001 0.01 1 100
t/s

t

P

D

t

p

D =

T

t

T

Fig.4. Transient thermal impedance.

Z

= f(t); parameter D = tp/T

th j-mb

50

ID/A

40

30

20

10

0

0246810

VDS/V

10.0 8.0

VGS/V =

Fig.5. Typical output characteristics, Tj = 25 ˚C

ID = f(VDS); parameter V

GS

6.0

5.4

5.0

4.8

4.6

4.4

4.2

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

.

100

ID/A

RDS(ON) = VDS/ID

10

1

0.1
1 10 100

DC

VDS/V

Fig.3. Safe operating area. Tmb = 25 ˚C

ID & IDM = f(VDS); IDM single pulse; parameter t

tp =

1 uS

10 uS

100uS

1 mS
10 mS

100 mS

p

RDS(ON)/mOhm

90

VGS/V =

85

80

75

70

65

60

55

5 10152025

ID/A

Fig.6. Typical on-state resistance, Tj = 25 ˚C

R

= f(ID); parameter V

DS(ON)

4.2

4

4.4
5

4.6

4.8

.

GS

April 1998 4 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9775-55
Logic level FET

25

ID/A

20

15

10

5

Tj/C = 150 25

0

012345

VGS/V

Fig.7. Typical transfer characteristics.

ID = f(VGS) ; conditions: VDS = 25 V; parameter T

Transconductance, gfs (S)

15
14
13
12
11
10

9
8
7
6
5

0 5 10 15 20 25

Fig.8. Typical transconductance, Tj = 25 ˚C

Drain current, ID (A)

.

gfs = f(ID); conditions: VDS = 25 V

VGS(TO) / V

2.5
max.

2

typ.

1.5

min.

1

0.5

0

-100 -50 0 50 100 150 200
Tj / C

BUK98xx-55

Fig.10. Gate threshold voltage.

V

j

1E-01

1E-02

1E-03

1E-04

1E-05

1E-05

= f(Tj); conditions: ID = 1 mA; VDS = V

GS(TO)

Sub-Threshold Conduction

2% typ

0 0.5 1 1.5 2 2.5 3

98%

GS

Fig.11. Sub-threshold drain current.

ID = f(V

; conditions: Tj = 25 ˚C; VDS = V

GS)

GS

a

2.5

2

1.5

1

0.5

-100 -50 0 50 100 150 200

BUK98XX-55

Rds(on) normalised to 25degC

Tmb / degC

Fig.9. Normalised drain-source on-state resistance.

a = R

DS(ON)/RDS(ON)25 ˚C

= f(Tj); ID = 10 A; VGS = 5 V

1
.9
.8
.7
.6
.5

Thousands pF

.4
.3
.2
.1

0

0.01 0.1 1 10 100

Fig.12. Typical capacitances, C

VDS/V

, C

iss

C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

oss

, C

rss

.

Ciss

Coss
Crss

April 1998 5 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9775-55
Logic level FET

6

VGS/V

5

VDS = 14V

4

3

2

1

0

024681012

QG/nC

VDS = 44V

Fig.13. Typical turn-on gate-charge characteristics.

V

= f(QG); conditions: ID = 20 A; parameter V

GS

100

IF/A

80

60

Tj/C = 150 25

40

DS

WDSS%

120
110
100

90
80
70
60
50
40
30
20
10

0

20 40 60 80 100 120 140

Tmb / C

Fig.15. Normalised avalanche energy rating.

W

% = f(Tmb); conditions: ID = 17 A

DSS

+

L

VDS

VGS

0

T.U.T.

-

VDD

-ID/100

20

0

0 0.5 1 1.5

VSDS/V

Fig.14. Typical reverse diode current.

IF = f(V

); conditions: V

SDS

= 0 V; parameter T

GS

RGS

R 01

shunt

Fig.16. Avalanche energy test circuit.

RG

2

D

⋅BV

DSS

/(BV

RD

DSS−VDD

VDS

T.U.T.

)

VDD

+

-

W

= 0.5 ⋅LI

j

VGS

0

DSS

Fig.17. Switching test circuit.

April 1998 6 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9775-55

Logic level FET

MECHANICAL DATA

Dimensions in mm
Net Mass: 2 g

10.3

Recesses (2x)

2.5

0.8 max. depth

3 max.

not tinned

13.5
min.

0.4

M

max

3.2

3.0

123

5.08

2.8

2.54

15.8
max.

3

19

max.

seating

plane

0.5

2.5

4.6

max

2.9 max

6.4

0.6

2.5

15.8
max

Fig.18. SOT186A; The seating plane is electrically isolated from all terminals.

1.3

1.0 (2x)

0.9

0.7

Notes

1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent
damage to MOS gate oxide.

2. Refer to mounting instructions for F-pack envelopes.

3. Epoxy meets UL94 V0 at 1/8".

April 1998 7 Rev 1.000

Philips Semiconductors Product specification

TrenchMOS transistor BUK9775-55

Logic level FET

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

 Philips Electronics N.V. 1998

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.

The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.

April 1998 8 Rev 1.000