Philips buk7e07-55b Datasheet

BUK7E07-55B

N-channel TrenchMOS standard level FET

Rev. 01 — 29 January 2008 Product data sheet

1. Product profile

1.1 General description

N-channel enhancement mode power Field-Effect Transistor (FET) in a plastic package
using NXP High-Performance Automotive(HPA) TrenchMOS technology. This product has
been designed and qualified to the appropriate AEC standard for use in Automotive critical
applications.

1.2 Features

n Very low on-state resistance n Q101 compliant
n 175 °C rated n Standard level compatible

1.3 Applications

n Automotive systems n General purpose power switching
n Motors, lamps and solenoids n 12 V and 24 V loads

1.4 Quick reference data

n E

DS(AL)S

n ID≤ 75 A n P

≤ 351 mJ n R

= 5.8 mΩ (typ)

DSon

≤ 203 W

tot

2. Pinning information

Table 1. Pinning

Pin Description Simplified outline Symbol

1 gate (G)
2 drain (D)
3 source (S)
mb mounting base; connected to drain (D)

mb

321

SOT226 (I2PAK)

G

mbb076

D

S

NXP Semiconductors

BUK7E07-55B

N-channel TrenchMOS standard level FET

3. Ordering information

Table 2. Ordering information

Type number Package

Name Description Version

BUK7E07-55B I2PAK plastic single-ended package (I2PAK); low-profile 3-lead TO-220AB SOT226

4. Limiting values

Table 3. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DS

V

DGR

V

GS

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

DR

I

DRM

Avalanche ruggedness

E

DS(AL)S

E

DS(AL)R

drain-source voltage -55V
drain-gate voltage (DC) RGS=20kΩ -55V
gate-source voltage - ±20 V
drain current Tmb=25°C; VGS= 10 V; see Figure 2 and 3

= 100 °C; VGS= 10 V; see Figure 2

T

mb

[1]

- 119 A

[2]
[2]

75 A

-75A
peak drain current Tmb=25°C; pulsed; tp≤ 10 µs; see Figure 3 - 478 A
total power dissipation Tmb=25°C; see Figure 1 - 203 W
storage temperature −55 +175 °C
junction temperature −55 +175 °C

reverse drain current Tmb=25°C

[2]

-75A
peak reverse drain current Tmb=25°C; pulsed; tp≤ 10 µs - 478 A

non-repetitive drain-source avalanche
energy

repetitive drain-source avalanche

Unclamped inductive load; ID=75A;
V

≤ 55 V; VGS= 10 V; RGS = 50 Ω; starting at

DS

T

=25°C

j

Repetitive rating defined in Figure 16

- 351 mJ

[3]

--J
energy

[1] Current is limited by chip power dissipation rating.
[2] Continuous current is limited by package.
[3] Conditions:

a) Maximum value not quoted.
b) Single-pulse avalanche rating limited by T
c) Repetitive avalanche rating limited by an average junction temperature of 170 °C.
d) Refer to application note

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 29 January 2008 2 of 12

AN10273

for further information.

j(max)

of 175 °C.

NXP Semiconductors

BUK7E07-55B

N-channel TrenchMOS standard level FET

120

P

der

(%)

80

40

0

0 20015050 100

P

der

----------------------- -

P

tot 25°C()

P

tot

100 %×=

003aab844

Tmb (°C)

Fig 1. Normalized total power dissipation as a

function of mounting base temperature

3

10

120

I

D

(A)

80

40

0

(1)

0 20015050 100

003aac120

Tmb (°C)

VGS≥ 10 V

(1) Capped at 75 A due to package.

Fig 2. Continuous drain current as a function of

mounting base temperature

003aac121

I

(A)

D

2

10

10

1

−1

10

Limit R

DSon

= VDS / I

D

(1)

DC

101

VDS (V)

tp = 10 µs

100 µs

1 ms

10 ms

100 ms

Tmb=25°C; IDM is single pulse.

(1) Capped at 75 A due to package.

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

2

10

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 29 January 2008 3 of 12

NXP Semiconductors

BUK7E07-55B

N-channel TrenchMOS standard level FET

5. Thermal characteristics

Table 4. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

th(j-mb)

R

th(j-a)

thermal resistance from junction to mounting base - - - 0.74 K/W
thermal resistance from junction to ambient vertical in still air - 60 - K/W

1

Z

th(j-mb)

(K/W)

10

10

10

−1

−2

−3

−6

10

δ = 0.5

0.2

0.1

0.05

0.02

single pulse

P

t

p

T

−5

10

−4

10

−3

10

−2

−1

10

tp (s)

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

003aac122

t

p

δ =

T

t

110

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 29 January 2008 4 of 12

NXP Semiconductors

BUK7E07-55B

N-channel TrenchMOS standard level FET

6. Characteristics

Table 5. Characteristics

Tj=25°C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V

(BR)DSS

V

GS(th)

I

DSS

I

GSS

R

DSon

Dynamic characteristics

Q

G(tot)

Q

GS

Q

GD

C

iss

C

oss

C

rss

t

d(on)

t

r

t

d(off)

t

f

L

D

L

S

Source-drain diode

V

SD

t

rr

Q

r

drain-source breakdown voltage ID= 0.25 mA; VGS=0V

=25°C 55--V

T

j

= −55 °C 50--V

T

j

gate-source threshold voltage ID= 1 mA; VDS=VGS; see Figure 9 and 10

=25°C 234V

T

j

= 175 °C 1--V

T

j

= −55 °C - - 4.4 V

T

j

drain leakage current VDS=55V; VGS=0V

=25°C - 0.02 1 µA

T

j

= 175 °C - - 500 µA

T

j

gate leakage current VGS= ±20 V; VDS=0V - 2 100 nA
drain-source on-state resistance VGS= 10 V; ID= 25 A; see Figure 6 and 8

=25°C - 5.8 7.1 mΩ

T

j

= 175 °C - - 14.2 mΩ

T

j

total gate charge ID= 25 A; VDS=44V; VGS=10V;

see

gate-source charge - 12 - nC

Figure 14

-53-nC

gate-drain charge - 17 - nC
input capacitance VGS=0V; VDS= 25 V; f = 1 MHz;

see

output capacitance - 554 665 pF

Figure 12

- 2820 3760 pF

reverse transfer capacitance - 200 274 pF
turn-on delay time VDS=30V; RL= 1.2 Ω;

V

=10V;RG=10Ω

rise time -52-ns

GS

-24-ns

turn-off delay time - 77 - ns
fall time -41-ns
internal drain inductance measured from drain lead 6 mm from

- 4.5 - nH

package to centre of die

internal source inductance measured from source lead

- 7.5 - nH

to source bond pad

source-drain voltage IS= 25 A; VGS= 0 V; see Figure 15 - 0.85 1.2 V
reverse recovery time IS= 20 A; dIS/dt = −100 A/µs;

V

= 0 V; VR=30V

recovered charge - 60 - nC

GS

-62-ns

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 29 January 2008 5 of 12

NXP Semiconductors

BUK7E07-55B

N-channel TrenchMOS standard level FET

003aac123

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

VDS (V)

I

(A)

300

D

200

100

0

0108462

9.01020
V

(V) = 8.5

GS

Tj=25°CT

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

003aac125

8.0

9.0

10

R

DSon

(mΩ)

25

20

15

10

VGS (V) = 6.0

6.5

7.0

7.5

25

R

DSon

(mΩ)

20

15

10

5

0

5201510

=25°C; ID=25A

j

003aac124

VGS (V)

Fig 6. Drain-source on-state resistance as a function

of gate-source voltage; typical values

2

a

1.5

1

003aab906

5

0

0 300200100

ID (A)

Tj=25°C

Fig 7. Drain-source on-state resistance as a function

of drain current; typical values

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

0.5

0

−60 180120060

R

DSon

=

a

----------------------------- -

R

DSon 25°C()

T

(°C)

j

Fig 8. Normalized drain-source on-state resistance

factor as a function of junction temperature

Product data sheet Rev. 01 — 29 January 2008 6 of 12

NXP Semiconductors

BUK7E07-55B

N-channel TrenchMOS standard level FET

5

V

GS(th)

(V)

4

3

2

1

0

−60 160120060

ID= 1 mA; VDS=V

GS

max

typ

min

003aab852

Tj (°C)

Fig 9. Gate-source threshold voltage as a function of

junction temperature

003aac126

g
(S)

60

fs

40

−1

10
I

D

(A)

−2

10

−3

10

−4

10

−5

10

−6

10

0642

Tj=25°C; VDS=V

min typ max

GS

003aab853

VGS (V)

Fig 10. Sub-threshold drain current as a function of

gate-source voltage

003aac127

iss

C

(nF)

4

C

3

20

0

0 1007525 50

ID (A)

Tj=25°C; VDS=25V VGS= 0 V; f=1 MHz

Fig 11. Forward transconductance as a function of

drain current; typical values

2

1

0

−2

10

−1

C

oss

C

rss

2

1

1010

10

(V)

V

DS

Fig 12. Input, output and reverse transfer capacitances

as a function of drain-source voltage; typical
values

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 29 January 2008 7 of 12

NXP Semiconductors

BUK7E07-55B

N-channel TrenchMOS standard level FET

100

I

D

(A)

75

50

25

0

08624

Tj = 175 °C Tj = 25 °C

003aac128

VGS (V)

VDS = 25 V Tj=25°C; ID=25A

Fig 13. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

003aac130

(A)

I

100

S

75

50

10

V

GS

(V)

8

6

4

2

0

0604020

VDD = 14 V

003aac129

VDD = 44 V

QG (nC)

Fig 14. Gate-source voltage as a function of gate

charge; typical values

003aac131

(1)

(2)

I

AL

(A)

2

10

10

Tj = 175 °C Tj = 25 °C

25

0

0.0 1.51.00.5
VSD (V)

1

−1

10

−3

10

−2

−1

10

(3)

tAL (ms)

10110

VGS= 0 V See Table note 3 of Table 3 Limiting values.

(1) Single-pulse; Tj=25°C.
(2) Single-pulse; Tj= 150 °C.
(3) Repetitive.

Fig 15. Source (diode forward) current as a function of

source-drain (diode forward) voltage; typical
values

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

Fig 16. Single-pulse and repetitive avalanche rating;

avalanche current as a function of avalanche
time

Product data sheet Rev. 01 — 29 January 2008 8 of 12

NXP Semiconductors

BUK7E07-55B

N-channel TrenchMOS standard level FET

7. Package outline

Plastic single-ended package (I2PAK); low-profile 3-lead TO-220AB SOT226

A

D

1

D

E

A

mounting

base

1

b

b

1.3

1.0

1

c

1

0.7

0.4

L

DIMENSIONS (mm are the original dimensions)

A

UNIT

Ab

1

1.40

4.5

mm

4.1

1.27

0.85

0.60

123

b

e

e

05

D

D

max

1

1.6

11

1.2

E

10.3

9.7

L

1

Q

10 mm

scale

eQ

2.54

15.0

13.5

L

L

1

2.6

3.30

2.2

2.79

c

OUTLINE
VERSION

SOT226

REFERENCES

IEC JEDEC JEITA

low-profile

3-lead TO-220AB

EUROPEAN

PROJECTION

ISSUE DATE

05-06-23
06-02-14

Fig 17. Package outline SOT226 (I2PAK)

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 29 January 2008 9 of 12

NXP Semiconductors

N-channel TrenchMOS standard level FET

BUK7E07-55B

8. Revision history

Table 6. Revision history

Document ID Release date Data sheet status Change notice Supersedes

BUK7E07-55B_1 20080129 Product data - -

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 29 January 2008 10 of 12

NXP Semiconductors

9. Legal information

9.1 Data sheet status

BUK7E07-55B

N-channel TrenchMOS standard level FET

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL

[1][2]

Product status

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

9.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or
warranties, expressedor implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected

[3]

http://www.nxp.com.

Definition

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at

http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyanceor implication of any license under any copyrights, patents
or other industrial or intellectual property rights.

9.4 Trademarks

Notice: All referenced brands,product names, service names and trademarks
are the property of their respective owners.

TrenchMOS —is a trademark of NXP B.V.

10. Contact information

For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]

BUK7E07-55B_1 © NXP B.V. 2008. All rights reserved.

Product data sheet Rev. 01 — 29 January 2008 11 of 12

NXP Semiconductors

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

9.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11

10 Contact information. . . . . . . . . . . . . . . . . . . . . 11

11 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

BUK7E07-55B

N-channel TrenchMOS standard level FET

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2008. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

Date of release: 29 January 2008

Document identifier: BUK7E07-55B_1