Philips buk6212-40c Datasheet

BUK6212-40C

N-channel TrenchMOS intermediate level FET

Rev. 2 — 21 September 2010 Product data sheet

1. Product profile

1.1 General description

Intermediate level gate drive N-channel enhancement mode Field-Ef fect Transistor (FET)
in a plastic package using TrenchMOS technology. This product has been designed and
qualified to the appropriate AEC standard for use in automotive critical applications.

1.2 Features and benefits

 AEC Q101 compliant
 Suitable for standard and logic level

 Suitable for thermally demanding

environments due to 175 °C rating

gate drive sources

1.3 Applications

 12 V Automotive systems
 Electric and electro-hydraulic power

steering

 Motors, lamps and solenoids

 Start-Stop micro-hybrid applications
 Transmission control
 Ultra high performance power

switching

1.4 Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

V

DS

I

D

P

tot

Static characteristics

R

DSon

drain-source
voltage

drain current VGS=10V; Tmb=25°C;

total power
dissipation

drain-source
on-state
resistance

Tj≥ 25 °C; Tj≤ 175°C --40V

[1]

--50A

see Figure 1
see Figure 2 --80W

VGS=10V; ID=12A;
T

= 25 °C; see Figure 11

mb

- 9.5 11.2 mΩ

NXP Semiconductors

3

2

mb

1

S

D

G

mbb076

Table 1. Quick reference data …continued

Symbol Parameter Conditions Min Typ Max Unit

Avalanche ruggedness

E

DS(AL)S

Dynamic characteristics

Q

GD

[1] Continuous current is limited by package.

2. Pinning information

N-channel Tre nchMOS intermediate level FET

non-repetitive
drain-source
avalanche energy

gate-drain charge ID=25A; VDS=32V;

ID=50A; V

=10V; T

V

GS

sup

j(init)

≤ 40 V;

=25°C;

unclamped

VGS= 10 V; see Figure 13;
see Figure 14

BUK6212-40C

--55mJ

-10.1-nC

Table 2. Pinning information

Pin Symbol Description Simplified outline Graphic symbol

1 G gate
2 D drain
3Ssource
mb D mounting base; connected to

drain

SOT428 (DPAK)

3. Ordering information

Table 3. Ordering information

Type number Package

BUK6212-40C DPAK plastic single-ended surface-mounted package (DPAK); 3 leads

Name Description Version

(one lead cropped)

SOT428

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 2 of 14

NXP Semiconductors

4. Limiting values

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V

DS

V

GS

I

D

I

DM

P

tot

T

stg

T

j

Source-drain diode

I

S

I

SM

Avalanche ruggedness

E

DS(AL)S

E

DS(AL)R

drain-source voltage Tj≥ 25 °C; Tj≤ 175 °C - 40 V
gate-source voltage Pulsed

DC

drain current Tmb=25°C; VGS=10V; see Figure 1

=100°C; VGS= 10 V; see Figure 1 -41A

T

mb

peak drain current Tmb=25°C; tp≤ 10 µs; pulsed;

[1]
[2]
[3]

-20 20 V

-16 16 V

-50A

- 233 A

see Figure 3
total power dissipation see Figure 2 -80W
storage temperature -55 175 °C
junction temperature -55 175 °C

source current Tmb=25°C

[3]

-50A

peak source current tp≤ 10 µs; pulsed; Tmb= 25 °C - 233 A

non-repetitive drain-source
avalanche energy

repetitive drain-source

ID=50A; V

T

j(init)

sup

= 25 °C; unclamped

≤ 40 V; VGS=10V;

[4][5][6]

-55mJ

--J

avalanche energy

[1] Accumulated pulse duration not to exceed 5 minutes.
[2] -16V accumulated duration not to exceed 168 hrs.
[3] Continuous current is limited by package.
[4] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[5] Repetitive avalanche rating limited by an average junction temperature of 170 °C.
[6] Refer to application note AN10273 for further information.

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 3 of 14

NXP Semiconductors

003aae456

0

20

40

60

0 50 100 150 200

T

mb

(C)

I

D

(A)

(1)

Tmb (°C)

0 20015050 100

03aa16

40

80

120

P

der

(%)

0

003aa e457

10

−1

1

10

10

2

10

3

10

−1

1 10 10

2

VDS (V)

I

D

(A)

Limit R

DSon

= VDS / I

D

DC

100 ms

10 ms

1 ms

100 μs

tp = 10 μs

(1) Capped at 50 A due to package

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Fig 1. Continuous drain current as a function of

mounting base temperature

Fig 2. Normalized total power dissipation as a

function of mounting base temperature

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 4 of 14

NXP Semiconductors

003aae458

10

−2

10

−1

1

10

10

−6

10

−5

10

−4

10

−3

10

−2

10

−1

1

t

p

(s)

single shot

0.2

0.1

0.05

0.02

Z

th(j-mb)

(K/W)

δ = 0.5

t

p

t

p

T

P

t

T

δ =

5. Thermal characteristics

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Table 5. Thermal characteristics

Symbol Parameter Conditions Min Typ Max Unit

R

th(j-mb)

thermal resistance from junction

see Figure 4 --1.87K/W

to mounting base

Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 5 of 14

NXP Semiconductors

6. Characteristics

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Table 6. Characteristics

Symbol Parameter Conditions Min Typ Max Unit

Static characteristics

V

(BR)DSS

V

GS(th)

I

DSS

I

GSS

R

DSon

drain-source
breakdown voltage

gate-source threshold
voltage

drain leakage current VDS=40V; VGS=0V; Tj= 25 °C - 0.02 1 µA

gate leakage current VDS=0V; VGS=20V; Tj= 25 °C - 2 100 nA

drain-source on-state
resistance

ID=250µA; VGS=0V; Tj=25°C 40--V

=250µA; VGS=0V; Tj= -55 °C 36 - - V

I

D

ID=1mA; VDS=VGS; Tj=25°C;

1.8 2.3 2.8 V

see Figure 9; see Figure 10

=1mA; VDS=VGS; Tj=-55°C;

I

D

see Figure 9
I

=1mA; VDS=VGS; Tj= 175 °C 0.8 - - V

D

=40V; VGS=0V; Tj= 175 °C - - 500 µA

V

DS

=0V; VGS=-20V; Tj= 25 °C - 2 100 nA

V

DS

; see Figure 10

VGS=10V; ID=12A; Tmb=25°C;

--3.3V

- 9.5 11.2 mΩ

see Figure 11

=5V; ID=12A; Tj=25°C;

V

GS

- 13 16.3 mΩ

see Figure 11

=4.5V; ID=12A; Tmb=25°C;

V

GS

- 1520mΩ

see Figure 11
V

=10V; ID=12A; Tj= 175 °C;

GS

- - 23.5 mΩ

see Figure 12; see Figure 11

Dynamic characteristi cs

Q

Q
Q
C
C
C

G(tot)

GS

GD
iss
oss
rss

total gate charge ID=25A; VDS=32V; VGS=10V;

see Figure 13
I

=25A; VDS=32V; VGS=5V;

D

see Figure 13

; see Figure 14

; see Figure 14
gate-source charge ID=25A; VDS=32V; VGS=10V;
gate-drain charge - 10.1 - nC

see Figure 13; see Figure 14

input capacitance VGS=0V; VDS=25V; f=1MHz;

T

=25°C; see Figure 15

output capacitance - 205 250 pF

j

reverse transfer

- 33.9 - nC

- 19.5 - nC

-5.4-nC

- 1422 1900 pF

- 143 200 pF

capacitance

t

d(on)

t

r

t

d(off)

t

f

L

D

L

S

turn-on delay time VDS=30V; RL=1.2Ω; VGS=10V;

=10Ω

R

rise time - 21 - ns

G(ext)

turn-off delay time - 54 - ns
fall time - 32 - ns
internal drain

inductance
internal source

inductance

measured from source lead to source
bond pad; ; T

=25°C

j

Tj= 25 °C; measured from drain to
centre of die;

-9.7-ns

-3.5-nH

-2.5-nH

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 6 of 14

NXP Semiconductors

003aae459

0

20

40

60

80

100

00.511.52
V

DS

(V)

I

D

(A)

3.8

4

4.5

5

8

3.2

VGS (V) = 10

3.4

3.6

003aae461

0

20

40

60

0 10203040

I

D

(A)

g

fs

(S)

003aae460

0

20

40

60

0246

V

GS

(V)

I

D

(A)

Tj = 175 °C

Tj = 25 °C

003aae464

0

10

20

30

40

0 5 10 15 20

V

GS

(V)

R

DSon

(mΩ)

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Table 6. Characteristics …continued

Symbol Parameter Conditions Min Typ Max Unit

Source-drain diode

V

SD

source-drain voltage IS=25A; VGS=0V; Tj=25°C;

see Figure 16

t

rr

Q

r

reverse recovery time IS=20A; dIS/dt = -100 A/µs; VGS=0V;
recovered charge - 38 - nC

VDS=25V

-0.91.2V

- 35.6 - ns

Fig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values

Fig 7. Transfer characteristics: drain current as a

function of gate-source voltage; typical values

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 7 of 14

Fig 6. Forward transconductance as a function of

drain current; typical values

Fig 8. Drain-source on-state resistance as a function

of gate-source voltage; typical values

NXP Semiconductors

003aad805

0

1

2

3

4

-60 0 60 120 180
T

j

(°C)

V

GS(th)

(V)

max

typ

min

003aad806

10

-6

10

-5

10

-4

10

-3

10

-2

10

-1

01234

V

GS

(V)

I

D

(A)

max

typ

min

003aae462

0

10

20

30

40

0 20406080

I

D

(A)

R

DSon

(mΩ)

4.5

10

VGS (V) = 3.8

5

4.0

003aad793

0

0.5

1

1.5

2

2.5

-60 0 60 120 180

T

j

(°C)

a

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Fig 9. Gate-source threshold voltage as a function of

junction temperature

Fig 11. Drain-source on-state resistance as a fun ction

of drain current; typical values

Fig 10. Sub-threshold drain current as a function of

gate-source voltage

Fig 12. Normalized drain-source on-state resistance

factor as a function of junction temperature

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 8 of 14

NXP Semiconductors

003aaa508

V

GS

V

GS(th)

Q

GS1QGS2

Q

GD

V

DS

Q

G(tot)

I

D

Q

GS

V

GS(pl)

003aae466

0

2

4

6

8

10

010203040

Q

G

(nC)

V

GS

(V)

V

DS

= 32 V

VDS = 14 V

003aae467

10

2

10

3

10

4

10

−2

10

−1

1 10 10

2

VDS (V)

C

(pF)

C

iss

C

rss

C

oss

003aae468

0

20

40

60

80

00.511.5

V

SD

(V)

I

S

(A)

Tj = 175 °C

Tj = 25 °C

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Fig 13. Gate charge waveform definitions Fig 14. Gate-source vo ltage as a function of gate

charge; typical values

Fig 15. In put, output and reverse trans fer capacitances

as a function of drain-source voltage; typical
values

Fig 16. Source (diode forward) current as a function of

source-drain (diode forward) voltage; typical
values

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 9 of 14

NXP Semiconductors

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT428 SC-63

TO-252

SOT428

06-02-14

06-03-16

DIMENSIONS (mm are the original dimensions)

Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)

A

2

13

E

1

D

2

D

1

H

D

L

L

1

L

2

e

1

e

mounting
base

wA

M

b

E

b

2

b

1

c

A

1

y

0 5 10 mm

scale

UNIT

mm

0.93

0.46

5.46

5.00

0.56

0.20

6.22

5.98

6.73

6.47

10.4

9.6

2.95

2.55

A

1

2.38

2.22

Ab

2

1.1

0.9

b

1

e

1

0.89

0.71

bcD

1

0.9

0.5

L

2

Ee

2.285 4.57

4.0

D

2

min

4.45

E

1

min

0.5

L

1

min

H

D

Lw

0.2

y

max

0.2

A

7. Package outline

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Fig 17. Package outline SOT428 (DPAK)

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 10 of 14

NXP Semiconductors

8. Revision history

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Table 7. Revision history

Document ID Release date Data sheet status Change notice Supersedes

BUK6212-40C v.2 20100921 Product data sheet - BUK6212-40C v.1
Modifications:

• Status changed from Objective to Product.

• Various changes to content.

BUK6212-40C v.1 20100512 Objective data sheet - -

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 11 of 14

NXP Semiconductors

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

9. Legal information

9.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) desc r ibed in this document may have changed since this document was published and may differ in case of multiple devices. The latest product

status information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

9.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to co nt ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.

9.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.

Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warran ted to be
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.

Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteri stics sections of this
document, and as such is not complete, exhaustive or legally binding.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.

NXP Semiconductors does not accept any liability related to any default ,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third part y
customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms
agreed in a valid written individual agreement. In case an individual

, unless otherwise

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 12 of 14

NXP Semiconductors

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpret ed or
construed as an offer to sell products that is open f or accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.

9.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks
are the property of their respective owners.

Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.

HD Radio and HD Radio logo — are trademarks of iBiquity Digital

Corporation.

10. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

BUK6212-40C All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

Product data sheet Rev. 2 — 21 September 2010 13 of 14

NXP Semiconductors

11. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.1 General description . . . . . . . . . . . . . . . . . . . . . .1

1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3

5 Thermal characteristics . . . . . . . . . . . . . . . . . . .5

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6

7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10

8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11

9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12

9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12

9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .12

9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13

10 Contact information. . . . . . . . . . . . . . . . . . . . . .13

BUK6212-40C

N-channel Tre nchMOS intermediate level FET

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2010. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

Date of release: 21 September 2010

Document identifier: BUK62 12-40C