Page 1
DISCRETE SEMICONDUCTORS
DATA SH EET
ook, halfpage
M3D109
BSS192
P-channel enhancement mode
vertical D-MOS transistor
Product specification
Supersedes data of 1997 Jun 20
2002 May 22
Page 2
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
FEATURES
• Direct interface to C-MOS, TTL, etc.
• High-speed switching
• No secondary breakdown.
APPLICATIONS
• Line current interrupter in telephone sets
• Relay, high-speed and line transformer drivers.
DESCRIPTION
P-channel enhancement mode vertical D-MOS transistor
in a SOT89 package.
PINNING - SOT89
PIN SYMBOL DESCRIPTION
1 s source
2 d drain
3 g gate
handbook, halfpage
g
123
Bottom view
Marking code: KB.
MAM354
Fig.1 Simplified outline and symbol.
BSS192
d
s
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MAX. UNIT
V
V
I
D
R
DS
GSth
DSon
drain-source voltage (DC) −240 V
gate-source threshold voltage ID= −1 mA; VGS=V
DS
−2.8 V
drain current (DC) −200 mA
drain-source on-state resistance ID= −200 mA; VGS= −10 V 12 Ω
2002 May 22 2
Page 3
Philips Semiconductors Product specification
P-channel enhancement mode
BSS192
vertical D-MOS transistor
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DS
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
Note
1. Device mounted on a ceramic substrate; area 2.5 cm2; thickness 0.7 mm.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th j-a
drain-source voltage (DC) −−240 V
gate-source voltage (DC) open drain −±20 V
drain current (DC) −−200 mA
peak drain current −−600 mA
total power dissipation T
≤ 25 °C; note 1 − 1W
amb
storage temperature −65 +150 °C
junction temperature − 150 °C
thermal resistance from junction to ambient note 1 125 K/W
Note
2
1. Device mounted on a ceramic substrate; area 2.5 cm
; thickness 0.7 mm.
CHARACTERISTICS
Tj=25°C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
V
GSth
I
DSS
I
GSS
R
DSon
forward transfer admittance VDS= −25 V; ID= −200 mA 60 200 − mS
y
fs
C
iss
C
oss
C
rss
drain-source breakdown voltage VGS= 0; ID= −10 µA −240 −−V
gate-source threshold voltage VGS=VDS; ID= −1mA −0.8 −−2.8 V
drain-source leakage current VGS= 0; VDS= −60 V −−−200 nA
= −0.2 V; VDS= −200 V −−0.1 −60 µA
V
GS
gate leakage current VDS= 0; VGS= ±20 V −−±100 nA
drain-source on-state resistance VGS= −10 V; ID= −200 mA − 10 12 Ω
input capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 55 90 pF
output capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 20 30 pF
reverse transfer capacitance VGS= 0; VDS= −25 V; f = 1 MHz − 515pF
Switching times (see Figs 2 and 3)
t
on
turn-on time VGS=0to−10 V; VDD= −50 V;
− 510ns
ID= −250 mA
t
off
turn-off time VGS= −10 to 0 V; VDD= −50 V;
− 20 30 ns
ID= −250 mA
2002 May 22 3
Page 4
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
handbook, halfpage
0 V
−10 V
50 Ω
VDD = −50 V
I
D
MBB689
handbook, halfpage
INPUT
OUTPUT
10 %
t
on
90 %
90 %
BSS192
10 %
t
off
MBB690
1.2
handbook, halfpage
P
tot
(W)
0.8
0.4
0
0 200
Fig.2 Switching times test circuit.
MLC697
50 100 150
T
amb
(°C)
Fig.3 Input and output waveforms.
160
handbook, halfpage
C
(pF)
120
80
40
0
0
−5 −25
VGS= 0; Tj=25°C; f = 1 MHz.
(1) C
.
iss
(2) C
.
oss
(3) C
.
rss
MDA180
(1)
(2)
(3)
−10 −15 −20
VDS (V)
Fig.4 Power derating curve.
2002 May 22 4
Fig.5 Capacitance as a function of drain-source
voltage; typical values.
Page 5
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
−1
handbook, halfpage
I
D
(A)
−0.8
−0.6
−0.4
−0.2
0
0
Tj=25°C.
(1) VGS= −10 V.
(2) VGS= −6V.
−5 −10 −15 −20
(1)
(2)
(3)
(4)
(5)
VDS (V)
(3) VGS= −5V.
(4) VGS= −4V.
(5) VGS= −3V.
MDA177
−25
−1
handbook, halfpage
I
D
(A)
−0.8
−0.6
−0.4
−0.2
0
0 −10
VDS= −10 V; Tj=25°C.
−2 −4 −6 −8
BSS192
MDA178
VGS (V)
Fig.6 Output characteristics; typical values.
3
−10
handbook, halfpage
I
D
(mA)
2
−10
−10
Tj=25°C.
(1) VGS= −10 V.
(2) VGS= −5V.
(3) VGS= −4V.
(1)
12 16 20 24
R
DSon
MDA179
(2)
(3)
(Ω)
Fig.7 Transfer characteristic; typical values.
100
MDA182
Tj (oC)
1.2
handbook, halfpage
k
1.1
1
0.9
0.8
288
0.7
−50 0 50 150
V
at T
GSth
=
k
-------------------------------------V
GSth
V
at ID= −1 mA.
GSth
j
at 25°C
Fig.8 Drain current as a function of drain-source
on-state resistance; typical values.
2002 May 22 5
Fig.9 Temperature coefficient of gate-source
threshold voltage; typical values.
Page 6
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
2.5
handbook, halfpage
k
2
1.5
1
0.5
0
−50 0 50 150
R
at T
DSon
=
k
----------------------------------------R
DSon
ID= −200 mA; VGS= −10 V.
j
at 25 °C
100
Tj (oC)
BSS192
MDA181
Fig.10 Temperature coefficient of drain-source
on-state resistance; typical values.
2002 May 22 6
Page 7
Philips Semiconductors Product specification
P-channel enhancement mode
BSS192
vertical D-MOS transistor
PACKAGE OUTLINE
Plastic surface mounted package; collector pad for good heat transfer; 3 leads SOT89
D
b
3
B
A
123
w M
DIMENSIONS (mm are the original dimensions)
UNIT
mm
1.6
1.4
A
b
0.48
0.35
b
2
1
0.53
0.40
b
1.8
1.4
c
3
0.44
0.37
E
L
b
2
b
1
e
1
e
0 2 4 mm
scale
D
E
e
e
1
4.6
2.6
3.0
4.4
2.4
1.5
H
4.25
3.75
H
E
c
L
0.8
w
0.13
E
min.
OUTLINE
VERSION
SOT89 TO-243 SC-62
IEC JEDEC EIAJ
REFERENCES
2002 May 22 7
EUROPEAN
PROJECTION
ISSUE DATE
97-02-28
99-09-13
Page 8
Philips Semiconductors Product specification
P-channel enhancement mode
BSS192
vertical D-MOS transistor
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
Objective data Development This data sheet contains data from the objective specification for product
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Product data Production This data sheet contains data from the product specification. Philips
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
(1)
STATUS
(2)
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
DEFINITIONS
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
atthese or at anyotherconditions above those giveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationor warranty that such applicationswill be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expectedto result inpersonal injury. Philips
Semiconductorscustomersusing or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseof any of theseproducts,conveysno licence or title
under any patent, copyright, or mask work right to these
products,and makes no representationsor warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
2002 May 22 8
Page 9
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSS192
NOTES
2002 May 22 9
Page 10
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSS192
NOTES
2002 May 22 10
Page 11
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor
BSS192
NOTES
2002 May 22 11
Page 12
Philips Semiconductors – a w orldwide compan y
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
© Koninklijke Philips Electronics N.V. 2002
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 613510/03/pp12 Date of release: 2002 May 22 Document order number: 9397 750 09633
SCA74
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