Philips blf6g20-180pn Datasheet

BLF6G20-180PN

Power LDMOS transistor

Rev. 03 — 30 March 2009 Product data sheet

1. Product profile

1.1 General description

180 W LDMOS power transistor for base station applications at frequencies from
1800 MHz to 2000 MHz.

Table 1. Typical performance

RF performance at T

Mode of operation f V

2-carrier W-CDMA 1805 to 1880 32 50 18 29.5 −35

[1] Test signal: 3GPP; test model 1; 64 DPCH; PAR =7.5 dB at 0.01 % probability on CCDF per carrier;

case

carrier spacing 5 MHz.

= 25°C in a common source class-AB production test circuit.

DS

(MHz) (V) (W) (dB) (%) (dBc)

P

L(AV)

G

p

η

D

ACPR

[1]

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.

1.2 Features

n Typical 2-carrier W-CDMAperformance at frequencies of 1805 MHz and 1880 MHz, a

supply voltage of 32 V and an IDq of 1600 mA:

u Average output power = 50 W
u Power gain = 18 dB (typ)
u Efficiency = 29.5 %

u ACPR = −35 dBc
n Easy power control
n Integrated ESD protection
n Excellent ruggedness
n High efficiency
n Excellent thermal stability
n Designed for broadband operation (1800 MHz to 2000 MHz)
n Internally matched for ease of use
n Qualified up to a supply voltage of 32 V
n Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances

(RoHS)

NXP Semiconductors

1.3 Applications

n RF power amplifiers for W-CDMA base stations and multicarrier applications in the

1800 MHz to 2000 MHz frequency range

2. Pinning information

Table 2. Pinning

Pin Description Simplified outline Graphic symbol

1 drain1
2 drain2
3 gate1
4 gate2
5 source

[1] Connected to flange.

BLF6G20-180PN

Power LDMOS transistor

12

5

43

[1]

1

3
4

2

sym117

5

3. Ordering information

Table 3. Ordering information

Type number Package

BLF6G20-180PN - flanged balanced LDMOST ceramic package;

4. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

V
V
T
T
T

DS
GS
stg
case
j

drain-source voltage - 65 V
gate-source voltage −0.5 +13 V
storage temperature −65 +150 °C
case temperature - 150 °C
junction temperature - 225 °C

Name Description Version

SOT539A

2 mounting holes; 4 leads

BLF6G20-180PN_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 30 March 2009 2 of 11

NXP Semiconductors

5. Thermal characteristics

Table 5. Thermal characteristics

Symbol Parameter Conditions Typ Unit

R

th(j-case)

thermal resistance from junction to case T

6. Characteristics

Table 6. Characteristics

Tj = 25°C per section; unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

V

(BR)DSS

V

GS(th)

V

GSq

I

DSS

I

DSX

I

GSS

g

fs

R

DS(on)

drain-source breakdown
voltage

gate-source threshold voltage VDS=10V;ID= 144 mA 1.575 1.9 2.3 V
gate-source quiescent voltage VDS=32V;ID= 800 mA 1.725 2.1 2.45 V
drain leakage current VGS=0V

drain cut-off current VGS=V

gate leakage current VGS= 11 V; VDS= 0 V - - 300 nA
forward transconductance VDS=10V; ID= 7.2 A - 10 - S
drain-source on-state

resistance

BLF6G20-180PN

Power LDMOS transistor

=80°C; P

case

VGS=0V; ID= 0.5 mA 65 - - V

=28V - - 3 µA

V

DS

=60V - - 5 µA

V

DS

+ 3.75 V;

DS

=5A

D

GS(th)

=10V

GS(th)

+ 3.75 V;

V

VGS=V
I

= 50 W 0.45 K/W

L(AV)

-25-A

- 0.1 0.165 Ω

7. Application information

Table 7. Application information

Mode of operation: 2-carrier W-CDMA; PAR 7.5 dB at 0.01 % probability on CCDF; 3GPP test
model 1; 1 to 64 PDPCH; f
RF performance at V
class-AB production test circuit.

Symbol Parameter Conditions Min Typ Max Unit

G
RL

η

p

in

D

power gain P
input return loss P
drain efficiency P

ACPR adjacent channel power ratio P

Table 8. Application information

Mode of operation: 1-carrier W-CDMA; PAR 7.5 dB at 0.01 % probability on CCDF; 3GPP test
model 1; 1 to 64 PDPCH; f
I

= 1600 mA; T

Dq

case

Symbol Parameter Conditions Min Typ Max Unit

PAR

BLF6G20-180PN_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 30 March 2009 3 of 11

output peak-to-average ratio P

O

= 1802.5 MHz; f2 = 1807.5 MHz; f3 = 1872.5 MHz; f4 = 1877.5 MHz;

1

= 32 V; IDq = 1600 mA; T

DS

= 1872.5 MHz; f2 = 1877.5 MHz; RF performance at VDS = 32 V;

1

= 25°C; unless otherwise specified; in a

case

= 50 W 16.8 18 19.2 dB

L(AV)

= 50 W - −10 −6.5 dB

L(AV)

= 50 W 26 29.5 - %

L(AV)

= 50 W - −35 −33 dBc

L(AV)

= 25°C; unless otherwise specified; in a class-AB production test circuit.

L(AV)

= 115 W;

4.1 4.3 - dB

at 0.01 % probability on CCDF

NXP Semiconductors

7.1 Ruggedness in class-AB operation

The BLF6G20-180PN is capable of withstanding a load mismatch corresponding to
VSWR = 10 : 1 through all phases under the following conditions: VDS=28V;
IDq= 1600 mA; PL = 180 W (CW); f = 1880 MHz.

BLF6G20-180PN

Power LDMOS transistor

G

(dB)

001aai017

P

L(AV)

(W)

60

η

D

(%)

40

20

0

G

(dB)

p

20

18

16

14

0 20016080 12040

G

p

η

D

VDS=32V; IDq= 1600 mA; f = 1880 MHz.

Fig 1. One-tone CW power gain and drain efficiency as function of average load power;

typical values

22

p

20

G

p

18

η

D

001aai018

50

η

D

(%)

40

30

−10

IMD

(dBc)

−30

001aai019

IMD3

IMD5

IMD7

P

L(PEP)

(W)

(W)

20

−50

10

0

−70
0 300200100

VDS= 32 V; IDq= 1600 mA; f1= 1880 MHz;
f2= 1880.1 MHz.

Fig 3. Two-tone intermodulation distortion as a

function of peak envelope load power; typical
values

16

14

12

0 300200100

P

L(PEP)

VDS=32V; IDq= 1600 mA; f1= 1880 MHz;
f2= 1880.1 MHz.

Fig 2. Two-tone CW power gain and drain efficiency

as function of peak envelope load power;
typical values

BLF6G20-180PN_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 30 March 2009 4 of 11

NXP Semiconductors

BLF6G20-180PN

Power LDMOS transistor

22

G

p

(dB)

20

18

16

14

0604020

G

p

η

D

001aai020

PL (W)

VDS=32V; IDq= 1600 mA; f1= 1872.5 MHz;
f2= 1877.5 MHz; carrier spacing 5 MHz.

Fig 4. 2-carrier W-CDMA power gain and drain

efficiency as function of load power; typical
values

001aai022

G

(dB)

22

p

20

40

η

D

(%)

30

20

10

0

−20

ACPR

(dBc)

−30

−40

−50

−60

0604020

001aai021

PL (W)

VDS= 32 V; IDq= 1600 mA; f1= 1872.5 MHz;
f2= 1877.5 MHz; carrier spacing 5 MHz.

Fig 5. 2-carrier W-CDMA adjacent channel power

ratio as a function of load power; typical
values

40

η

D

(%)

30

−20

ACPR,

IMD3
(dBc)

−30

001aai023

G

p

18

16

14

0604020

η

D

PL (W)

20

10

0

VDS=32V; IDq= 1600 mA; f1= 1867.5 MHz;
f2= 1877.5 MHz; carrier spacing 10 MHz.

Fig 6. 2-carrier W-CDMA power gain and drain

efficiency as function of load power; typical
values

BLF6G20-180PN_3 © NXP B.V. 2009. All rights reserved.

−40

−50

−60

0604020

VDS= 32 V; IDq= 1600 mA; f1= 1867.5 MHz;
f2= 1877.5 MHz; carrier spacing 10 MHz.

Fig 7. 2-carrier W-CDMA adjacent channel power

ratio and third order intermodulationdistortion
as function of load power; typical values

IMD3

ACPR

PL (W)

Product data sheet Rev. 03 — 30 March 2009 5 of 11

NXP Semiconductors

8. Test information

BLF6G20-180PN

Power LDMOS transistor

C3 C9 C13 C5 C14

R3

input
50 Ω

C1

R1

R2

See Table9 for list of components.

Fig 8. Test circuit for operation at 1805 MHz and 1880 MHz

C11

output

C6

C12

C4

C10C2 C8

50 Ω

C7

001aai024

BLF6G20-180PN_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 30 March 2009 6 of 11

NXP Semiconductors

BLF6G20-180PN

Power LDMOS transistor

C14

C5

C13

R3

C3 C9

C1

INPUT

C8

C2

R1

R1

R2

TB

Striplines are on a double copper-clad Rogers R04350 Printed-Circuit Board (PCB) with εr = 3.5 and thickness = 0.76 mm.
See Table9 for list of components.

Fig 9. Component layout for 1805 MHz and 1880 MHz test circuit

C11

C10 C12 C4

C6

C7

TB

OUTPUT

R1

001aai025

Table 9. List of components

For test circuit, see Figure 8 and Figure 9.

Component Description Value Remarks

C1 ATC multilayer ceramic chip capacitor 6.2 pF
C2, C3 ATC multilayer ceramic chip capacitor 16 pF
C4, C5, C6 ATC multilayer ceramic chip capacitor 18 pF
C7 ATC multilayer ceramic chip capacitor 1.1 pF

[1]
[1]
[2]
[3]

C8, C9, C10, C11 TDK multilayer ceramic chip capacitor 4.7 µF
C12, C13 AVX multilayer ceramic chip capacitor 220 nF
C14 electrolytic capacitor 100 µF; 63 V

[2]

R1 chip resistor 33 Ω
R2, R3 chip resistor 8.2 Ω

[1] American Technical Ceramics type 100B or capacitor of same quality.
[2] American Technical Ceramics type 180R or capacitor of same quality.
[3] American Technical Ceramics type 100A or capacitor of same quality.

BLF6G20-180PN_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 30 March 2009 7 of 11

NXP Semiconductors

BLF6G20-180PN

Power LDMOS transistor

9. Package outline

Flanged balanced LDMOST ceramic package; 2 mounting holes; 4 leads SOT539A

D

A

D

1

U

1

q

H

1

w

M M

2

F

B

C

C

c

12

H

U

2

L

A

e

43

b

0 5 10 mm

scale

p

5

w

M

3

w

M M M

1

AB

E

1

Q

E

DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)

UNIT

mm

inches

A

5.33

3.96

0.210

0.156

OUTLINE
VERSION

SOT539A

11.81

11.56

0.465

0.455

c

0.15

0.08

0.006

0.003

D

Db

31.55

30.94

1.242

1.218

IEC JEDEC EIAJ

e U

13.72

0.540

EE

9.53

9.50

9.27

9.30

0.374

0.375

0.366

0.365

REFERENCES

1

31.52

30.96

1.241

1.219

1

F

1.75

1.50

0.069

0.059

H

17.12

16.10

0.674

0.634

H

1

25.53

25.27

1.005

0.995

L

3.73

2.72

0.147

0.107

p

3.30

3.05

0.130

0.120

qw

Q

2.31

2.01

0.091

0.079

U

41.28

35.56

41.02

1.625

1.615

EUROPEAN

PROJECTION

1

2

10.29

10.03

0.405

0.395

w

1

ISSUE DATE

99-12-28
00-03-03

2

0.250.25 0.51

0.0100.010 0.0201.400

w

3

Fig 10. Package outline SOT539A

BLF6G20-180PN_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 30 March 2009 8 of 11

NXP Semiconductors

10. Abbreviations

Table 10. Abbreviations

Acronym Description

3GPP 3rd Generation Partnership Project
CCDF Complementary Cumulative Distribution Function
CW Continuous Wave
DPCH Dedicated Physical CHannel
IMD InterModulation Distortion
LDMOS Laterally Diffused Metal-Oxide Semiconductor
LDMOST Laterally Diffused Metal-Oxide Semiconductor Transistor
PAR Peak-to-Average power Ratio
PDPCH transmission Power of the Dedicated Physical CHannel
RF Radio Frequency
VSWR Voltage Standing-Wave Ratio
W-CDMA Wideband Code Division Multiple Access

BLF6G20-180PN

Power LDMOS transistor

11. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

BLF6G20-180PN_3 20090330 Product data sheet - BLF6G20-180PN_2
BLF6G20-180PN_2 20090121 Preliminary data sheet - BLF6G20-180PN_1
Modifications:

BLF6G20-180PN_1 20080428 Objective data sheet - -

• Table 7 on page 3: Maximum adjacent channel power ratio changed

• Table 8 on page 3: Minimum output peak-to-average ratio changed

BLF6G20-180PN_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 30 March 2009 9 of 11

NXP Semiconductors

12. Legal information

12.1 Data sheet status

BLF6G20-180PN

Power LDMOS transistor

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document mayhave changed since this document was published and maydiffer in case of multiple devices. The latest product status

information is available on the Internet at URL

[1][2]

Product status

12.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall haveno liability for the consequences of
use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title.A short data sheet is intended
for quick referenceonly and should not be relied upon to containdetailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.

12.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or
warranties, expressedor implied,as tothe accuracyor completeness ofsuch
information and shall have no liability for the consequences of use of such
information.

Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informationsupplied prior
to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental

[3]

http://www.nxp.com.

Definition

damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134)may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at

http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyanceor implication of any license under any copyrights, patents
or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.

12.4 Trademarks

Notice: All referencedbrands, product names, service names and trademarks
are the property of their respective owners.

13. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

BLF6G20-180PN_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 30 March 2009 10 of 11

NXP Semiconductors

14. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 3

6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Application information. . . . . . . . . . . . . . . . . . . 3

7.1 Ruggedness in class-AB operation. . . . . . . . . . 4

8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 6

9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8

10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 9

11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 9

12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10

12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10

12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

12.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

13 Contact information. . . . . . . . . . . . . . . . . . . . . 10

14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

BLF6G20-180PN

Power LDMOS transistor

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2009. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

Date of release: 30 March 2009

Document identifier: BLF6G20-180PN_3