Philips blf4g10-160 Datasheet

Page 1
BLF4G10-160
UHF power LDMOS transistor
Rev. 01 — 22 June 2007 Product data sheet
1. Product profile

1.1 General description

160 W LDMOS power transistor for base station applications at frequencies from 800 MHz to 1000 MHz.
Table 1. Typical performance
RF performance at T
Mode of operation f VDSPLP
CW 894 28 200 - 19.0 59 - - - - - ­2-tone 894 28 - 80 19.7 42.5 - - - - - −29 GSM EDGE 894 28 - 80 19.7 41.5 −61 CDMA 881.5 28 - 40 19.0 29.5 - - −45
= 25°C in a common source class-AB test circuit.
case
L(AV)GpηD
(MHz) (V) (W) (W) (dB) (%) (dBc) (dBc) (dBc) (dBc) (%) (dBc)
ACPR
ACPR
400
[1]
−72
ACPR
600
[1]
- - 3.0 -
ACPR
750
[2]
−64
[2]
EVM
1980
rms
--
IMD3
[1] ACPR [2] Test signal: IS-95, with PAR =9.9 dB at 0.01 % probability.
CAUTION
and ACPR
400
at 30 kHz resolution bandwidth.
600
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken during transport and handling.

1.2 Features

n Typical GSM EDGE performance at f = 894 MHz, VDS = 28 V and IDq = 900 mA:
u Average output power = 80 W u Gain = 19.7 dB u Efficiency = 41.5 % u ACPR u ACPR
u EVM n Easy power control n Excellent ruggedness n High efficiency n Excellent thermal stability n Designed for broadband operation (800 MHz to 1000 MHz) n Internally matched for ease of use
400 600
= 3.0 %
rms
= −61 dBc = −72 dBc
Page 2
NXP Semiconductors

1.3 Applications

n RF power amplifiers for GSM, GSM EDGE and CDMA base stations and multi carrier
applications in the 800 MHz to 1000 MHz frequency range.

2. Pinning information

Table 2. Pinning
Pin Description Simplified outline Symbol
1 drain 2 gate 3 source
[1] Connected to flange

3. Ordering information

BLF4G10-160
UHF power LDMOS transistor
1
[1]
2
3
2
sym112
1
3
Table 3. Ordering information
Type number Package
BLF4G10-160 - flanged LDMOST ceramic package; 2 mounting holes; 2

4. Limiting values

Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
V
GS
I
D
T
stg
T
j
drain-source voltage - 65 V gate-source voltage −0.5 +15 V drain current - 15 A storage temperature −65 +150 °C junction temperature - 200 °C

5. Thermal characteristics

Table 5. Thermal characteristics
Symbol Parameter Conditions Typ Max Unit
R
th(j-case)
thermal resistance from junction to case
Name Description Version
SOT502A
leads
T P
case L
=80°C;
=50W
0.55 0.64 K/W
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 2 of 14
Page 3
NXP Semiconductors

6. Characteristics

Table 6. Characteristics
Tj = 25°C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
(BR)DSS
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
C
rs
BLF4G10-160
UHF power LDMOS transistor
drain-source breakdown voltage
gate-source threshold voltage VDS= 10 V; ID= 230 mA 2.5 2.9 3.5 V gate-source quiescent voltage VDS= 28 V; ID= 900 mA 2.65 3.15 3.65 V drain leakage current VGS=0V; VDS=28V - - 5 µA drain cut-off current VGS=V
gate leakage current VGS= 15 V; VDS= 0 V - - 420 nA forward transconductance VDS=10V; ID= 7.5 A - 11 - S drain-source on-state
resistance feedback capacitance VGS=0V; VDS=28V;
VGS=0V; ID= 2.1 mA 65 - - V
V
=10V
DS
VGS=V I
= 7.5 A
D
GS(th)
GS(th)
+6 V;
+ 6 V;
35 42 - A
- 0.065 - Ω
- 3.0 - pF
f=1MHz

7. Application information

Table 7. Application information
Mode of operation: 2-tone; f1= 894 MHz; f2= 894.2 MHz; RF performance at VDS=28V; I
= 900 mA; T
Dq
Symbol Parameter Conditions Min Typ Max Unit
G
p
RL
in
η
D
IMD3 third order intermodulation distortion P IMD5 fifth order intermodulation distortion P IMD7 seventh order intermodulation distortion P

7.1 Ruggedness in class-AB operation

The BLF4G10-160 is capable of withstanding a load mismatch corresponding to VSWR = 10 : 1 through all phases under the following conditions: VDS=28V; IDq= 900 mA; PL = 160 W (CW); f = 894 MHz.
case
power gain P input return loss P drain efficiency P
=25°C; unless otherwise specified; in a class-AB test circuit.
= 160 W 18.5 19.7 - dB
L(PEP)
= 160 W - −10 −6dB
L(PEP)
= 160 W 40 42.5 - %
L(PEP)
= 160 W - −29 −26 dBc
L(PEP)
= 160 W - −38 −35 dBc
L(PEP)
= 160 W - −57 −53 dBc
L(PEP)
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 3 of 14
Page 4
NXP Semiconductors
BLF4G10-160
UHF power LDMOS transistor
PL (W)
=25°C;
001aag546
60
η
D
(%)
40
20
0
21
G
p
(dB)
19
17
15
0 24016080
G
p
η
D
VDS= 28 V; IDq= 900 mA; T
case
f = 894 MHz.
Fig 1. One-tone CW power gain and drain efficiency
as functions of load power; typical values
0
IMD
(dBc)
−20
001aag548
IMD3
P
L(AV)
=25°C;
001aag547
(W)
60
η
(%)
40
20
0
22
G
p
(dB)
G
20
18
16
0 1208040
p
η
D
VDS=28V; IDq= 900 mA; T
case
f = 894 MHz.
Fig 2. Two-tone power gain and drain efficiency as
functions of average load power; typical values
0
IMD3 (dBc)
−20
001aag549
D
P
L(AV)
IMD5
IMD7
(W)
−40
−60
−80
0 1208040
VDS= 28 V; IDq= 900 mA; T
case
=25°C;
f = 894 MHz.
Fig 3. Intermodulation distortion a function of
average load power; typical values
−40
−60
−80
0 1208040
VDS=28V; T
1 2
3 4
=25°C; f = 894 MHz.
case
P
L(AV)
(W)
(1) IDq = 800 mA. (2) IDq = 900 mA. (3) IDq = 1000 mA. (4) IDq = 1100 mA.
Fig 4. IMD3 as a function of average load power;
typical values
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 4 of 14
Page 5
NXP Semiconductors
BLF4G10-160
UHF power LDMOS transistor
21
G
p
(dB)
20
19
18
17
16
G
p
η
D
0 1008040 6020
VDS= 28 V; IDq= 900 mA; T
case
P
=25°C;
001aag550
L(AV)
(W)
50
η
D
(%)
40
30
20
10
0
f = 894 MHz.
Fig 5. GSM EDGE power gain and drain efficiency as
functions of average load power; typical values
16
EVM
(%)
12
001aag552
P
=25°C;
001aag551
(W)
L(AV)
−50
ACPR
(dBc)
−60
−70
−80
0 1008040 6020
VDS=28V; IDq= 900 mA; T
ACPR
ACPR
400
600
case
f = 894 MHz.
Fig 6. GSM EDGE ACPR at 400 kHz and at 600 kHz as
a function of average load power; typical values
−56
ACPR
(dBc)
−60 ACPR
400
001aag553
4
EVM
(%)
3
8
4
0
0 1008040 6020
VDS= 28 V; IDq= 900 mA; T
EVM
EVM
case
M
rms
=25°C;
P
L(AV)
(W)
f = 894 MHz.
Fig 7. GSM EDGE rms EVM and peak EVM as
functions of average load power; typical values
−64
−68
−72
0604020
EVM
rms
VDS=28V; IDq= 900 mA; T
case
ηD (%)
=25°C;
2
1
0
f = 894 MHz.
Fig 8. GSM EDGE ACPR and rms EVM as functions of
drain efficiency; typical values
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 5 of 14
Page 6
NXP Semiconductors
BLF4G10-160
UHF power LDMOS transistor
001aag554
P
L(AV)
(dBm)
G
(dB)
20
p
19
18
17
16
28 484436 4032
G
p
η
D
VDS= 28 V; IDq= 1100 mA; f = 881.5 MHz. Test signal: IS-95 with PAR = 9.9 dB at 0.01 % probability.
Fig 9. CDMA power gain and drain efficiency as
functions of average loadpower; typical values, measured in a CDMA demo test circuit
40
η
D
(%)
30
20
10
0
G
(dB)
20
p
19
18
17
16
28 484436 4032
1
2 3
001aag555
P
L(AV)
(dBm)
VDS=28V; IDq= 1100 mA. (1) f = 869 MHz. (2) f = 881.5 MHz. (3) f = 894 MHz.
Fig 10. CDMA power gain as a function of average load
power at various frequencies; typical values,
measured in a CDMA demo test circuit
001aag556
P
L(AV)
(dBm)
VDS= 28 V; IDq= 1100 mA; T
−35
ACPR
(dBc)
−45
−55
−65
−75
28 484436 4032
=25°C; f = 881.5 MHz.
case
ACPR
ACPR
750
1980
Fig 11. CDMA ACPR at 750 kHz and at 1980 kHz as functions of average load power;typical values, measured in a
CDMA demo test circuit
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 6 of 14
Page 7
NXP Semiconductors

8. Test information

V
bias
BLF4G10-160
UHF power LDMOS transistor
V
DD
C6
R1
C5
L6L5
C10
C9C8C7
L3
RF in RF out
C1
L2L1
C2
L4
See Table8 for a list of components
Fig 12. Circuit schematic for 894 MHz production test circuit
+V
bias
L5
L1 L2
C1
C6
R1
C5
L3 L4 L7 L8
C2
L7
L6
L8
C7 C8 C9
C4
L9
C3
V
DD
C3
L10
001aag557
C10
L10
L9
C4
BLF4G10-160
Input-Rev1
BLF4G10-160
Output-Rev1
001aag558
The striplines are on a double copper-clad Rogers 6006 Printed-Circuit Board (PCB) with εr= 6.15 and thickness = 0.635 mm.
See Table8 for a list of components.
Fig 13. Component layout for 894 MHz production test circuit
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 7 of 14
Page 8
NXP Semiconductors
Table 8. List of components (see Figure 12 and Figure 13).
Component Description Value Remarks
C1, C4, C6, C7 multilayer ceramic chip
C2 multilayer ceramic chip
C3 multilayer ceramic chip
C5, C9 tantalum capacitor 10 µF C8 ceramic capacitor 1 µF 1812X7R105KL2AB C10 electrolytic capacitor 220 µF L1 stripline ­L2 stripline ­L3 tapered stripline -
L4 stripline ­L5 stripline ­L6 stripline ­L7 stripline ­L8 tapered stripline -
L9 stripline ­L10 stripline ­R1 SMD resistor 5.1 Ω
capacitor
capacitor
capacitor
68 pF
1.5 pF
1.4 pF
BLF4G10-160
UHF power LDMOS transistor
[1]
[1]
[1]
[2]
(W × L) 0.914 mm × 10.160 mm
[2]
(W × L) 0.914 mm × 24.384 mm
[2]
(W1 × W2 × L)
0.914 mm × 19.812 mm × 11.024 mm
[2]
(W × L) 19.812 mm × 21.438 mm
[2]
(W × L) 0.914 mm × 42.342 mm
[2]
(W × L) 1.524 mm × 42.418 mm
[2]
(W × L) 17.221 mm × 22.479 mm
[2]
(W1 × W2 × L)
17.221 mm × 0.914 mm × 20.625 mm
[2]
(W × L) 0.914 mm × 19.126 mm
[2]
(W × L) 0.914 mm × 6.858 mm
[1] American Technical Ceramics type 100B or capacitor of same quality. [2] The striplines are on a double copper-clad Rogers 6006 Printed-Circuit Board (PCB) with εr= 6.15 and
thickness = 0.635 mm.
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 8 of 14
Page 9
NXP Semiconductors
V
(12 V - 28 V)
bias
Fig 14. Circuit schematic for 869 MHz to 894 MHz CDMA demo test circuit
Q1
C3
C4
R6
R9R10 R7
Q2
RF in RF out
R2
R1
C1
R3
R4
R5
R8
C5
L2L1
C6
L6L5
C7
L3
L4
Q3
C2
See Table9 for a list of components
BLF4G10-160
UHF power LDMOS transistor
VDD(28 V)
C11
C10C9C8
L7
L8
C12
L9
L10
001aag559
(12 V - 28 V)
bias
R9 Q2
R10
C6
L5
C7
L3 L4 L7 L8
C2
Q3
BLF4G10-160
CDMA in
L6
BLF4G10-160
CDMA out
R1
R2
R3
L1 L2
C1
Q1
C3
C4
R6
R5
R7
R4
R8
C5
The other side is unetched and serves as a ground plane. See Table9 for a list of components.
Fig 15. Component layout for 869 MHz to 894 MHz CDMA demo test circuit
VDD(28 V)V
C8 C9 C10
C11
L10
L9
C12
001aag560
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 9 of 14
Page 10
NXP Semiconductors
Table 9. List of components (see Figure 14 and Figure 15).
Component Description Value Remarks
C1, C6, C8 multilayer ceramic chip
C2, C7 multilayer ceramic chip
C3, C4 ceramic capacitor 100 nF C5, C10 tantalum capacitor 10 µF C9 ceramic capacitor 1 µF C11 electrolytic capacitor 2200 µF C12 multilayer ceramic chip
L1 stripline ­L2 stripline ­L3 tapered stripline -
L4 stripline ­L5 stripline ­L6 stripline ­L7 stripline ­L8 tapered stripline -
L9 stripline ­L10 stripline ­R1, R2 SMD resistor 430 Ω R3 SMD resistor 300 Ω R4 potentiometer 200 Ω R5 SMD resistor 2 kΩ R6 SMD resistor 1.1 kΩ R7 SMD resistor 11 kΩ R8 SMD resistor 5.1 Ω R9 SMD resistor 5.1 kΩ R10 SMD resistor 910 Ω Q1 voltage regulator - 78L08 Q2 transistor - 2N2222 Q3 BLF4G10-160 -
capacitor
capacitor
capacitor
68 pF
1.3 pF
18 pF
BLF4G10-160
UHF power LDMOS transistor
[1]
[1]
[1]
[2]
(W × L) 0.914 mm × 10.160 mm
[2]
(W × L) 0.914 mm × 24.384 mm
[2]
(W1 × W2 × L)
0.914 mm × 19.812 mm × 11.024 mm
[2]
(W × L) 19.812 mm × 21.438 mm
[2]
(W × L) 0.914 mm × 42.342 mm
[2]
(W × L) 1.524 mm × 42.418 mm
[2]
(W × L) 17.221 mm × 22.479 mm
[2]
(W1 × W2 × L)
17.221 mm × 0.914 mm × 20.625 mm
[2]
(W × L) 0.914 mm × 19.126 mm
[2]
(W × L) 0.914 mm × 6.858 mm
[1] American Technical Ceramics type 100B or capacitor of same quality. [2] The striplines are on a double copper-clad Rogers 6006 Printed-Circuit Board (PCB) with εr= 6.15 and
thickness = 0.635 mm.
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 10 of 14
Page 11
NXP Semiconductors
BLF4G10-160
UHF power LDMOS transistor

9. Package outline

Flanged LDMOST ceramic package; 2 mounting holes; 2 leads SOT502A
D
A
3
D
1
U
1
q
1
H
U
2
A
2
b
w
M M
C
2
0 5 10 mm
scale
F
B
C
L
p
w
M M M
AB
1
c
E
1
Q
E
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT
mm
inches
A
4.72
3.43
0.186
0.135
OUTLINE VERSION
SOT502A
12.83
12.57
0.505
0.495
c
0.15
0.08
0.006
0.003
IEC JEDEC JEITA
Db
20.02
19.61
0.788
0.772
D
19.96
19.66
0.786
0.774
1
0.374
0.366
EE
1
9.53
9.50
9.25
9.30
0.375
0.364
REFERENCES
F
1.14
0.89
0.045
0.035
H
19.94
18.92
0.785
0.745
L
5.33
4.32
0.210
0.170
p
3.38
3.12
0.133
0.123
qw
Q
1.70
1.45
0.067
0.057
PROJECTION
U
U
1
9.91
34.16
9.65
33.91
0.390
1.345
0.380
1.335
EUROPEAN
w
2
0.25 0.5127.94
0.01 0.021.100
2
1
ISSUE DATE
99-12-28 03-01-10
Fig 16. Package outline SOT502A
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 11 of 14
Page 12
NXP Semiconductors

10. Abbreviations

Table 10. Abbreviations
Acronym Description
CDMA Code Division Multiple Access CW Continuous Waveform EDGE Enhanced Data GSM Environment EVM Error Vector Magnitude GSM Global System for Mobile communications IS-95 CDMA Interim Standard 95 LDMOS Laterally Diffused Metal Oxide Semiconductor LDMOST Laterally Diffused Metal-Oxide Semiconductor Transistor PAR Peak-to-Average power Ratio RF Radio Frequency RMS Root Mean Square SMD Surface-Mount Device VSWR Voltage Standing-Wave Ratio
BLF4G10-160
UHF power LDMOS transistor

11. Revision history

Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
BLF4G10-160_1 20070622 Product data sheet - -
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 12 of 14
Page 13
NXP Semiconductors

12. Legal information

12.1 Data sheet status

BLF4G10-160
UHF power LDMOS transistor
Document status
Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document mayhave changed since this document was published and may differ in case of multiple devices.The latest product status
information is available on the Internet at URL
[1][2]
Product status
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall haveno liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title.Ashort data sheet is intended for quick referenceonly and should not be relied upon to containdetailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

12.3 Disclaimers

General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or warranties, expressedor implied,as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all informationsupplied prior to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
[3]
http://www.nxp.com.
Definition
malfunction of a NXP Semiconductorsproductcanreasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134)maycause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyanceor implicationof any license under any copyrights, patents or other industrial or intellectual property rights.

12.4 Trademarks

Notice: All referencedbrands, product names, service names and trademarks are the property of their respective owners.

13. Contact information

For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected]
BLF4G10-160_1 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 01 — 22 June 2007 13 of 14
Page 14
NXP Semiconductors

14. Contents

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 2
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Application information. . . . . . . . . . . . . . . . . . . 3
7.1 Ruggedness in class-AB operation. . . . . . . . . . 3
8 Test information. . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
13 Contact information. . . . . . . . . . . . . . . . . . . . . 13
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
BLF4G10-160
UHF power LDMOS transistor
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected]
Date of release: 22 June 2007
Document identifier: BLF4G10-160_1
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