Philips bf998wr Datasheet

DATA SH EET

DISCRETE SEMICONDUCTORS

BF998WR

N-channel dual-gate MOS-FET

Product specification
Supersedes data of 1995 Apr 25

1997 Sep 05

NXP Semiconductors Product specification

Fig.1 Simplified outline (SOT343R) and symbol.

Marking code: MB.

MAM198

Top view

21

34

s,b

d

g

1

g

2

N-channel dual-gate MOS-FET BF998WR

FEATURES

 High forward transfer admittance
 Short channel transistor with high forward transfer

admittance to input capacitance ratio

 Low noise gain controlled amplifier up to 1 GHz.

APPLICATIONS

 VHF and UHF applications with 12 V supply voltage,

such as television tuners and professional
communications equipment.

DESCRIPTION

Depletion type field-effect transistor in a plastic
microminiature SOT343R package with source and
substrate interconnected. The transistor is protected
against excessive input voltage surges by integrated
back-to-back diodes between gates and source.

CAUTION

The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handlin g.

PINNING

PIN SYMBOL DESCRIPTION

1s, bsource
2 d drain
3g
4g

gate 2

2

gate 1

1

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DS

I

D

P

tot

T

j

 forward transfer admittance  24  mS

y

fs

C

ig1-s

C

rs

drain-source voltage 12 V
drain current 30 mA
total power dissipation 300 mW
operating junction temperature 150 C

input capacitance at gate 1  2.1  pF
reverse transfer capacitance f = 1 MHz  25  fF

F noise figure f = 800 MHz  1  dB

1997 Sep 05 2

NXP Semiconductors Product specification

Fig.2 Power derating curve.

handbook, halfpage

0 50 100 200

0

MLD154

150

400

200

300

100

P

tot

(mW)

T ( C)

amb

o

N-channel dual-gate MOS-FET BF998WR

LIMITING VALUES

In accordance with the Absolu te Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

Note

1. Device mounted on a printed-circuit board.

drain-source voltage  12 V
drain current  30 mA
gate 1 current 10 mA
gate 2 current 10 mA
total power dissipation up to T

=45C; see Fig.2; note 1  300 mW

amb

storage temperature 65 +150 C
operating junction temperature  +150 C

1997 Sep 05 3

NXP Semiconductors Product specification

N-channel dual-gate MOS-FET BF998WR

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

R

th j-s

Notes

1. Device mounted on a printed-circuit board.

2. T

is the temperature at the soldering point of the source lead.

s

STATIC CHARACTERISTICS

=25C; unless otherwise specified.

T

j

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

(BR)G1-SS

V

(BR)G2-SS

V

(P)G1-S

V

(P)G2-S

I

DSS

I

G1-SS

I

G2-SS

thermal resistance from junction to ambient note 1 350 K/W
thermal resistance from junction to soldering point note 2; Ts=90C200K/W

gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
gate 1-source cut-off voltage V
gate 2-source cut-off voltage V
drain-source current V
gate 1 cut-off current V
gate 2 cut-off current V

G2-S=VDS
G1-S=VDS
G2-S
G1-S
G2-S
G2-S=VDS
G1-S=VDS

=0; I
=0; I

=10mA 6 20 V

G1-S

=10mA 6 20 V

G2-S

=4V; VDS=8V; ID=20A 2.5 V
=0; VDS=8V; ID=20A 2V
=4V; VDS=8V; V

=0; V

G1-S

=0; V

G2-S

=0 2 18 mA

G1-S

=5V  50 nA
=5V  50 nA

DYNAMIC CHARACTERISTICS

Common source; T

=25C; V

amb

=4V; ID=10mA; VDS= 8 V; unless otherwise specified.

G2-S

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

 forward transfer admittance pulsed; Tj=25C2225 mS

y

fs

C

ig1-s

C

ig2-s

C

os

C

rs

F noise figure f = 200 MHz; G

input capacitance at gate 1 f = 1 MHz  2.1 2.5 pF
input capacitance at gate 2 f = 1 MHz  1.2  pF
drain-source capacitance f = 1 MHz  1.05  pF
reverse transfer capacitance f = 1 MHz  25  fF

f=800MHz; G

=2mS; BS=B

S

= 3.3 mS; BS=B

S

 0.6  dB

Sopt

 1  dB

Sopt

1997 Sep 05 4

NXP Semiconductors Product specification

Fig.3 Transfer characteristics; typical values.

VDS=8V.
T

amb

=25C.

0

24

16

8

0

11

MGC471

I

D

(mA)

V (V)

G1 S

V = 4 V

3 V

2 V

1 V

0 V

G2 S

Fig.4 Output characteristics; typical values.

V

G2-S

=4V.

T

amb

=25C.

0

24

16

8

0

210

MGC470

468

I

D

(mA)

V (V)

DS

0.4 V

0.3 V

0.2 V

0.1 V

−0.1 V

0 V

V =

G1 S

−0.2 V

−0.3 V

−0.4 V

−0.5 V

VDS=8V; VG2=4V; T

amb

=25C.

Fig.5 Drain current as a function of gate 1 voltage;

typical values.

−1600 400

24

0

8

16

MGC472

−1200 −800 −400 0

max typ

min

I

D

(mS)

V (mV)

G1

Fig.6 Forward transfer admittance as a function

of drain current; typical values.

VDS=8V; T

amb

=25C.

020

30

0

6

MGC473

12

18

24

4 8 12 16

y

fs

(mS)

I (mA)

D

V = 0 V

G2 − S

0.5 V

4 V

3 V
2 V
1 V

N-channel dual-gate MOS-FET BF998WR

1997 Sep 05 5

NXP Semiconductors Product specification

Fig.7 Forward transfer admittance as a function

of gate 1 voltage; typical values.

VDS=8V; T

amb

=25C.

−11

30

0

6

MGC474

12

18

24

0

V (V)

G1-S

y

fs

(mS)

3 V

2 V

1 V

0 V

V = 4 V

G2 S

Fig.8 Output capacitance as a function of

drain-source voltage; typical values.

V

G2-S

= 4 V; f = 1 MHz; T

amb

=25C.

414

1.5

1.0

1.1

MGC475

1.2

1.3

1.4

6 8 10 12

VDS(V)

C

os

(pF)

12 mA
10 mA

8 mA

I

D =

Fig.9 Gate 1 input capacitance as a function of

gate 1-source voltage; typical values.

VDS=8V; V

G2-S

=4V; f=1MHz; T

amb

=25C.

−2.4 −1.6 −0.8 0.8

2.4

1.4

2.2

MGC476

0

2.0

1.8

1.6

C

is

(pF)

V (mV)

G1-S

Fig.10 Gate 1 input capacitance as a function of

gate 2-source voltage; typical values.

VDS=8V; V

G1-S

=0V; f=1MHz; T

amb

=25C.

642 −2

2.4

2.3

2.1

2.0

2.2

MGC477

0

C

is

(pF)

V (V)

G2-S

N-channel dual-gate MOS-FET BF998WR

1997 Sep 05 6

NXP Semiconductors Product specification

Fig.11 Input admittance as a function of the

frequency; typical values.

VDS=8V; V

G2-S

=4V.

ID=10mA; T

amb

=25C.

10

3

MGC466

10

2

10

10

2

1

10

10

1

y

is

(mS)

f (MHz)

b

is

g

is

VDS=8V; V

G2-S

=4V.

ID=10mA; T

amb

=25C.

Fig.12 Reverse transfer admittance and phase as

a function of frequency; typical values.

10

3

MGC467

10

2

10

10

3

10

2

10

1

y

rs

10

3

10

10

1

2

(μS)

f (MHz)

rs

y

rs

(deg)

rs

ϕ

ϕ

Fig.13 Forward transfer admittance and phase as

a function of frequency; typical values.

VDS=8V; V

G2-S

=4V.

ID=10mA; T

amb

=25C.

10

3

MGC468

10

2

10

1

10

2

10

1

10

10

2

y

fs

(mS)

y

fs

f (MHz)

(deg)

fs

fs

ϕ

ϕ

Fig.14 Output admittance as a function of the

frequency; typical values.

VDS=8V; V

G2-S

=4V.

ID=10mA; T

amb

=25C.

10

3

MGC469

10

2

10

10

1

10

1

10

2

y

os

(mS)

f (MHz)

b

os

g

os

N-channel dual-gate MOS-FET BF998WR

1997 Sep 05 7

NXP Semiconductors Product specification

Fig.15 Gain control testcircuit at f = 200 MHz.

VDD=12V; GS=2mS; GL= 0.5 mS.
L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust G

L

= 0.5 mS. C1 adjusted for GS=2mS.

V

AGC

1 nF1 nF

50 Ω
input

50 Ω
input

1 nF

1 nF

L1

L2

20 μH

47 μF

1 nF

1 nF

1 nF

1 nF

47
kΩ

1.8
kΩ

360

Ω

140 kΩ

1 nF

V

DD

V

DD

15 pF 10 pF

100
kΩ

330
kΩ

V

tun

D1
BB405

C1

5.5 pF

330
kΩ

D2
BB405

input

V

tun

output

MGC481

N-channel dual-gate MOS-FET BF998WR

1997 Sep 05 8

NXP Semiconductors Product specification

VDD=12V; GS= 3.3 mS; GL=1mS.
L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4mm above ground plane.

Fig.16 Gain control test circuit at f = 800 MHz.

V

AGC

1 nF

1 nF

1 nF

50 Ω
input

50 Ω
input

1 nF

270
kΩ

360

Ω

1.8
kΩ

140

kΩ

100 kΩ

V

DD

V

DD

1 nF

MGC480

V

DD

1 nF

1 nF

L1

L2

C1
2-18 pF

C2

0.5-3.5 pF

C3

0.5-3.5 pF

L3

L4

C4
4-40 pF

Fig.17 Automatic gain control characteristics

measured in circuit of Fig.15.

VDD= 12 V; f = 200 MHz; T

amb

=25C.

010

0

−50

−40

MGC479

−30

−20

−10

2468

I

DSS

=

max
typ
min

ΔG

tr

(dB)

V

AGC

(V)

VDD= 12 V; f = 800 MHz; T

amb

=25C.

Fig.18 Automatic gain control characteristics

measured in circuit of Fig.16.

010

0

−50

−40

MGC478

−30

−20

−10

2468

I

DSS

=

max
typ
min

ΔG

tr

(dB)

V

AGC

(V)

N-channel dual-gate MOS-FET BF998WR

1997 Sep 05 9

NXP Semiconductors Product specification

REFERENCES

OUTLINE
VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

SOT343R

D

A

A

1

L

p

Q

detail X

c

H

E

E

v M

A

AB

0 1 2 mm

scale

X

21

43

Plastic surface-mounted package; reverse pinning; 4 leads SOT343R

w M

B

97-05-21
06-03-16

b

p

UNIT

A

1

max

b

p

cD

E

b

1

H

E

L

p

Qwv

mm

0.1

1.1

0.8

0.4

0.3

0.25

0.10

0.7

0.5

2.2

1.8

1.35

1.15

e

2.2

2.0

1.3

e

1

0.2y0.10.21.15

DIMENSIONS (mm are the original dimensions)

0.45

0.15

0.23

0.13

e

1

A

e

y

b

1

N-channel dual-gate MOS-FET BF998WR

PACKAGE OUTLINE

1997 Sep 05 10

NXP Semiconductors Product specification

N-channel dual-gate MOS-FET BF998WR

DATA SHEET STATUS

DOCUMENT

STATUS

Objective data sheet Development This docume nt contains data from the objective specification for product

Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.

Notes

1. Please consult the most recently issued document before initiating or co mpleting a design.

2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.

DEFINITIONS
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provided in a Product data sheet shall define the
specification of the product as agreed between NXP
Semiconductors and its customer, unless NXP
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an
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product is deemed to offer functions and qualities beyond
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Limited warranty and liability  Information in this

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(1)

PRODUCT
STATUS

(2)

DEFINITION

development.

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reserves the right to make changes to information
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Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
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Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the ris ks
associated with their applications and products.

1997 Sep 05 11

NXP Semiconductors Product specification

N-channel dual-gate MOS-FET BF998WR

NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
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customer(s). NXP does not accept any liability in this
respect.

Limiting values  Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Rec ommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
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reliability of the device.

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Quick reference data  The Quick reference data is an
extract of the product data given in t he Limiting values and
Characteristics sections of this document, and as such is
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In the event that customer uses the product for design-in
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Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.

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1997 Sep 05 12

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
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This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.

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The information presented in this document does not form part of any quotation or co nt ra ct, is b elieve d to be accurate and reliable and may be changed
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Printed in The Netherlands R77/02/pp13 Date of release: 1997 Sep 05