Philips bf909_r Datasheet

BF909; BF909R

N-channel dual gate MOS-FETs

Rev. 02 — 19 November 2007 Product data sheet

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NXP Semiconductors

NXP Semiconductors Product specification

Rev. 02 - 19 November 2007

2 of 12

N-channel dual gate MOS-FETs BF909; BF909R

FEATURES

• Specially designed for use at 5 V supply voltage

• High forward transfer admittance

• Short channel transistor with high forward transfer

admittance to input capacitance ratio

• Low noise gain controlled amplifier up to 1 GHz

• Superior cross-modulation performance during AGC.

APPLICATIONS

• VHF and UHF applications with 3 to 7 V supply voltage
such as television tuners and professional
communications equipment.

DESCRIPTION

Enhancement type field-effect transistor in a plastic
microminiature SOT143 or SOT143R package. The

handbook, halfpage

43

d

transistor consists of an amplifier MOS-FET with source
and substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.

CAUTION

The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handling.

PINNING

PIN SYMBOL DESCRIPTION

1 s, b source
2 d drain
3g
4g

handbook, halfpage

34

gate 2

2

gate 1

1

d

g

2

g

1

21

Top view

BF909 marking code: %M3.

MAM124

Fig.1 Simplified outline (SOT143) and symbol.

s,b

12

Top view

BF909R marking code: %M4.

MAM125 - 1

Fig.2 Simplified outline (SOT143R) and symbol.

g

2

g

1

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DS

I

D

P

tot

T

j

y

 forward transfer admittance 36 43 50 mS

fs

C

ig1-s

C

rs

drain-source voltage −−7V
drain current −−40 mA
total power dissipation −−200 mW
operating junction temperature −−150 °C

input capacitance at gate 1 − 3.6 4.3 pF
reverse transfer capacitance f = 1 MHz − 35 50 fF

F noise figure f = 800 MHz − 2 2.8 dB

s,b

NXP Semiconductors Product specification

Rev. 02 - 19 November 2007

3 of 12

N-channel dual gate MOS-FETs BF909; BF909R

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

Note

1. Device mounted on a printed-circuit board.

drain-source voltage − 7V
drain current − 40 mA
gate 1 current −±10 mA
gate 2 current −±10 mA
total power dissipation see Fig.3

BF909 up to T
BF909R up to T

=50°C; note 1 − 200 mW

amb

=40°C; note 1 − 200 mW

amb

storage temperature −65 +150 °C
operating junction temperature − 150 °C

250

handbook, halfpage

P

tot

(mW)

200

150

100

50

0

0 50 100 200

BF909R BF909

150

T ( C)

Fig.3 Power derating curves.

amb

MLB935

o

NXP Semiconductors Product specification

Rev. 02 - 19 November 2007

4 of 12

N-channel dual gate MOS-FETs BF909; BF909R

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

R

th j-s

Notes

1. Device mounted on a printed-circuit board.

is the temperature at the soldering point of the source lead.

2. T

s

STATIC CHARACTERISTICS

Tj=25°C; unless otherwise specified.

thermal resistance from junction to ambient note 1

BF909 500 K/W
BF909R 550 K/W

thermal resistance from junction to soldering point note 2

BF909 T
BF909R T

=92°C 290 K/W

s

=78°C 360 K/W

s

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

(BR)G1-SS

V

(BR)G2-SS

V

(F)S-G1

V

(F)S-G2

V

G1-S(th)

gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
forward source-gate 1 voltage V
forward source-gate 2 voltage V
gate 1-source threshold voltage V

G2-S=VDS
G1-S=VDS
G2-S=VDS
G1-S=VDS
G2-S

= 0; I

G1-S

= 0; I

G2-S

= 0; I

S-G1

= 0; I

S-G2

=4V; VDS=5V;

= 10 mA 6 15 V
= 10 mA 6 15 V
= 10 mA 0.5 1.5 V
= 10 mA 0.5 1.5 V

0.3 1 V

ID=20µA

V

G2-S(th)

I

DSX

gate 2-source threshold voltage V
drain-source current V

G1-S=VDS
G2-S

=5V; ID=20µA 0.3 1.2 V

=4V; VDS=5V;

12 20 mA

RG1= 120 kΩ; note 1

I

G1-SS

I

G2-SS

gate 1 cut-off current V
gate 2 cut-off current V

G1-S
G2-S

=5V; V
=5V; V

G2-S=VDS
G1-S=VDS

=0 − 50 nA
=0 − 50 nA

Note

1. R

connects gate 1 to VGG= 5 V; see Fig.18.

G1

DYNAMIC CHARACTERISTICS

Common source; T

=25°C; VDS= 5 V; V

amb

= 4 V; ID= 15 mA; unless otherwise specified.

G2-S

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

 forward transfer admittance pulsed; Tj=25°C 364350mS

y

fs

C

ig1-s

C

ig2-s

C

os

C

rs

F noise figure f = 800 MHz; G

input capacitance at gate 1 f = 1 MHz − 3.6 4.3 pF
input capacitance at gate 2 f = 1 MHz − 2.3 3 pF
drain-source capacitance f = 1 MHz − 2.3 3 pF
reverse transfer capacitance f = 1 MHz − 35 50 fF

S=GSopt

; BS=B

− 2 2.8 dB

Sopt

NXP Semiconductors Product specification

Rev. 02 - 19 November 2007

5 of 12

N-channel dual gate MOS-FETs BF909; BF909R

110

handbook, halfpage

V

unw

(dBµV)

100

90

80

0

10 50

VDS= 5V; VGG= 5 V; fw= 50 MHz.
f

= 60 MHz; T

unw

=25°C; RG1= 120 kΩ.

amb

20 30 40

gain reduction (dB)

MLB936

Fig.4 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical
values; see Fig.18.

30

handbook, halfpage

V = 4 V

I

D

G2 S

3 V 2.5 V

(mA)

20

10

0

0

0.4 2.0

VDS=5V.
Tj=25°C.

0.8 1.2 1.6

Fig.5 Transfer characteristics; typical values.

MLB937

2 V

1.5 V

1 V

V (V)

G1 S

30

handbook, halfpage

I

D

(mA)

20

10

0

0

VDS=5V.
V

=4V.

G2-S

Tj=25°C.

210

V = 1.4 V

G1 S

1.3 V

1.2 V

1.1 V

1.0 V

0.9 V

468

Fig.6 Output characteristics; typical values.

MLB938

V (V)

DS

200

handbook, halfpage

I

G1

(µA)

150

100

50

0

VDS=5V.
Tj=25°C.

0123

V = 4 V

G2 S

3.5 V

3 V

2.5 V

2 V

V (V)

Fig.7 Gate 1 current as a function of gate 1

voltage; typical values.

MLB939

G1 S

NXP Semiconductors Product specification

Rev. 02 - 19 November 2007

6 of 12

N-channel dual gate MOS-FETs BF909; BF909R

60

handbook, halfpage

y

fs

(mS)

40

20

0

0

VDS=5V.
Tj=25°C.

10 20 30

Fig.8 Forward transfer admittance as a

function of drain current; typical values.

MLB940

V = 4 V

G2 S

3.5 V
3 V

2.5 V

2 V

I (mA)

D

25

handbook, halfpage

I

D

(mA)

20

15

10

5

0

0204060

VDS= 5 V; V
Tj=25°C.

G2-S

=4V.

MLB941

I (µA)

G1

Fig.9 Drain current as a function of gate 1 current;

typical values.

16

handbook, halfpage

I

D

(mA)

12

8

4

0

0246

VDS= 5 V; V
RG1= 120 kΩ (connected to VGG); Tj=25°C.

G2-S

=4V.

Fig.10 Drain current as a function of gate 1

supply voltage (= VGG); typical values;
see Fig.18.

MLB942

V (V)

GG

30

handbook, halfpage

I

D

(mA)

20

10

0

0

V

=4V.

G2-S

RG1 connected to VGG; Tj=25°C.

R = 47 kΩ

G1

24 8

68 kΩ

V = V (V)

GG DS

Fig.11 Drain current as a function of gate 1

(= VGG) and drain supply voltage;
typical values; see Fig.18.

MLB943

82 kΩ

100 kΩ
120 kΩ

150 kΩ
180 kΩ
220 kΩ

6

NXP Semiconductors Product specification

Rev. 02 - 19 November 2007

7 of 12

N-channel dual gate MOS-FETs BF909; BF909R

V = 5 V

GG

4.5 V
4 V

3.5 V
3 V

V (V)

G2 S

MLB944

20

handbook, halfpage

I

D

(mA)

16

12

8

4

0

0246

VDS= 5 V; Tj=25°C.
RG1= 120 kΩ (connected to VGG).

Fig.12 Drain current as a function of gate 2 voltage;

typical values; see Fig.18.

40

handbook, halfpage

I

G1

(µA)

30

20

10

0

0246

VDS= 5 V; Tj=25°C.
RG1= 120 kΩ (connected to VGG).

V = 5 V

Fig.13 Gate 1 current as a function of gate 2

voltage; typical values; see Fig.18.

MLB945

GG

4.5 V
4 V

3.5 V
3 V

V (V)

G2 S

f (MHz)

MLB946

10

2

10

handbook, halfpage

y

is

(mS)

10

1

1

10

10

VDS= 5 V; VG2=4V.
ID= 15 mA; T

amb

=25°C.

b

is

g

is

2

10

Fig.14 Input admittance as a function of frequency;

typical values.

f (MHz)

MLB947

3

10

ϕ

rs

(deg)

2

10

10

1

3

10

3

10

y

rs

(µS)

ϕ

2

10

10

3

1

10

VDS= 5 V; VG2=4V.
ID= 15 mA; T

amb

=25°C.

rs

y

rs

2

10

Fig.15 Reverse transfer admittance and phase as

a function of frequency; typical values.

NXP Semiconductors Product specification

Rev. 02 - 19 November 2007

8 of 12

N-channel dual gate MOS-FETs BF909; BF909R

2

10

y

fs

(mS)

10

1

10

VDS= 5 V; VG2=4V.
ID= 15 mA; T

amb

=25°C.

y

fs

ϕ

fs

2

10

f (MHz)

MLB948

3

10

Fig.16 Forward transfer admittance and phase as

a function of frequency; typical values.

10

ϕ

(deg)

10

1

f (MHz)

MLB949

3

10

2

fs

10

handbook, halfpage

y

os

(mS)

1

1

10

2

10

10

VDS= 5 V; VG2=4V.
ID= 15 mA; T

amb

=25°C.

b

os

g

os

2

10

Fig.17 Output admittance as a function of

frequency; typical values.

R

GEN

50 Ω

V

V

AGC

R1

10 kΩ

C2

4.7 nF

R2

50 Ω

I

V

GG

C1

4.7 nF

DUT

R

G1

R3

10 Ω

C5

2.2
pF

≈

V

DS

C3 12 pF

L1

350 nH

C4

4.7 nF

R
50 Ω

MLD151

L

Fig.18 Cross-modulation test set-up.

NXP Semiconductors Product specification

Rev. 02 - 19 November 2007

9 of 12

N-channel dual gate MOS-FETs BF909; BF909R

Table 1 Scattering parameters: T

s

f

(MHz)

MAGNITUDE

(ratio)

11

ANGLE

(deg)

=25°C; VDS= 5 V; V

amb

s

21

MAGNITUDE

(ratio)

G2-S

ANGLE

(deg)

= 4 V; ID=15mA

s

12

MAGNITUDE

(ratio)

ANGLE

(deg)

s

MAGNITUDE

(ratio)

22

ANGLE

(deg)

50 0.985 −6.4 4.064 172.3 0.001 86.9 0.985 −3.2
100 0.978 −12.6 3.997 164.9 0.002 82.7 0.982 −6.4
200 0.957 −25.0 3.886 150.8 0.005 74.3 0.973 −12.6
300 0.931 −36.5 3.682 137.3 0.006 68.9 0.960 −18.6
400 0.899 −47.6 3.484 123.8 0.007 59.6 0.947 −24.2
500 0.868 −57.4 3.260 111.7 0.007 57.9 0.936 −29.6
600 0.848 −66.6 3.053 101.0 0.006 58.5 0.927 −34.8
700 0.816 −74.6 2.829 90.3 0.005 65.5 0.919 −39.8
800 0.792 −82.2 2.652 79.9 0.005 83.3 0.913 −44.6
900 0.772 −89.3 2.470 69.5 0.005 114.9 0.910 −49.5
1000 0.754 −95.6 2.328 59.5 0.006 138.7 0.909 −54.6

Table 2 Noise data: T

f

(MHz)

=25°C; VDS= 5 V; V

amb

F

min

(dB)

= 4 V; ID=15mA

G2-S

(ratio) (deg)

Γ

opt

r

n

800 2.00 0.603 67.71 0.581

NXP Semiconductors Product specification

Rev. 02 - 19 November 2007

10 of 12

N-channel dual gate MOS-FETs BF909; BF909R

PACKAGE OUTLINES

handbook, full pagewidth

Dimensions in mm.

10

max

3.0

0.150

1.1
30

max

0.090

0.1

max

max

o

o

10

0.88

0.75

0.60

o

max

2.8

1.9

43

1

2

0

0.1

TOP VIEW

0.48

1.7

0

0.1

B

A

1.4

1.2

M0.1 AB

2.5

max

0.2

MBC845

M

AB

Fig.19 SOT143.

handbook, full pagewidth

Dimensions in mm.

0.40

0.25

10

max

3.0

0.150

0.090

30

max

o

0.1

max

10

max

o

0.48

0.38

o

1.1

max

2.8

1.9

34

2

1

0.88

0.78

1.7

M0.1 B

TOP VIEW

B

A

1.4

1.2

MBC844

2.5

max

0.2

A

M

Fig.20 SOT143R.

NXP Semiconductors

Rev. 02 - 19 November 2007

11 of 12

Legal information

Data sheet status

BF909; BF909R

N-channel dual gate MOS-FETs

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
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information is available on the Internet at URL

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For sales office addresses, send an email to: [email protected]

NXP Semiconductors

BF909; BF909R

N-channel dual gate MOS-FETs

Revision history

Revision history

Document ID Release date Data sheet status Change notice Supersedes

BF909_N_2 20071119 Product data sheet - BF909_1
Modifications:
BF909_1 19950425 Product specification - -

• Fig.1 and 2 on page 2; Figure note changed

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

© NXP B.V. 2007. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]

Date of release: 19 November 2007

Document identifier: BF909_N_2