Philips bf904wr Datasheet

DATA SH EET

DISCRETE SEMICONDUCTORS

BF904WR

N-channel dual-gate MOS-FET

Product specification
Supersedes data of 1995 Apr 25

2010 Sep 15

NXP Semiconductors Product specification

Fig.1 Simplified outline (SOT343R) and symbol.

Marking code: MC*

handbook, halfpage

MAM192

s,b

d

g

1

g

2

Top view

21

34

* = - : made in Hong Kong
* = p : made in Hong Kong
* = t : made in Malaysia

N-channel dual-gate MOS-FET BF904WR

FEATURES

 Specially designed for use at 5 V supply voltage
 Short channel transistor with high forward transfer

admittance to input capacitance ratio

 Low noise gain controlled amplifier up to 1 GHz
 Superior cross-modulation performance during AGC.

APPLICATIONS

 VHF and UHF applications with 3 to 7 V supply voltage

such as television tuners and professional
communications equipment.

DESCRIPTION

Enhancement type field-effect transistor in a plastic
microminiature SOT343R package. The transistor
consists of an amplifier MOS-FET with source and
substrate interconnected and an internal bias circuit to
ensure good cross-modulation performance during AGC.

CAUTION

The device is supplied in an antistatic package. The
gate-source input must be protected against static
discharge during transport or handlin g.

PINNING

PIN SYMBOL DESCRIPTION

1s, bsource
2 d drain
3g
4g

gate 2

2

gate 1

1

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

DS

I

D

P

tot

T

j

 forward transfer admittance 22 25 30 mS

y

fs

C

ig1-s

C

rs

drain-source voltage 7V
drain current 30 mA
total power dissipation 280 mW
operating junction temperature 150 C

input capacitance at gate 1  2.2 2.6 pF
reverse transfer capacitance f = 1 MHz  25 35 fF

F noise figure f = 800 MHz  2  dB

2010 Sep 15 2

NXP Semiconductors Product specification

Fig.2 Power derating curve.

handbook, halfpage

0 50 100 200

300

0

MLD150

150

200

100

P

tot

(mW)

T ( C)

amb

o

N-channel dual-gate MOS-FET BF904WR

LIMITING VALUES

In accordance with the Absolu te Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

Note

1. Device mounted on a printed-circuit board.

drain-source voltage  7V
drain current  30 mA
gate 1 current 10 mA
gate 2 current 10 mA
total power dissipation up to T

=50C; see Fig.2;

amb

 280 mW

note 1
storage temperature 65 +150 C
operating junction temperature  +150 C

2010 Sep 15 3

NXP Semiconductors Product specification

N-channel dual-gate MOS-FET BF904WR

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th j-a

R

th j-s

Notes

1. Device mounted on a printed-circuit board.

2. T

is the temperature at the soldering point of the source lead.

s

STATIC CHARACTERISTICS

=25C; unless otherwise specified.

T

j

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

(BR)G1-SS

V

(BR)G2-SS

V

(F)S-G1

V

(F)S-G2

V

G1-S(th)

V

G2-S(th)

I

DSX

I

G1-SS

I

G2-SS

thermal resistance from junction to ambient note 1 350 K/W
thermal resistance from junction to soldering point Ts=91C; note 2 210 K/W

gate 1-source breakdown voltage V
gate 2-source breakdown voltage V
forward source-gate 1 voltage V
forward source-gate 2 voltage V
gate 1-source threshold voltage V
gate 2-source threshold voltage V
drain-source current V

G2-S=VDS
G1-S=VDS
G2-S=VDS
G1-S=VDS
G2-S
G1-S=VDS
G2-S

=0; I
=0; I
=0; I
=0; I

=10mA 6 15 V

G1-S

=10mA 6 15 V

G2-S

=10mA 0.5 1.5 V

S-G1

=10mA 0.5 1.5 V

S-G2

=4V; VDS=5V; ID=20A0.31V

=5V; ID=20A0.31.2V

=4V; VDS=5V; RG1=120k;

813mA

note 1
gate 1 cut-off current V
gate 2 cut-off current V

G2-S=VDS
G1-S=VDS

=0; V
=0; V

=5V  50 nA

G1-S

=5V  50 nA

G2-S

Note

connects gate 1 to VGG=5V.

1. R

G

DYNAMIC CHARACTERISTICS

Common source; T

=25C; VDS=5V; V

amb

=4V; ID= 10 mA; un less otherwise specified.

G2-S

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

y

 forward transfer admittance pulsed; Tj=25C222530mS

fs

C

ig1-s

C

ig2-s

C

os

C

rs

F noise figure f = 200 MHz; G

input capacitance at gate 1 f = 1 MHz  2.2 2.6 pF
input capacitance at gate 2 f = 1 MHz 1 1.5 2 pF
drain-source capacitance f = 1 MHz 1 1.3 1.6 pF
reverse transfer capacitance f = 1 MHz  25 35 fF

f=800MHz; G

=2mS; BS=B

S
S=GSopt

; BS=B

 11.5dB

Sopt

 22.8dB

Sopt

2010 Sep 15 4

NXP Semiconductors Product specification

Fig.3 Forward transfer admittance as a function

of junction temperature; typical values.

50 0 50 150

30

0

MLD268

100

T ( C)

o

j

Y

fs

(mS)

40

20

10

Fig.4 Typical gain reduction as a function of

AGC voltage.

f=50MHz.
Tj=25C.

handbook, halfpage

0

10

20

30

40

50

01234

V (V)

AGC

gain

reduction

(dB)

MRA769

Fig.5 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical
values; see Fig.19.

VGG=5V; fw=50MHz.
f

unw

=60MHz; T

amb

=25C; RG1=120k

handbook, halfpage

80

90

100

110

120

0 1020304050

V

unw

(dB V)

gain reduction (dB)

MRA771

μ

Fig.6 Transfer characteristics; typical values.

VDS=5V.
T

j

=25C.

0

20

10

15

5

0

0.4 2.0

MLD270

0.8 1.2 1.6

I

D

(mA)

V (V)

G1 S

2 V

1.5 V

1 V

V = 4 V

3 V 2.5 V

G2 S

N-channel dual-gate MOS-FET BF904WR

2010 Sep 15 5

NXP Semiconductors Product specification

Fig.7 Output characteristics; typical values.

V

G2-S

=4V.

Tj=25C.

handbook, halfpage

0

20

8

12

16

4

0

210

MLD269

468

I

D

(mA)

V (V)

DS

1.3 V

1.2 V

1.1 V

1.0 V

0.9 V

V = 1.4 V

G1 S

Fig.8 Gate 1 current as a function of gate 1

voltage; typical values.

VDS=5V.
Tj=25C.

handbook, halfpage

0

150

100

50

0

0.5 2.5

MLD271

1.0 1.5 2.0

I

G1

(μA)

V (V)

G1 S

3.5 V

2.5 V

2 V

3 V

V = 4 V

G2 S

Fig.9 Forward transfer admittance as a

function of drain current; typical values.

VDS=5V.
Tj=25C.

handbook, halfpage

0

40

30

20

10

0

4 8 12 16 20

MLD272

y

fs

(mS)

I (mA)

D

3 V

2.5 V

2 V

V = 4 V

G2 S

3.5 V

Fig.10 Drain current as a function of gate 1 current;

typical values.

VDS=5V; V

G2-S

=4V.

Tj=25C.

handbook, halfpage

0

16

8

12

4

0

10 50

MLD273

20 30 40

I

D

(mA)

I (μA)

G1

N-channel dual-gate MOS-FET BF904WR

2010 Sep 15 6

NXP Semiconductors Product specification

Fig.11 Drain current as a function of gate 1

supply voltage (= V

GG

); typical values;

see Fig.19.

VDS=5V; V

G2-S

=4V.

RG1=120k (connected to VGG); Tj=25C.

handbook, halfpage

0

12

8

4

0

15

MLD275

234

I

D

(mA)

V (V)

GG

Fig.12 Drain current as a function of gate 1

(= V

GG

) and drain supply voltage;

typical values; see Fig.19.

V

G2-S

=4V.

RG1 connected to VGG; Tj=25C.

handbook, halfpage

0

20

10

15

5

0

24 8

MLD274

6

V = V (V)

GG DS

I

D

(mA)

R = 47 kΩ

G1

68 kΩ

82 kΩ

100 kΩ
120 kΩ
150 kΩ

180 kΩ
220 kΩ

VDS=5V; Tj=25C.
RG=120k (connected to VGG).

Fig.13 Drain current as a function of gate 2 voltage;

typical values; see Fig.19.

handbook, halfpage

0246

12

0

MLD276

8

4

I

D

(mA)

4.5 V

4 V

3.5 V
3 V

V (V)

G2 S

V = 5 V

GG

Fig.14 Gate 1 current as a function of gate 2

voltage; typical values; see Fig.19.

VDS=5V; Tj=25C.
RG=120k (connected to VGG).

handbook, halfpage

0246

40

30

10

0

20

MLB945

I

G1

(μA)

V (V)

G2 S

4.5 V
4 V

3.5 V
3 V

V = 5 V

GG

N-channel dual-gate MOS-FET BF904WR

2010 Sep 15 7

NXP Semiconductors Product specification

Fig.15 Input admittance as a function of frequency;

typical values.

VDS=5V; VG2=4V.
ID=10mA; T

amb

=25C.

handbook, halfpage

10

3

MLD277

10

2

10

10

1

10

2

10

1

y

is

(mS)

f (MHz)

b

is

g

is

Fig.16 Reverse transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V.
ID=10 mA; T

amb

=25C.

10

3

MLD278

10

2

10

10

3

10

2

10

1

y

rs

10

3

10

10

1

2

rs

(μS)

f (MHz)

rs

y

rs

(deg)

ϕ

ϕ

Fig.17 Forward transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V.
ID=10mA; T

amb

=25C.

10

3

MLD279

10

2

10

1

10

2

10

1

10

10

2

y

fs

(mS)

y

fs

f (MHz)

fs

fs

(deg)

ϕ

ϕ

Fig.18 Output admittance as a function of

frequency; typical values.

VDS=5V; VG2=4V.
ID=10mA; T

amb

=25C.

handbook, halfpage

10

3

MLD280

10

2

10

10

1

10

1

10

2

y

os

(mS)

f (MHz)

b

os

g

os

N-channel dual-gate MOS-FET BF904WR

2010 Sep 15 8

NXP Semiconductors Product specification

Fig.19 Cross-modulation test set-up.

DUT

V

AGC

C1

4.7 nF

R1

10 kΩ

MLD171

C4

4.7 nF

L1

450 nH

C3 12 pF

R

L

50 Ω

≈

V

GG

V

DS

R

GEN

50

V

I

R2

50

4.7 nF

C2

R

G1

Ω

Ω

N-channel dual-gate MOS-FET BF904WR

2010 Sep 15 9

NXP Semiconductors Product specification

N-channel dual-gate MOS-FET BF904WR

Table 1 Scattering parameters: VDS=5 V; V

s

f

(MHz)

MAGNITUDE

(ratio)

11

ANGLE

(deg)

MAGNITUDE

(ratio)

=4V; ID=10mA

G2-S

s

21

ANGLE

(deg)

s

12

MAGNITUDE

(ratio)

ANGLE

(deg)

s

22

MAGNITUDE

(ratio)

ANGLE

(deg)

40 0.989 3.4 2.420 175.7 0.000 79.9 0.993 1.6
100 0.985 8.3 2.414 169.1 0.001 78.3 0.992 3.9
200 0.976 16.4 2.368 158.8 0.003 80.3 0.987 7.8
300 0.958 24.1 2.301 148.5 0.004 73.7 0.980 11.4
400 0.942 32.0 2.251 138.8 0.005 70.7 0.974 15.2
500 0.918 39.3 2.170 129.5 0.005 67.2 0.966 18.7
600 0.899 46.0 2.080 120.7 0.005 67.8 0.958 22.2
700 0.876 52.6 2.001 112.1 0.005 68.6 0.951 25.5
800 0.852 58.8 1.924 103.2 0.005 72.9 0.944 28.9
900 0.823 64.9 1.829 94.7 0.005 78.7 0.937 32.1

1000 0.800 70.9 1.747 86.5 0.005 88.3 0.933 35.2
1200 0.750 82.4 1.621 70.7 0.005 120.5 0.928 41.7
1400 0.719 92.7 1.535 54.6 0.008 139.8 0.930 48.4
1600 0.682 102.5 1.424 39.4 0.010 137.8 0.924 54.9
1800 0.642 109.8 1.349 22.5 0.013 156.8 0.928 62.9
2000 0.602 116.5 1.283 1.1 0.018 175.1 0.928 73.1
2200 0.547 124.9 1.130 15.1 0.014 172.6 0.887 81
24

00 0.596 128.7 1.018 49.1 0.040 163.9 0.837 95.8

2600 0.682 132.6 0.979 79.4 0.077 164.0 0.778 109.6
2800 0.771 142.5 0.804 116.2 0.120 178.8 0.629 119.5
3000 0.793 157.5 0.541 153.5 0.149 158.3 0.479 119.9

.0

Table 2 Noise data: V

f

(MHz)

=5V; V

DS

=4V; ID=10mA

G2-S

F

min

(dB)



opt

(ratio) (deg)

r

n

800 2.00 .686 49.6 50.40

2010 Sep 15 10

NXP Semiconductors Product specification

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

SOT343R

D

A

A

1

L

p

Q

detail X

c

H

E

E

v M

A

AB

0 1 2 mm

scale

X

21

43

Plastic surface-mounted package; reverse pinning; 4 leads SOT343R

w M

B

97-05-21
06-03-16

b

p

UNIT

A

1

max

b

p

cD

E

b

1

H

E

L

p

Qwv

mm

0.1

1.1

0.8

0.4

0.3

0.25

0.10

0.7

0.5

2.2

1.8

1.35

1.15

e

2.2

2.0

1.3

e

1

0.2y0.10.21.15

DIMENSIONS (mm are the original dimensions)

0.45

0.15

0.23

0.13

e

1

A

e

y

b

1

N-channel dual-gate MOS-FET BF904WR

PACKAGE OUTLINE

2010 Sep 15 11

NXP Semiconductors Product specification

N-channel dual-gate MOS-FET BF904WR

DATA SHEET STATUS

DOCUMENT

STATUS

Objective data sheet Development This document contains data from the objective specification for product

Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.

Notes

1. Please consult the most recently issued document before initiating or co mpleting a design.

2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.

DISCLAIMERS
Limited warranty and liability  Information in this

document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
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reserves the right to make changes to information
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expected to result in personal injury, death or severe

(1)

PRODUCT
STATUS

(2)

DEFINITION

development.

property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inc l usion and/or use is at
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Applications  Applications that ar e described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.

Customers are responsible for the design and operation of
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Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
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Semiconductors product is suitable and fit for the
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the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.

2010 Sep 15 12

NXP Semiconductors Product specification

N-channel dual-gate MOS-FET BF904WR

Limiting values  Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Rec ommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.

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Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
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Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
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Quick reference data  The Quick reference data is an
extract of the product data given in t he Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.

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In the event that customer uses the product for design-in
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Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.

2010 Sep 15 13

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This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for the marking codes
and the package outline drawings which were updated to the latest version.

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Printed in The Netherlands R77/02/pp14 Date of release: 2010 Sep 15