Philips bf1211_r_wr Datasheet

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Page 1

DATA SH EET

DISCRETE SEMICONDUCTORS

BF1211; BF1211R; BF1211WR

N-channel dual-gate MOS-FETs

Product specification 2003 Dec 16

Page 2

NXP Semiconductors Product specification

handbook, 2 columns

Top view

MSB014

Fig.1 Simplified outline (SOT143B).

BF1211 marking code: LFp

handbook, 2 columns

Top view MSB035

Fig.2 Simplified outline (SOT143R).

BF1211R marking code: LHp

handbook, halfpage

Top view

MSB842

Fig.3 Simplified outline (SOT343R).

BF1211WR marking code: MK

N-channel dual-gate MOS-FETs

FEATURES

 Short channel transistor with high forward transfer

admittance to input capacitance ratio

 Low noise gain controlled amplifier  Excellent low frequency noise performance  Partly internal self-biasing circuit to ensure good

cross-modulation performance during AGC and go od DC stabilization.

APPLICATIONS

 Gain controlled low noise VHF and UHF amplifiers for

5 V digital and analog television tuner applications.

DESCRIPTION

Enhancement type N-channel field-effect transistor with source and substrate interconnected. Integrated diodes between gates and source protect against excessive input voltage surges. The BF1211, BF1211R and BF1211WR are encapsulated in the SOT143B, SOT143R and SOT343R plastic packages respectively.

BF1211; BF1211R;

BF1211WR

PINNING

PIN DESCRIPTION

1source 2drain 3gate2 4gate1

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

tot

 forward transfer admittance 25 30 40 mS

y

ig1-ss

rss

drain-source voltage 6V drain current 30 mA total power dissipation 180 mW

input capacitance at gate 1  2.1 2.6 pF reverse transfer capacitance f = 1 MHz  15 30 fF

F noise figure f = 400 MHz  0.9 1.6 dB

cross-modulation input level for k = 1% at

junction temperature 150 C

mod

2003 Dec 16 2

100 105  dBV

40 dB AGC

Page 3

NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

CAUTION

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling.

ORDERING INFORMATION

T YPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

BF1211  plastic surface mounted package; 4 leads SOT143B BF1211R  plastic surface mounted package; reverse pinning; 4 leads SOT143R BF1211WR  plastic surface mounted package; reverse pinning; 4 leads SOT343R

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 601 34).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

tot

stg

drain-source voltage  6V drain current (DC)  30 mA gate 1 current 10 mA gate 2 current 10 mA total power dissipation

BF1211; BF1211R T BF1211WR T

 116 C; note 1  180 mW

 122 C; note 1  180 mW

storage temperature 65 +150 C junction temperature  150 C

Note

1. T

is the temperature of the soldering point of the source lead.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

th(j-s)

thermal resistance from junction to soldering point

BF1211; BF1211R 185 K/W BF1211WR 155 K/W

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NXP Semiconductors Product specification

handbook, halfpage

0 50 100 200

250

200

150

100

MDB828

(2) (1)

tot

(mW)

Ts (°C)

Fig.4 Power derating curve.

(1) BF1211WR. (2) BF1211; BF1211R.

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

STATIC CHARACTERISTICS

=25C unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

(BR)DSS

(BR)G1-SS

(BR)G2-SS

(F)S-G1

(F)S-G2

G1-S(th)

G2-S(th)

DSX

drain-source breakdown voltage V gate 1-source breakdown voltage V gate 2-source breakdown voltage V forward source-gate 1 voltage V forward source-gate 2 voltage V gate 1-source threshold voltage V gate 2-source threshold voltage V drain-source current V

G1-S=VG2-S G2-S=VDS G1-S=VDS G2-S=VDS G1-S=VDS

=4V; VDS=5V; ID=100A0.31V

G2-S

=5V; VDS=5V; ID=100A0.351V

G1-S

=4V; VDS=5V; RG1=75k;

G2-S

=0V; ID=10A6 V =0V; I =0V; I =0V; I =0V; I

=10mA 6 10 V

G1-S

=10mA 6 10 V

G2-S

=10mA 0.5 1.5 V

S-G1

=10mA 0.5 1.5 V

S-G2

11 19 mA

note 1

G1-S

G2-S

Note

1. R

gate 1 cut-off current V gate 2 cut-off current V

connects G1to VGG=5V.

G2-S=VDS G1-S=VDS

=0V; V =0V; V

=5V  50 nA

G1-S

=4V  20 nA

G2-S

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NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

DYNAMIC CHARACTERISTICS

Common source; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

y

 forward transfer admittance pulsed; Tj=25C 253040mS

C C C C

ig1-ss ig2-ss oss rss

input capacitance at gate 1 f = 1 MHz  2.1 2.6 pF input capacitance at gate 2 f = 1 MHz  1.1  pF output capacitance f = 1 MHz  0.9  pF reverse transfer capacitance f = 1 MHz  15 30 fF

F noise figure f = 11 MHz; G

mod

power gain f = 200 MHz; GS=2mS; BS=B

cross-modulation input level for k = 1%; fw=50MHz;

=25C; V

amb

=4V; VDS=5V; ID= 15 mA; unless otherwise specified.

G2-S

=20mS; BS=0  3.5  dB

f=400MHz; Y f=800MHz; Y

= 0.5 mS; BL=B

f=400MHz; G

=1mS; BL=B

f=800MHz; G

=1mS; BL=B

=60MHz; note1

unw

S=YS(opt) S=YS(opt)

L(opt)

=2mS; BS=B

L(opt)

= 3.3 mS; BS=B

L(opt)

S(opt)

;

at 0 dB AGC 90 dBV at 10 dB AGC  92  dBV at 40 dB AGC 100 105  dBV

 0.9 1.6 dB  1.3 2 dB  34  dB

 29  dB

 24  dB

Note

1. Measured in test circuit Fig.21.

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NXP Semiconductors Product specification

handbook, halfpage

0 2.5

0.5 1 1.5 2

MDB829

(1) (2) (3) (4)

(5)

(6)

(7)

(mA)

G1-S

(V)

Fig.5 Transfer characteristics; typical values.

VDS=5V; Tj=25C. (1) V

G2-S

=4V.

(2) V

G2-S

=3.5V.

(3) V

G2-S

=3V.

(4) V

G2-S

=2.5V.

(5) V

G2-S

=2V.

(6) V

G2-S

=1.5V.

(7) V

G2-S

=1V.

handbook, halfpage

024

MDB830

(mA)

(V)

(1)

(2)

(3)

(4)

(5)

(6)

(7) (8)

Fig.6 Output characteristics; typical values.

G2-S

=4V; Tj=25C.

(1) V

G1-S

=1.5V.

(2) V

G1-S

=1.4V.

(3) V

G1-S

=1.3V.

(4) V

G1-S

=1.2V.

(5) V

G1-S

=1.1V.

(6) V

G1-S

=1V.

(7) V

G1-S

=0.9V.

(8) V

G1-S

=0.8V.

handbook, halfpage

100

0.5 1 1.5 2

MDB831

(μA)

G1-S

(V)

(1) (2) (3)

(5)

(4)

(6)

(7)

Fig.7 Gate 1 current as a function of gate 1

voltage; typical values.

VDS=5V; Tj=25C. (1) V

G2-S

=4V.

(2) V

G2-S

=3.5V.

(3) V

G2-S

=3V.

(4) V

G2-S

=2.5V.

(5) V

G2-S

=2V.

(6) V

G2-S

=1.5V.

(7) V

G2-S

=1V.

handbook, halfpage

06 30

12 18 24

MDB832

(mS)

ID (mA)

(1) (2)

(3)

(4)(5)(6)

Fig.8 Forward transfer admittance as a function

of drain current; typical values.

VDS=5V; Tj=25C. (1) V

G2-S

=4V.

(2) V

G2-S

=3.5V.

(3) V

G2-S

=3V.

(4) V

G2-S

=2.5V.

(5) V

G2-S

=2V.

(6) V

G2-S

=1.5V.

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

2003 Dec 16 6

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NXP Semiconductors Product specification

handbook, halfpage

050

10 20 30 40

MDB833

(mA)

IG1(μA)

Fig.9 Drain current as a function of gate 1 current;

typical values.

VDS=5V; V

G2-S

=4V.

Tj=25C.

handbook, halfpage

01 5

23 4

MDB834

(mA)

(V)

Fig.10 Drain current as a function of gate 1 supply

voltage (V

); typical values.

VDS=5V; V

G2-S

=4V; Tj=25C.

RG1=75k (connected to VGG); see Fig.21.

handbook, halfpage

0246

MDB835

(mA)

VGG = VDS (V)

(7)

(6)

(5)

(4)

(3)

(2)(1)

Fig.11 Drain current as a function of gate 1 (VGG)

and drain supply voltage; typical values.

G2-S

=4V; Tj=25C; RG1 connected to VGG; see Fig.21.

(1) R

=47k.

(2) R

=56k.

(3) R

=68k.

(4) RG1=75k. (5) R

=82k.

(6) R

= 100 k.

(7) RG1=120k.

handbook, halfpage

0246

MDB836

(mA)

G2-S

(V)

(2)

(1)

(3) (4) (5)

Fig.12 Drain current as a function of gate 2

voltage; typical values.

(1) VGG=5V. (2) VGG=4.5V. (3) VGG=4V.

(4) VGG=3.5V. (5) VGG=3V.

VDS=5V; Tj=25C; RG1=75k (connected to VGG); see Fig.21.

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

2003 Dec 16 7

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NXP Semiconductors Product specification

handbook, halfpage

0246

MDB837

(μA)

G2-S

(V)

(1)

(2)

(3)

(4)

(5)

Fig.13 Gate 1 cu rrent as a function of gate 2

voltage; typical values.

VDS=5V; Tj=25C; RG1=75k (connected to VGG); see Fig.21. (1) V

=5V.

(2) VGG=4.5V.

(3) VGG=4V. (4) VGG=3.5V.

(5) VGG=3V.

handbook, halfpage

012 4

−60

−40

−20

MDB838

−10

−50

−30

gain

reduction

(dB)

AGC

(V)

Fig.14 Typical gain reduction as a function of AGC

voltage.

VDS=5V; VGG=5V; RG1=75k (connected to VGG); see Fig.21; f = 50 MHz; T

amb

=25C.

handbook, halfpage

010 50

120

110

100

20 30 40

MDB839

unw

(dBμV)

gain reduction (dB)

Fig.15 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical values.

VDS=5V; VGG=5V; RG1=75k (connected to VGG); see Fig.21; f = 50 MHz; f

unw

=60MHz; T

amb

=25C.

handbook, halfpage

050

10 20 30 40

MDB840

(mA)

gain reduction (dB)

Fig.16 Drain current as a function of gain

reduction; typical values.

VDS=5V; VGG=5V; RG1=75k (connected to VGG); see Fig.21; f = 50 MHz; T

amb

=25C.

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

2003 Dec 16 8

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NXP Semiconductors Product specification

handbook, halfpage

−1

MDB841

10 10

(mS)

f (MHz)

Fig.17 Input admittance as a function of frequency;

typical values.

VDS=5V; VG2=4V. ID=15mA; T

amb

=25C.

handbook, halfpage

MDB842

10 10

(μS)

f (MHz)

−10

−1

(deg)

Fig.18 Reverse transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V. ID=15mA; T

amb

=25C.

handbook, halfpage

MDB843

f (MHz)

(mS)

−10

−1

(deg)

Fig.19 Forwa rd transfer admittance and phase as

functions of frequency; typical values.

VDS=5V; VG2=4V. I

=15mA; T

amb

=25C.

handbook, halfpage

MDB844

10 10

−1

−2

(mS)

f (MHz)

Fig.20 Output admittance as a function of

frequency; typical values.

VDS=5V; VG2=4V. I

=15mA; T

amb

=25C.

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

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NXP Semiconductors Product specification

handbook, full pagewidth

DUT

4.7 nF

10 kΩ

MGS315

4.7 nF

≈2.2 μH

4.7 nF

50 Ω

AGC

GEN 50 Ω

50 Ω

4.7 nF

Fig.21 Cross-modulation test set-up.

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

Table 1 Scattering parameters: VDS=5V; V

(MHz)

100 0.985 7.73 2.921 171.6 0.0010 86.9 0.993 3.14

1000 0.791 72.22 2.315 99.9 0.0028 87.1 0.956 30.94

Table 2 Noise data: V

MAGNITUDE

(ratio)

ANGLE

(deg)

G2-S

MAGNITUDE

(ratio)

=4V; ID=15mA; T

ANGLE

MAGNITUDE

(deg)

amb

(ratio)

=25C

ANGLE

(deg)

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.987 3.86 2.928 175.8 0.0005 89.3 0.993 1.58

200 0.979 15.25 2.807 163.2 0.0015 91.1 0.993 6.31 300 0.965 22.84 2.846 155.0 0.0028 77.4 0.988 9.41 400 0.949 30.15 2.784 146.7 0.0034 74.0 0.985 12.48 500 0.929 30.25 2.704 138.9 0.0037 71.4 0.981 15.54 600 0.904 44.24 2.639 130.9 0.0040 69.6 0.976 18.59 700 0.876 51.16 2.558 123.0 0.0039 69.0 0.971 21.65 800 0.846 58.16 2.486 115.1 0.0037 70.0 0.965 24.27 900 0.816 65.15 2.402 107.2 0.0032 74.5 0.960 27.79

(MHz)

=5V; V

=4V; ID=15mA; T

G2-S

min

(dB)

=25C

amb



opt

(ratio) (deg)

()

400 0.9 0.693 16.75 29.85 800 1.3 0.707 37.33 29.90

2003 Dec 16 10

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NXP Semiconductors Product specification

UNIT

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

1.1

0.9

max

0.1

0.88

0.78

0.15

0.09

3.0

2.8

1.4

1.2

ywvQ

2.5

2.1

0.45

0.15

0.55

0.45

1.9

1.7

0.1 0.10.2

0.48

0.38

DIMENSIONS (mm are the original dimensions)

SOT143B

04-11-16 06-03-16

0 1 2 mm

scale

Plastic surface-mounted package; 4 leads SOT143B

detail X

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

PACKAGE OUTLINES

2003 Dec 16 11

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NXP Semiconductors Product specification

UNIT

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

1.1

0.9

max

0.1

0.88

0.78

0.15

0.09

3.0

2.8

1.4

1.2

ywvQ

2.5

2.1

0.55

0.25

0.45

0.25

1.9

1.7

0.1 0.10.2

0.48

0.38

DIMENSIONS (mm are the original dimensions)

SOT143R SC-61AA

04-11-16 06-03-16

0 1 2 mm

scale

Plastic surface-mounted package; reverse pinning; 4 leads SOT143R

v M

detail X

w M

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

2003 Dec 16 12

Page 13

NXP Semiconductors Product specification

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

SOT343R

detail X

v M

0 1 2 mm

scale

Plastic surface-mounted package; reverse pinning; 4 leads SOT343R

w M

97-05-21 06-03-16

UNIT

max

HEL

Qwv

0.1

1.1

0.8

0.4

0.3

0.25

0.10

0.7

0.5

2.2

1.8

1.35

1.15

2.2

2.0

1.3

0.2y0.10.21.15

DIMENSIONS (mm are the original dimensions)

0.45

0.15

0.23

0.13

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

2003 Dec 16 13

Page 14

NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

DATA SHEET STATUS

DOCUMENT

STATUS

Objective data sheet D evelopment This document contains data from the objective specification for product

Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification.

Notes

1. Please consult the most recently issued document before initiating or completing a design.

2. The product status of device(s) desc ribed in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

DEFINITIONS Product specification  The information and data

provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

DISCLAIMERS Limited warranty and liability  Information in this

document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

(1)

PRODUCT STATUS

(2)

DEFINITION

development.

Right to make changes  NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication he reof.

Suitability for use  NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications wher e failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inc l usion and/or use is at the customer’s own risk.

Applications  Applications that ar e described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the ris ks associated with their applications and products.

2003 Dec 16 14

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NXP Semiconductors Product specification

N-channel dual-gate MOS-FETs BF1211; BF1211R; BF1211WR

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applicat ions and products using NXP Semiconductors products in or de r to avoid a default of the applications and the prod ucts or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values  Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Rec ommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale  NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In cas e an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

Export control  This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

Quick reference data  The Quick reference data is an extract of the product data given in t he Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products  Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with auto motive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from cus tom er d esign and use o f the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

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2003 Dec 16 15

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This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.

Contact information

For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected]

The information presented in this document does not form part of any quotation or contra ct, is b elieve d t o b e a ccur ate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands R77/01/pp16 Date of release: 2003 Dec 16