Philips bf1205 Datasheet

DATA SH EET

DISCRETE SEMICONDUCTORS

MBD128

BF1205

Dual N-channel dual gate MOS-FET

Product specification 2003 Sep 30

NXP Semiconductors Product specification

handbook, halfpage

123

654

Top view

MGX429

AMP

a

d (a) s d (b)

g1 (a) g2 g1 (b)

AMP

b

Fig.1 Simplified outline and symbol.

Marking code: L4-.

Dual N-channel dual gate MOS-FET BF1205

FEATURES

 Two low noise gain controlled amplifiers in a single

package. One with a fully integrated bias and one with a partly integrated bias

 Internal switch reduces the number of external

components

 Superior cross-modulation performance during AGC  High forward transfer admittance  High forward transfer admittance to input capacitance

ratio.

APPLICATIONS

 Gain controlled low noise amplifiers for VHF and UHF

applications with 5 V supply voltage, such as digital and analog television tuners and professional communications equipment.

DESCRIPTION

The BF1205 is a combination of two equal dual gate MOS-FET amplifiers with shared source an d gate 2 lead s and an integrated switch. The integrated switch is operated by the gate 1 bias of amplifier b. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect against excessive input voltage surges. The transistor is encapsulated in SOT363 micro-miniature plastic package.

PINNING - SOT363

PIN DESCRIPTION

1gate1(a) 2gate2 3gate1(b) 4 drain (b) 5 source 6 drain (a)

ORDERING INFORMATION

PACKAGE

T YPE NUMBER

NAME DESCRIPTION VERSION

BF1205  Plastic surface mounted package; 6 leads SOT363

2003 Sep 30 2

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FET BF1205

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Per MOS-FET; unless otherw ise specified

V

DS

I

D

P

tot

y

 forward transfer admittance ID=12mA 263140 mS

fs

C

ig1-ss

C

rss

NF noise figure amp. a: f = 800 MHz  1.2 1.9 dB

X

mod

T

j

drain-source voltage 10 V drain current (DC) 30 mA total power dissipation Ts 102 C; temperature at the

200 mW

soldering point of the source lead

input capacitance at gate 1 amp. a: f = 1 MHz  1.8 2.3 pF

amp. b: f = 1 MHz  2.0 2.5 pF

reverse transfer capacitance f = 1 MHz  20  fF

amp. b: f = 800 MHz  1.4 2.1 dB

cross-modulation amp. a: input level for k = 1% at

98 102  dBV

40 dB AGC amp. b: input level for k = 1% at

100 105  dBV

40 dB AGC

junction temperature 150 C

CAUTION

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Per MOS-FET; unless otherw ise specified

V

DS

I

D

I

G1

I

G2

P

tot

T

stg

T

j

drain-source voltage  10 V drain current (DC)  30 mA gate 1 current 10 mA gate 2 current 10 mA total power dissipation Ts 102 C; note  200 mW storage temperature 65 +150 C junction temperature  150 C

Note

is the temperature at the soldering point of the source lead.

1. T

s

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-s

thermal resistance from junction to soldering point 240 K/W

2003 Sep 30 3

NXP Semiconductors Product specification

handbook, halfpage

0 50 100 200

250

0

200

MGS359

150

100

50

Ts (°C)

P

tot

(mW)

Fig.2 Power derating curve.

Dual N-channel dual gate MOS-FET BF1205

STATIC CHARACTERISTICS

T

=25C; per MOS-FET; unless otherwise specified.

j

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

(BR)DSS

V

(BR)G1-SS

V

(BR)G2-SS

V

(F)S-G1

V

(F)S-G2

V

G1-S(th)

V

G2-S(th)

I

DSX

I

G1-S

I

G2-S

drain-source breakdown voltage amp. a: V

amp. b: V

G1-S=VG2-S G1-S=VG2-S

gate-source breakdown voltage VGS=VDS=0V; I gate-source breakdown voltage VGS=VDS=0V; I forward source-gate voltage V forward source-gate voltage V

G2-S=VDS G1-S=VDS

gate-source threshold voltage VDS=5V; V gate-source threshold voltage VDS=5V; V drain-source current amp. a: V

=150k; note 1

R

G1

amp. b: V

=150k; note 2

R

G1

gate cut-off current amp. a: V

amp. b: V

gate cut-off current V

G2-S

=0V; I =0V; I

G2-S G1-S

G2-S

G1-S G1-S

=4V; V

=4V; VDS=5V;

=5V; V =5V; V

G1-S=VDS

=0V; ID=10A10  V =0V; ID=10A7  V

=10mA 6 10 V

G1-S

=10mA 6 10 V

G2-S

=10mA 0.5 1.5 V

S-G1

=10mA 0.5 1.5 V

S-G2

=4V; ID=100A0.31 V =5V; ID=100A0.41.0V

816mA

G2-S=VDS G2-S=VDS

=0V  50 nA =0V  50 nA

=0V  20 nA

Note

1. R

2. R

connects gate 1 (b) to VGG= 0 V (see Fig.4).

G1

connects gate 1 (b) to VGG= 5 V (see Fig.4).

G1

2003 Sep 30 4

NXP Semiconductors Product specification

handbook, halfpage

0

VGG (V)

5

16

12

4

0

8

2314

MGX430

I

D

(mA)

(1)

(2)

(3)

(4) (5) (6)

Fig.3 Drain currents of MOS-FET a and b as

functions of V

GG

(see Fig.4).

(1) ID (b); RG1=120k. (2) ID (b); RG1=150k. (3) ID (b); RG1=180k.

(4) ID (a); RG1=180k. (5) ID (a); RG1=150k. (6) ID (a); RG1=120k.

handbook, halfpage

MGX431

V

GG

R

G1

d (a)

s

d (b)

g1 (a)

g2

g1 (b)

Fig.4 Functional diagram

VGG= 5 V: amplifier a is OFF; amplifier b is ON. VGG= 0 V: amplifier a is ON; amplifier b is OFF.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 5

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FET BF1205

DYNAMIC CHARACTERISTICS AMPLIFIER a

Common source; T

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

y

 forward transfer admittance Tj=25C263140mS

fs

C C C C G

ig1-ss ig2-ss oss rss tr

input capacitance at gate 1 f = 1 MHz  1.8 2.3 pF input capacitance at gate 2 f = 1 MHz  3.3  pF output capacitance f = 1 MHz  0.75  pF reverse transfer capacitance f = 1 MHz  20  fF power gain f = 200 MHz; GS=2mS; BS=B

NF noise figure f = 10.7 MHz; G

X

mod

cross-modulation input level for k = 1% at 0 dB AGC;

=25C; V

amb

=4V; VDS=5V; ID= 12 mA; note 1

G2-S

=0.5mS; BL=B

G

L

f=400MHz; G G

=1mS; BL=B

L

f=800MHz; G

=1mS; BL=B

G

L

f=400MHz; Y f=800MHz; Y

=50MHz; f

f

w

=2mS; BS=B

S

= 3.3 mS; BS=B

S

S S=YS(opt) S=YS(opt)

unw

input level for k = 1% at 10 dB AGC;

=50MHz; f

f

w

unw

input level for k = 1% at 40 dB AGC; f

=50MHz; f

w

unw

;

S(opt)

L(opt)

S(opt)

L(opt)

S(opt)

L(opt)

31 35 39 dB

;

27 31 35 dB

;

22 26 30 dB

=20mS; BS=0  4  dB

 1.1 1.7 dB  1.2 1.9 dB

90 dBV

= 60 MHz; note 2

 90  dBV

= 60 MHz; note 2

98 102  dBV

= 60 MHz; note 2

Notes

1. For the MOS-FET not in use: V

2. Measured in Fig.13 test circuit.

(b) = 0 V; VDS(b) = 0 V.

G1-S

2003 Sep 30 6

NXP Semiconductors Product specification

handbook, halfpage

02

0

5

10

15

20

0.4 0.8 1.2 1.6 V

G1-S

(V)

I

D

(mA)

MGX432

(7)

(6)

(5)

(4)

(1)

(2)

(3)

Fig.5 Transfer characteristics; typical values;

amplifier a.

VDS(a) = 5 V; V

G1-S

(b) = VDS(b) = 0 V; Tj=25C.

(1) V

G2-S

=4V.

(2) V

G2-S

=3.5V.

(3) V

G2-S

=3V.

(4) V

G2-S

=2.5V.

(5) V

G2-S

=2V.

(6) V

G2-S

=1.5V.

(7) V

G2-S

=1V.

handbook, halfpage

010

24

0

8

16

2

VDS (V)

I

D

(mA)

648

MGX433

(7)

(6)

(5)

(4)

(3)

(2)

(1)

Fig.6 Output characteristics; typical values;

amplifier a.

V

G2-S

=4V; V

G1-S

(b) = VDS(b) = 0 V; Tj=25C.

(1) V

G1-S

(a) = 1.4 V.

(2) V

G1-S

(a) = 1.3 V.

(3) V

G1-S

(a) = 1.2 V.

(4) V

G1-S

(a) = 1.1 V.

(5) V

G1-S

(a) = 1 V.

(6) V

G1-S

(a) = 0.9 V.

(7) V

G1-S

(a) = 0.8 V.

Dual N-channel dual gate MOS-FET BF1205

GRAPHS FOR AMPLIFIER a

2003 Sep 30 7

NXP Semiconductors Product specification

handbook, halfpage

0

ID (mA)

420

40

30

10

0

20

81216

MGX434

y

fs

(mS)

(5)

(4)

(3)

(2)(1)

Fig.7 Forward transfer admittance as a function

of drain current; typical values; amplifier a.

VDS(a) = 5 V; V

G1-S

(b) = VDS(b) = 0 V; Tj=25C.

(1) V

G2-S

=4V.

(2) V

G2-S

=3.5V.

(3) V

G2-S

=3V.

(4) V

G2-S

=2.5V.

(5) V

G2-S

=2V.

handbook, halfpage

01020 40

12

0

30

ID (b) (μA)

ID (a)

(mA)

8

4

MGX435

Fig.8 Drain current as a function of internal G1

current (current in pin drain (b) if MOS-FET (b) is switched off); typical values; amplifier a.

VDS(a) = 5 V; V

G2-S

=4V; VDS(b) = 5 V; V

G1-S

(b) = 0 V; Tj=25C.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 8

NXP Semiconductors Product specification

handbook, halfpage

0

12

0

4

2

6

8

10

246

VGG = VDS (V)

I

D

(mA)

MGX436

(5)

(4)

(3)

(2)

(1)

Fig.9 Drain current as a function of gate 2 and

drain supply voltage; typical values; amplifier a.

VDS(a) = 5 V; V

G1-S

(b) = 0 V; Gate 1 (a) = open; Tj=25C.

(1) V

DS

(b) = 5 V. (2) VDS(b) = 4.5 V. (3) VDS(b) = 4 V.

(4) VDS(b) = 3.5 V. (5) VDS(b) = 3 V.

handbook, halfpage

0

gain reduction (dB)

60

120

110

90

80

100

20 40

MGX437

V

unw

(dBμV)

Fig.10 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical values; amplifier a.

VDS(a) = VDS(b) = 5 V; V

G1-S

(b) = 0 V; fw=50MHz;

f

unw

=60MHz; T

amb

=25C; see Fig.13.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 9

NXP Semiconductors Product specification

handbook, halfpage

012 4

0

60

3

V

AGC

(V)

gain

reduction

(dB)

20

40

MGX438

Fig.11 Gain reduction as a function of AGC

voltage; typical values; amplifier a.

VDS(a) = VDS(b) = 5 V; V

G1-S

(b) = 0 V; f = 50 MHz; see Fig.13.

handbook, halfpage

0

gain reduction (dB)

60

16

12

4

0

8

20 40

MGX439

I

D

(mA)

Fig.12 Drain current as a function of gain

reduction; typical values; amplifier a.

VDS(a) = VDS(b) = 5 V; V

G1-S

(b) = 0 V; f = 50 MHz; T

amb

=25C;

see Fig.13.

handbook, full pagewidth

L2

2.2 μH

R

G1

150 kΩ

10 kΩ

R

GEN 50 Ω

V

i

L1

2.2 μH

MGX440

d (a)

s

d (b)

g1 (a)

g2

g1 (b)

4.7 nF

BF1205

4.7 nF

R

L

50 Ω

VDS(a)

5 V

VDS(b)

5 V

V

GG

0 V

V

AGC

Fig.13 Cross-modulation test set-up for amplifier a.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 10

NXP Semiconductors Product specification

handbook, halfpage

MGX441

10

2

10

1

10

2

10

3

f (MHz)

10

−

2

10

−

1

y

is

(mS)

g

is

b

is

Fig.14 Input admittance as a function of frequency;

typical values; amplifier a.

VDS(a) = 5 V; V

G2-S

(a) = 4 V; VDS(b) = V

G1-S

(b) = 0 V;

I

D

(a) = 12 mA.

handbook, halfpage

MGX442

10

2

10

1

−10

2

−10

−1

10 10

2

10

3

f (MHz)

|

y

fs

|

(mS)

ϕ

fs

(deg)

ϕ

fs

|

y

fs

|

Fig.15 Forwa rd transfer admittance and phase as

a function of frequency; typical values; amplifier a.

VDS(a) = 5 V; V

G2-S

(a) = 4 V; VDS(b) = V

G1-S

(b) = 0 V;

I

D

(a) = 12 mA.

handbook, halfpage

MGX443

10

3

10

2

10

1

10

2

10

3

f (MHz)

−10

2

−10

−1

ϕ

rs

(deg)

−10

3

|

y

rs

|

(μS)

ϕ

rs

|

y

rs

|

Fig.16 Reverse transfer admittance and phase as

a function of frequency; typical values; amplifier a.

VDS(a) = 5 V; V

G2-S

(a) = 4 V; VDS(b) = V

G1-S

(b) = 0 V;

I

D

(a) = 12 mA.

handbook, halfpage

MGX444

10

1

10

2

10

3

f (MHz)

10

−

2

10

−

1

y

os

(mS)

g

os

b

os

Fig.17 Output admittance as a function of

frequency; typical values; amplifier a.

VDS(a) = 5 V; V

G2-S

(a) = 4 V; VDS(b) = V

G1-S

(b) = 0 V;

I

D

(a) = 12 mA.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 11

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FET BF1205

Scattering parameters: amplifier a

V

(a) = 5 V; V

DS

=4V; ID(a) = 12 mA; VDS(b) = 0 V; V

G2-S

(b) = 0 V; T

G-1S

amb

=25C

f

(MHz)

s

11

MAGNITUDE

(ratio)

ANGLE

(deg)

MAGNITUDE

(ratio)

s

21

ANGLE

(deg)

s

12

MAGNITUDE

(ratio)

ANGLE

(deg)

s

22

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.997 3.70 3.15 175.99 0.00067 86.39 0.992 1.38

100 0.995 7.37 3.15 171.92 0.00132 84.34 0.991 2.83

200 0.988 14.64 3.12 163.99 0.00262 79.71 0.990 5.62 300 0.976 21.85 3.09 156.06 0.00373 75.29 0.988 8.40 400 0.963 28.95 3.04 148.32 0.00471 71.43 0.985 11.15 500 0.944 35.98 2.99 140.52 0.00557 66.89 0.982 13.88 600 0.924 42.90 2.94 132.88 0.00624 63.52 0.978 16.65 700 0.900 49.77 2.87 125.30 0.00669 60.09 0.975 19.35 800 0.874 56.61 2.81 117.79 0.00701 59.58 0.972 22.08 900 0.846 63.18 2.73 110.29 0.00705 52.42 0.968 24.87

1000 0.817 69.84 2.65 102.91 0.00688 49.17 0.965 27.63

Noise data

V

(a) = 5 V; V

DS

f

(MHz)

=4V; ID(a) = 12 mA; VDS(b) = 0 V; V

G2-S

F MIN

(dB)

(b) = 0 V; T

G-1S

amb

=25C

GAMMA OPT

(ratio) (deg)

Rn ()

400 1.1 0.719 16.16 31.18 800 1.2 0.628 32.7 29.74

DYNAMIC CHARACTERISTICS AMPLIFIER b

Common source; T

=25C; V

amb

=4V; VDS=5V; ID=12mA

G2-S

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

 forward transfer admittance Tj=25C263140mS

y

fs

C

ig1-ss

C

ig2-ss

C

oss

C

rss

G

tr

NF noise figure f = 10.7 MHz; G

input capacitance at gate 1 f = 1 MHz  2.0 2.5 pF input capacitance at gate 2 f = 1 MHz  3.3  pF output capacitance f = 1 MHz  0.85  pF reverse transfer capacitance f = 1 MHz  20  fF power gain f = 200 MHz; GS=2mS; BS=B

=0.5mS; BL=B

G

L

f=400MHz; G G

=1mS; BL=B

L

f=800MHz; G

=1mS; BL=B

G

L

f=400MHz; Y f=800MHz; Y

=2mS; BS=B

S

= 3.3 mS; BS=B

S

S S=YS(opt) S=YS(opt)

; note 1

L(opt)

; note 1

L(opt)

; note 1

L(opt)

=20mS; BS=0  4  dB

S(opt)

30 34 38 dB

;

27 31 35 dB

22 26 30 dB

;

 1.3 1.9 dB  1.4 2.1 dB

2003 Sep 30 12

NXP Semiconductors Product specification

handbook, halfpage

02

0

5

10

15

20

0.4 0.8 1.2 1.6 V

G1-S

(V)

I

D

(mA)

MGX445

(6)

(7)

(5)

(4)

(1)

(2)

(3)

Fig.18 Transf er characteristics; typical values;

amplifier b.

VDS(b) = 5 V; VDS(a) = V

G1-S

(a) = 0 V; Tj=25C.

(1) V

G2-S

=4V.

(2) V

G2-S

=3.5V.

(3) V

G2-S

=3V.

(4) V

G2-S

=2.5V.

(5) V

G2-S

=2V.

(6) V

G2-S

=1.5V.

(7) V

G2-S

=1V.

handbook, halfpage

010

24

0

8

16

2

VDS (V)

I

D

(mA)

648

MGX446

(6)

(7)

(5)

(4)

(3)

(2)

(1)

Fig.19 Output characteristics; typical values;

amplifier b.

V

G2-S

=4V; VDS(a) = V

G1-S

(a) = 0 V; Tj=25C.

(1) V

G1-S

(b) = 1.4 V.

(2) V

G1-S

(b) = 1.3 V.

(3) V

G1-S

(b) = 1.2 V.

(4) V

G1-S

(b) = 1.1 V.

(5) V

G1-S

(b) = 1 V.

(6) V

G1-S

(b) = 0.9 V.

(7) V

G1-S

(b) = 0.8 V.

Dual N-channel dual gate MOS-FET BF1205

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

X

mod

cross-modulation input level for k = 1% at 0 dB AGC;

Notes

1. For the MOS-FET not in use: V

2. Measured in test circuit Fig.30.

GRAPHS FOR AMPLIFIER b

f

w

input level for k = 1% at 10 dB AGC; f

w

input level for k = 1% at 40 dB AGC; f

w

(a) = 0; VDS(a) = 0.

G1-S

=50MHz; f

= 60 MHz; note 2

unw

= 60 MHz; note 2

unw

= 60 MHz; note 2

unw

90 dBV

 92  dBV

100 105  dBV

2003 Sep 30 13

NXP Semiconductors Product specification

handbook, halfpage

0 0.80.4 1.61.2 2

60

20

0

40

MGX447

V

G1-S

(V)

I

G1

(μA)

(7)

(5)

(4)

(6)

(3)(2)

(1)

Fig.20 Gate 1 current as a function of gate 1

voltage; typical values; amplifier b.

VDS(b) = 5 V; VDS(a) = V

G1-S

(a) = 0 V; Tj=25C.

(1) V

G2-S

=4V.

(2) V

G2-S

=3.5V.

(3) V

G2-S

=3V.

(4) V

G2-S

=2.5V.

(5) V

G2-S

=2V.

(6) V

G2-S

=1.5V.

(7) V

G2-S

=1V.

handbook, halfpage

0

ID (mA)

420

40

30

10

0

20

81216

MGX448

y

fs

(mS)

(5)

(4)

(3)

(2)(1)

Fig.21 Forward transfer admittance as a function

of drain current; typical values; amplifier b.

VDS(b) = 5 V; VDS(a) = V

G1-S

(a) = 0 V; Tj=25C.

(1) V

G2-S

=4V.

(2) V

G2-S

=3.5V.

(3) V

G2-S

=3V.

(4) V

G2-S

=2.5V.

(5) V

G2-S

=2V.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 14

NXP Semiconductors Product specification

handbook, halfpage

050

20

0

4

8

12

16

10 20 30 40

IG1 (μA)

I

D

(mA)

MGX449

Fig.22 Drain current as a function of gate 1 current;

typical values; amplifier b.

VDS(b) = 5 V; V

G2-S

=4V; VDS(a) = V

G1-S

(a) = 0 V; Tj=25C.

handbook, halfpage

0

VGG (V)

15

16

12

4

0

8

23 4

MGX450

I

D

(mA)

Fig.23 Drain current as a function of gate 1 supply

voltage (V

GG

); typical values; amplifier b.

VDS(b) = 5 V; V

G2-S

=4V; VDS(a) = V

G1-S

(a) = 0 V;

T

j

=25C; RG1(b) = 150 k (connected to VGG); see Fig.4.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 15

NXP Semiconductors Product specification

handbook, halfpage

0246

VGG = VDS (V)

I

D

(mA)

20

0

16

12

8

4

MGX451

(6) (7)

(8)

(5)

(4)

(3)

(2)

(1)

Fig.24 Drain current as a function of gate 1 (VGG)

and drain supply voltage; typical values; amplifier b.

V

G2-S

=4V; VDS(a) = V

G1-S

(a) = 0 V; Tj=25C;

R

G1

(b) = 150 k (connected to VGG); see Fig.4.

(1) R

G1

(b) = 68 k. (2) RG1(b) = 82 k. (3) RG1(b) = 100 k. (4) RG1(b) = 120 k.

(5) RG1(b) = 150 k. (6) RG1(b) = 180 k. (7) RG1(b) = 220 k. (8) RG1(b) = 270 k.

handbook, halfpage

0246

16

12

4

0

8

MGX452

V

G2-S

(V)

I

D

(mA)

(5)

(4)

(3)

(2)

(1)

Fig.25 Drain current as a function of gate 2

voltage; typical values; amplifier b.

VDS(b) = 5 V; VDS(a) = V

G1-S

(a) = 0 V; Tj=25C;

R

G1

(b) = 150 k (connected to VGG); see Fig.4.

(1) V

GG

=5.0V. (2) VGG=4.5V. (3) VGG=4.0V.

(4) VGG=3.5V. (5) VGG=3.0V.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 16

NXP Semiconductors Product specification

handbook, halfpage

0246

30

10

0

20

MGX453

V

G2-S

(V)

I

G1

(μA)

(5)

(4)

(3)

(2)

(1)

Fig.26 Gate 1 current as a function of gate 2

voltage; typical values; amplifier b.

VDS(b) = 5 V; VDS(a) = V

G1-S

(a) = 0 V; Tj=25C;

R

G1

(b) = 150 k (connected to VGG); see Fig.4.

(1) V

GG

=5.0V. (2) VGG=4.5V. (3) VGG=4.0V.

(4) VGG=3.5V. (5) VGG=3.0V.

handbook, halfpage

0

gain reduction (dB)

60

120

110

90

80

100

20 40

MGX454

V

unw

(dBμV)

Fig.27 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical values; amplifier b.

VDS(b) = 5 V; VGG=5V; VDS(a) = V

G1-S

(a) = 0 V;

R

G1

(b) = 150 k (connected to VGG); fw=50MHz;

f

unw

=60MHz; T

amb

=25C; see Fig.30.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 17

NXP Semiconductors Product specification

handbook, halfpage

012 4

0

60

3

V

AGC

(V)

gain

reduction

(dB)

20

40

MGX455

Fig.28 Typical gain reduction as a function of AGC

voltage; amplifier b.

VDS(b) = 5 V; VGG=5V; VDS(a) = V

G1-S

(a) = 0 V;

R

G1

(b) = 150 k (connected to VGG); f = 50 MHz;

T

amb

=25C; see Fig.30.

handbook, halfpage

0

gain reduction (dB)

60

16

12

4

0

8

20 40

MGX456

I

D

(mA)

Fig.29 Drain current as a function of gain

reduction; typical values; amplifier b.

VDS(b) = 5 V; VGG=5V; VDS(a) = V

G1-S

(a) = 0 V;

R

G1

(b) = 150 k (connected to VGG); f = 50 MHz;

T

amb

=25C; see Fig.30.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 18

NXP Semiconductors Product specification

handbook, full pagewidth

L2

2.2 μH

R

G1

150 kΩ

10 kΩ

L1

2.2 μH

MDB813

d (a)

s

d (b)

g1 (a)

g2

g1 (b)

4.7 nF

BF1205

4.7 nF

R

L

50 Ω

R

GEN 50 Ω

V

i

50 Ω

VDS(a)

5 V

VDS(b)

5 V

V

GG

5 V

V

AGC

Fig.30 Cross-modulation test set-up for amplifier b.

handbook, halfpage

MGX457

10

2

10

1

10

2

10

3

f (MHz)

10

−

1

y

is

(mS)

g

is

b

is

Fig.31 Input admittance as a function of frequency;

typical values; amplifier b.

VDS(b) = 5 V; V

G2-S

=4V; VDS(a) = V

G1-S

(a) = 0 V;

I

D

(b)= 12 mA.

handbook, halfpage

MGX458

10

2

10

1

−10

2

−10

−1

10 10

2

10

3

f (MHz)

|

y

fs

|

(mS)

ϕ

fs

(deg)

ϕ

fs

|

y

fs

|

Fig.32 Forwa rd transfer admittance and phase as

a function of frequency; typical values; amplifier b.

VDS(b) = 5 V; V

G2-S

=4V; VDS(a) = V

G1-S

(a) = 0 V;

I

D

(b) = 12 mA.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 19

NXP Semiconductors Product specification

handbook, halfpage

MGX459

10

3

10

2

10

1

10

2

10

3

f (MHz)

−10

2

−10

−1

ϕ

rs

(deg)

−10

3

|

y

rs

|

(μS)

|

y

rs

|

ϕ

rs

Fig.33 Reverse transfer admittance and phase as

a function of frequency; typical values; amplifier b.

VDS(b) = 5 V; V

G2-S

=4V; VDS(a) = V

G1-S

(a) = 0 V;

I

D

(b) = 12 mA.

handbook, halfpage

MGX460

10

1

10

2

10

3

f (MHz)

10

−

2

10

−

1

y

os

(mS)

g

os

b

os

Fig.34 Output admittance as a function of

frequency; typical values; amplifier b.

VDS(b) = 5 V; V

G2-S

=4V; VDS(a) = V

G1-S

(a) = 0 V;

I

D

(b) = 12 mA.

Dual N-channel dual gate MOS-FET BF1205

2003 Sep 30 20

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FET BF1205

Scattering parameters: amplifier b

V

(b) = 5 V; V

DS

=4V; ID(b) = 12 mA; VDS(a) = 0 V; V

G2-S

(a) = 0 V; T

G1-S

amb

=25C

f

(MHz)

s

11

MAGNITUDE

(ratio)

ANGLE

(deg)

s

21

MAGNITUDE

(ratio)

ANGLE

(deg)

MAGNITUDE

(ratio)

s

12

ANGLE

(deg)

s

22

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.987 3.76 3.12 175.87 0.00071 85.43 0.991 1.56

100 0.985 7.38 3.11 171.77 0.00136 86.06 0.989 3.11

200 0.978 14.63 3.09 163.72 0.00272 84.25 0.988 6.16 300 0.968 21.82 3.06 155.67 0.00396 82.63 0.986 9.17 400 0.956 28.92 3.01 147.79 0.00509 81.35 0.983 12.17 500 0.941 35.99 2.95 139.86 0.00616 79.46 0.973 15.16 600 0.924 42.93 2.89 132.06 0.00710 78.57 0.975 18.15 700 0.905 49.89 2.83 124.31 0.00791 77.88 0.972 21.07 800 0.884 56.57 2.75 116.69 0.00848 76.72 0.968 24.08 900 0.861 63.36 2.67 108.97 0.00900 76.55 0.964 27.03

1000 0.837 70.05 2.59 101.39 0.00941 76.67 0.959 30.02

Noise data

V

(b) = 5 V; V

DS

=4V; ID(b) = 12 mA; VDS(a) = 0 V; V

G2-S

(a) = 0 V; T

G1-S

amb

=25C

F MIN

f

(MHz)

F MIN

(dB)

R

()

n

(ratio) (deg)

400 1.3 0.662 16.76 31.55 800 1.4 0.578 33.97 30.53

2003 Sep 30 21

NXP Semiconductors Product specification

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT363 SC-88

wBM

b

p

D

e

1

e

pin 1 index

A

1

L

p

Q

detail X

H

E

v M

A

AB

y

0 1 2 mm

scale

c

X

132

456

Plastic surface-mounted package; 6 leads SOT363

UNIT

A

1

max

b

p

cD

E

e

1

H

E

L

p

Qywv

mm

0.1

0.30

0.20

2.2

1.8

0.25

0.10

1.35

1.15

0.65

e

1.3

2.2

2.0

0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15

0.25

0.15

A

1.1

0.8

04-11-08 06-03-16

Dual N-channel dual gate MOS-FET BF1205

PACKAGE OUTLINE

2003 Sep 30 22

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FET BF1205

DATA SHEET STATUS

DOCUMENT

STATUS

Objective data sheet Development This document contains data from the objective specification for product

Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification.

Notes

1. Please consult the most recently issued document before initiating or completing a design.

2. The product status of device(s) desc ribed in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

DEFINITIONS Product specification  The information and data

provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

DISCLAIMERS Limited warranty and liability  Information in this

document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

(1)

PRODUCT

STATUS

(2)

DEFINITION

development.

Right to make changes  NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication he reof.

Suitability for use  NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications wher e failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inc l usion and/or use is at the customer’s own risk.

Applications  Applications that ar e described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the ris ks associated with their applications and products.

2003 Sep 30 23

NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FET BF1205

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applicat ions and products using NXP Semiconductors products in or de r to avoid a default of the applications and the prod ucts or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values  Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Rec ommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale  NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In cas e an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

Export control  This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

Quick reference data  The Quick reference data is an extract of the product data given in t he Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products  Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with auto motive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from cus tom er d esign and use o f the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

No offer to sell or license  Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights .

2003 Sep 30 24

NXP Semiconductors

provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.

Contact information

For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected]

The information presented in this document does not form part of any quotation or cont ra ct, is believed to be accurate and reliable and may be change d without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands R77/01/pp25 Date of release: 2003 Sep 30