Philips bf1204 Datasheet

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DATA SH EET

DISCRETE SEMICONDUCTORS

MBD128

BF1204

Dual N-channel dual gate MOS-FET

Product specification Supersedes data of 2001 Apr 25

2010 Sep 16

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NXP Semiconductors Product specification

handbook, halfpage

MBL252

AMP

d (a) s d (b)

g1 (a)

Top view

g2 g1 (b)

132

Fig.1 Simplified outline and symbol.

Marking code: L3* * = - : made in Hong Kong

* = p : made in Hong Kong * = t : made in Malaysia

Dual N-channel dual gate MOS-FET BF1204

FEATURES

 Two low noise gain controlled amplifiers in a single

package

 Superior cross-modulation performance during AGC  High forward transfer admittance  High forward transfer admittance to input capacitance

ratio.

APPLICATIONS

 Gain controlled low noise amplifiers for VHF and UHF

applications with 3 to 9 V supply voltage, such as digital and analog television tuners and professional communications equipment.

DESCRIPTION

The BF1204 is a combination of two equal dual gate MOS-FET amplifiers with shared source and gate 2 leads. The source and substrate are interconnected. Internal bias circuits enable DC stabilization and a very good cross-modulation performance during AGC. Integrated diodes between the gates and source protect ag ainst excessive input voltage surges. The transistor has a SOT363 micro-miniature plastic package.

PINNING - SOT363

PIN DESCRIPTION

1gate1(a) 2gate2 3gate1(b) 4 drain (b) 5 source 6 drain (a)

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Per MOS-FET; unless otherw ise specified

tot

 forward transfer admittance ID=12mA; f=1MHz 25 30 40 mS

y

ig1-s

rss

drain-source voltage 10 V drain current (DC) 30 mA total power dissipation Ts 102 C; note 1 200 mW

input capacitance at gate 1 ID=12mA; f=1MHz  1.7 2.2 pF

reverse transfer capacitance f = 1 MHz  15  fF NF noise figure f = 800 MHz  1.1 1.8 dB X

mod

cross-modulation input level for k = 1% at 40 dB AGC 100 105  dBV

operating junction temperature 150 C

Note

is the temperature at the soldering point of the source lead.

1. T

CAUTION

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling.

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NXP Semiconductors Product specification

handbook, halfpage

0 50 100 200

250

200

MGS359

150

100

Ts (°C)

tot

(mW)

Fig.2 Power derating curve.

Dual N-channel dual gate MOS-FET BF1204

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Per MOS-FET; unless otherw ise specified

tot

stg

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

th j-s

drain-source voltage  10 V

drain current (DC)  30 mA

gate 1 curren t 10 mA

gate 2 curren t 10 mA

total power dissipation Ts 102 C  200 mW

storage temperature 65 +150 C

operating junction temperature  150 C

thermal resistance from junction to soldering point 240 K/W

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Dual N-channel dual gate MOS-FET BF1204

STATIC CHARACTERISTICS

=25C; per MOS-FET; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

(BR)DSS

(BR)G1-SS

(BR)G2-SS

(F)S-G1

(F)S-G2

G1-S(th)

G2-S(th)

DSX

G1-S

G2-S

Note

1. R

drain-source breakdown voltage V

gate-source breakdown voltage VGS=VDS=0; I

forward source-gate voltage V

gate-source threshold voltage VDS=5V; V

drain-source current V

gate cut-off current V

connects gate 1 to VGG=5V.

G1-S=VG2-S

G2-S=VDS G1-S=VDS

=4V; VDS=5V; RG= 120 k; note 1 8 16 mA

G2-S

=5V; V

G1-S

=4V; V

G2-S

=0; ID=10A10 V

=10mA 6 10 V

G1-S

=10mA 6 10 V

G2-S

=0; I =0; I

G2-S G1-S

G2-S=VDS G1-S=VDS

=10mA 0.5 1.5 V

S-G1

=10mA 0.5 1.5 V

S-G2

=4V; ID=100A0.31V =4V; ID=100A0.31.2V

=0  50 nA =0  20 nA

DYNAMIC CHARACTERISTICS

Common source; T

=25C; V

amb

=4V; VDS=5V; ID= 12 mA; per MOS-FET

G2-S

(1)

; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

 forward transfer admittance Tj=25C 253040mS

y

ig1-ss

ig2-ss

oss

rss

NF noise figure f = 10.7 MHz; G

mod

input capacitance at gate 1 f = 1 MHz  1.7 2.2 pF

input capacitance at gate 2 f = 1 MHz  3.3  pF

output capacitance f = 1 MHz  0.85  pF

reverse transfer capacitance f = 1 MHz  15  fF

power gain f = 200 MHz; GS=2mS; BS=B

= 0.5 mS; BL=B

f=400MHz; G

=1mS; BL=B

f=800MHz; G

=1mS; BL=B

f=400MHz; Y f=800MHz; Y

=2mS; BS=B

= 3.3 mS; BS=B

S S=YS(opt) S=YS(opt)

; note 1

L(opt)

; note 1

L(opt)

; note 1

L(opt)

=20mS; BS=0  911dB

S(opt)

cross-modulation input level for k = 1% at 0 dB AGC;

=50MHz; f

=60MHz; note2

unw

input level for k = 1% at 10 dB AGC;

=50MHz; f

=60MHz; note2

unw

input level for k = 1% at 40 dB AGC; f

=50MHz; f

=60MHz; note2

unw

30 34 38 dB

;

26 30 34 dB

;

21 25 29 dB

;

 0.9 1.5 dB  1.1 1.8 dB 90 dBV

 92  dBV

100 105  dBV

Notes

1. For the MOS-FET not in use: V

=0; VDS=0.

G1-S

2. Measured in Fig.19 test circuit.

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0.4 0.8 1.2 1.6 V

G1-S

(V)

(mA)

MCD952

G2-S

= 4 V

2.5 V

3.5 V 3 V

2 V

1.5 V

1 V

Fig.3 Transfer characteristics; typical values.

VDS=5V. Tj=25C.

handbook, halfpage

010

VDS (V)

(mA)

648

MCD953

G1-S

= 1.5 V

1.4 V

1.2 V

1.3 V

1.1 V 1 V

0.9 V

Fig.4 Output characteristics; typical values.

G2-S

=4V.

Tj=25C.

handbook, halfpage

0 2.5

100

0.5 1 1.5 2 V

G1-S

(V)

(μA)

MCD954

G2-S

= 4 V

3.5 V 3 V

2.5 V

2 V

1.5 V 1 V

Fig.5 Gate 1 current as a function of gate 1

voltage; typical values.

VDS=5V. T

=25C.

VDS=5V. T

=25C.

handbook, halfpage

ID (mA)

420

81216

MCD955

(mS)

3.5 V

2.5 V

3 V

2 V

G2-S

= 4 V

Fig.6 Forward transfer admittanc e as a function

of drain current; typical values.

VDS=5V. T

=25C.

Dual N-channel dual gate MOS-FET BF1204

ALL GRAPHS FOR ONE MOS-FET

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050

10 20 30 40

IG1 (μA)

(mA)

MCD956

Fig.7 Drain current as a function of gate 1 current;

typical values.

VDS=5V; V

G2-S

=4V.

Tj=25C.

handbook, halfpage

VGG (V)

23 4

MCD957

(mA)

Fig.8 Drain current as a function of gate 1 supply

voltage (= V

); typical values.

VDS=5V; V

G2-S

=4V; Tj=25C.

RG1=120k (connected to VGG); see Fig.19.

handbook, halfpage

0246

VGG = VDS (V)

(mA)

MCD958

= 68 kΩ

82 kΩ

100 kΩ 120 kΩ

150 kΩ

220 kΩ

180 kΩ

Fig.9 Drain current as a function of gate 1 (= VGG)

and drain supply voltage; typical values.

G2-S

=4V; Tj=25C.

connected to VGG; see Fig.19.

handbook, halfpage

0246

MCD959

G2-S

(V)

(mA)

4.5 V 4 V

3 V

= 5 V

3.5 V

VDS=5V; Tj=25C. RG1=120k (connected to VGG); see Fig.19.

Fig.10 Drain current as a function of gate 2

voltage; typical values.

Dual N-channel dual gate MOS-FET BF1204

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0246

MCD960

G2-S

(V)

(μA)

4 V

3.5 V 3 V

4.5 V

= 5 V

Fig.11 Gate 1 current as a func tion of gate 2

voltage; typical values.

VDS=5V; Tj=25C. RG1=120k (connected to VGG); see Fig.19.

handbook, halfpage

012 4

−50

−10

AGC

(V)

gain

reduction

(dB)

−20

−30

−40

MCD961

Fig.12 Typical gain reduction as a function of AGC

voltage; see Fig.19.

VDS=5V; VGG=5V; RG1= 120 k; f = 50MHz; T

amb

=25C.

handbook, halfpage

gain reduction (dB)

10 50

120

110

100

20 30 40

MCD962

unw

(dBμV)

Fig.13 Unwanted voltage for 1% cross-modulation

as a function of gain reduction; typical values; see F ig.19.

VDS=5V; VGG=5V; RG1= 120 k; f= 50 MHz; f

unw

=60MHz; T

amb

=25C.

handbook, halfpage

gain reduction (dB)

10 50

20 30 40

MCD963

(mA)

Fig.14 Drain current as a function of gain

reduction; typical values; see Fig.19.

VDS=5V; VGG=5V; RG1= 120 k; f = 50 MHz; T

amb

=25C.

Dual N-channel dual gate MOS-FET BF1204

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MLD429

f (MHz)

(mS)

−1

Fig.15 Input admittance as a function of frequency;

typical values.

VDS=5V; VG2=4V.

handbook, halfpage

MLD430

f (MHz)

−10

−1

(deg)

(μS)

Fig.16 Reverse transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V.

handbook, halfpage

−10

−1

MLD431

10 10

f (MHz)

(mS)

(deg)

Fig.17 Forwa rd transfer admittance and phase as

a function of frequency; typical values.

VDS=5V; VG2=4V.

handbook, halfpage

MLD432

f (MHz)

(mS)

−2

−1

Fig.18 Output admittance as a function of

frequency; typical values.

VDS=5V; VG2=4V.

Dual N-channel dual gate MOS-FET BF1204

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handbook, full pagewidth

DUT

4.7 nF

10 kΩ

MGS315

4.7 nF

≈2.2 μH

4.7 nF

50 Ω

AGC

GEN 50 Ω

50 Ω

4.7 nF

Fig.19 Cross-modulation test set-up (for one MOS-FET).

Dual N-channel dual gate MOS-FET BF1204

Scattering parameters

(MHz)

100 0.987 7.12 2.90 171.61 0.00119 84.74 0.994 2.90

1000 0.817 67.84 2.41 100.24 0.00670 52.16 0.966 27.45

=5V; V

=4V; ID=12mA; T

G2-S

MAGNITUDE

(ratio)

ANGLE

(deg)

=25C.

amb

MAGNITUDE

(ratio)

ANGLE

(deg)

MAGNITUDE

(ratio)

ANGLE

(deg)

MAGNITUDE

(ratio)

ANGLE

(deg)

50 0.991 3.29 2.95 175.78 0.00060 85.25 0.995 1.44

200 0.981 14.21 2.86 163.45 0.00234 80.85 0.992 5.70 300 0.969 21.22 2.83 155.11 0.00339 75.77 0.989 8.50 400 0.958 28.14 2.79 147.37 0.00429 72.23 0.987 11.25 500 0.939 35.01 2.74 139.04 0.00508 68.24 0.983 13.96 600 0.921 41.75 2.68 131.35 0.00565 64.97 0.981 16.67 700 0.898 48.51 2.62 123.38 0.00611 61.90 0.976 19.36 800 0.874 54.96 2.55 115.74 0.00646 57.77 0.973 22.04 900 0.847 61.62 2.49 107.84 0.00662 55.04 0.969 24.80

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NXP Semiconductors Product specification

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT363 SC-88

wBM

pin 1 index

detail X

v M

0 1 2 mm

scale

132

456

Plastic surface-mounted package; 6 leads SOT363

UNIT

max

Qywv

0.1

0.30

0.20

2.2

1.8

0.25

0.10

1.35

1.15

0.65

1.3

2.2

2.0

0.2 0.10.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15

0.25

0.15

1.1

0.8

04-11-08 06-03-16

Dual N-channel dual gate MOS-FET BF1204

PACKAGE OUTLINE

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NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FET BF1204

DATA SHEET STATUS

DOCUMENT

STATUS

Objective data sheet Development This document contains data from the objective s pe cification for product

Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification.

Notes

1. Please consult the most recently issued document before initiating or completing a design.

2. The product status of device(s) desc ribed in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

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document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

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(1)

PRODUCT STATUS

(2)

DEFINITION

development.

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Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the ris ks associated with their applications and products.

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2010 Sep 16 11

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NXP Semiconductors Product specification

Dual N-channel dual gate MOS-FET BF1204

Limiting values  Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Rec ommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

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2010 Sep 16 12

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This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for the marking codes and the package outline drawings which were updated to the latest version.

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Printed in The Netherlands R77/03/pp13 Date of release: 2010 Sep 16